KR102292580B1 - Apparatus and method for managing physical register file of high-performance out-of-order superscalar cores - Google Patents

Abstract

The present invention divides a plurality of instructions applied to the core into instruction blocks according to a predetermined criterion, identifies a non-final write instruction within the divided instruction block, and a logical purpose register of the non-final write instruction identified within the instruction block. By determining a single read command that uniquely performs a read operation on the value written to, the physical register allocated as a physical source register in a single read command determined among multiple physical registers in the physical register file is converted to a physical object register within the same instruction. physical register file of out-of-order execution core that can support a high level of instruction execution performance even with a small-capacity physical register file and increase the effective size of the physical register file to reduce manufacturing cost and power consumption. Management devices and methods may be provided.

Description

APPARATUS AND METHOD FOR MANAGING PHYSICAL REGISTER FILE OF HIGH-PERFORMANCE OUT-OF-ORDER SUPERSCALAR CORES

The present invention relates to an apparatus and method for managing a physical register file, and to an apparatus and method for managing a physical register file of a high-performance out-of-order execution core.

Out-of-order execution (also known as OoOE or out-of-order instruction processing) is a paradigm in which high-performance microprocessors seek to exploit instruction cycles that can be wasted due to certain kinds of delays. Out-of-order execution is a technique that does not process instructions in order to increase instruction execution efficiency, and is currently employed in many processors.

The latest out-of-order execution core architecture has a reorder buffer and a physical register file ( Physical Register File) is being used.

The reorder buffer is a structure that stores all decoded instructions according to the program order, and by committing the instructions that have completed the operation in the original order, the structural state of the core can be updated correctly. To this end, each instruction is allocated a reorder buffer entry in the original order in the dispatch stage before out-of-order execution is performed. That is, every instruction that is executed is allocated a reorder buffer entry until it completes the operation and is committed in the pipeline.

In addition, the physical register file is a structure that stores the result of the instruction that has completed the operation. By allocating a number of physical registers to one logical register, the physical register file is designed to correctly execute out-of-order execution between different instructions that update the same logical register. do. For this purpose, physical registers are allocated in the dispatch stage for all instructions that update logical registers.

In other words, all executed instructions must be allocated a reorder buffer entry until the operation is completed and committed in the pipeline. should be assigned

On the other hand, modern processors use a method of simultaneously executing multiple instructions without data dependency by utilizing the instruction-level parallelism (ILP) inherent in the program to increase the execution performance of the program inside the core. At this time, if the size of the physical register file is small, even if other components can provide parallelism, that is, even if the idle computational resources inside the pipeline are sufficient, the operation result cannot be stored due to the lack of the physical register file, The number of commands that can be executed is limited. As a result, modern processors employ increasingly large physical register files.

However, since the physical register file is accessed at least twice for each instruction by all executed instructions, the larger the size, the greater the number of transistors and power consumption to implement the chip, which has a significant impact on the overall system configuration cost and power efficiency. It can be overhead.

Korean Patent Registration No. 10-1139066 (Registered on April 16, 2012)

It is an object of the present invention to provide a high-level instruction even with a small capacity physical register file by allowing the physical source register of the physical register file to be released early in an instruction according to a predetermined condition and immediately reallocated to the physical destination register within the same instruction. An object of the present invention is to provide an apparatus and method for managing a physical register file that can support execution performance.

Another object of the present invention is to provide an apparatus and method for managing a physical register file, which can reduce manufacturing cost and power consumption by increasing the effective size of the physical register file by early release and reallocation of the physical register of the physical register file. have.

In order to achieve the above object, an apparatus for managing a physical register file of an out-of-order execution core according to an embodiment of the present invention divides a plurality of instructions applied to the core into instruction blocks according to a predetermined criterion, and Identifies a non-final write command in the command block and determines a single read command that uniquely performs a read operation on the value written to the logical purpose register of the non-final write command identified within the instruction block, so that multiple physical A physical register allocated as a physical source register in a single read instruction determined among registers is reallocated as a physical destination register in the same instruction.

The physical register file management apparatus searches for a branch instruction among the plurality of instructions, divides the plurality of instructions into the instruction block based on the searched branch instruction, and performs a final write operation among the plurality of instructions in the instruction block. a block setting unit for identifying a write command; and a physical object that is a physical register of a physical register file allocated to a logical object register of the non-final write instruction by identifying a non-final write instruction for performing a write operation within a command block in addition to the last write instruction identified in the block setting unit A single read command for reading a value written to the physical source register is determined using the register as a physical source register, and when a read operation is performed on the value of the physical source register in the determined single read command, the physical source register is released early and a handover unit for reallocating a physical object register in which an operation result of the single read command is stored.

The handover unit receives an instruction in which a plurality of instructions applied to the core are decoded by an opcode and a logical source register and logical destination register address, and a physical register file is stored in a logical source register and a logical destination register of the decoded instruction, respectively. A register may be allocated as a physical source register and a physical object register, but for the single read instruction, a renamed instruction may be obtained by allocating the same physical register to one of the physical source registers and the physical object register.

When the core dispatches the renamed instruction and the value stored in the physical source register of the single read instruction is transferred to an operation execution unit that performs an operation on the instruction, the core immediately releases the physical source register and executes the operation It may further include an instruction issue unit for issuing a negative issue so that the operation execution result of the operation execution unit is stored in a released physical source register.

The physical register file management apparatus includes: a block history table storing at least one instruction block as an entry; and a block order queue that monitors whether the instructions included in the instruction block are normally executed in the core, and when it is determined that all instructions are normally executed, commits and approves all instructions corresponding to the instruction block. have.

The block setting unit includes a block definer indicating a memory address for a first instruction among a plurality of instructions included in an instruction block, a last write indicator indicating location information of an instruction performing a final write operation among a plurality of instructions, and a location of a branch instruction; When a branch indicator indicating a predicted branch path is included in the information of the instruction block and stored in the entry of the block history table, and from the block order queue, when consecutive commits are approved for more than a predetermined reference commit number of consecutive identical instruction blocks , it is possible to merge adjacent instruction blocks, and restore information of the merged instruction blocks to the block history table.

When it is determined that an error has occurred in at least one of the instructions of the instruction block, the block order queue may transmit location information of the instruction in which an error occurs in the instruction block to the block setting unit.

The block setting unit divides two instruction blocks based on a branch instruction before an error occurred instruction based on the location information of the instruction in which the error occurred transmitted from the block order queue, and divides the information of the divided instruction block into the block It can be restored to the history table.

In a method for managing a physical register file of an out-of-order execution core according to another embodiment of the present invention for achieving the above other object, a plurality of instructions applied to the core are divided into instruction blocks according to a predetermined criterion, and the divided instruction blocks identifying a non-final write command in the command block, and determining a single read command that uniquely performs a read operation on a value written to a logical object register of the non-last write command identified in the instruction block; and reallocating a physical register allocated as a physical source register in a determined single read instruction among a plurality of physical registers of the physical register file to a physical destination register in the same instruction.

Accordingly, the apparatus and method for managing a physical register file of an out-of-order execution core according to an embodiment of the present invention utilize the characteristics of a program in which instructions are repeatedly executed, group a plurality of instructions into instruction blocks, and write in each instruction block. Physical source registers are released early for instructions according to specified conditions and are immediately reallocated to physical destination registers within the same instruction, so that even a small size physical register file can be managed to support a high level of instruction execution performance. have. Accordingly, it is possible to increase the effective size of the physical register file, thereby reducing manufacturing cost and power consumption.

1 shows a schematic structure of an out-of-order execution core according to an embodiment of the present invention.
FIG. 2 shows an example of early release and reallocation of physical registers to increase the effective size of a physical register file in the out-of-order execution core of FIG. 1 .
FIG. 3 shows another example of early release and reallocation of physical registers to increase the effective size of the physical register file in the out-of-order execution core of FIG. 1 .
FIG. 4 is a diagram for explaining a process of merging or dividing command blocks by the block setting unit of FIG. 1 .
5 illustrates a method for managing a physical register file of an out-of-order execution core according to an embodiment of the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be embodied in various different forms, and is not limited to the described embodiments. In addition, in order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals in the drawings indicate the same members.

Throughout the specification, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components unless otherwise stated. In addition, terms such as "... unit", "... group", "module", and "block" described in the specification mean a unit that processes at least one function or operation, which is hardware, software, or hardware. and a combination of software.

1 shows a schematic structure of an out-of-order execution core according to an embodiment of the present invention.

Referring to FIG. 1 , the out-of-order execution core includes an instruction issue unit 100 , an instruction block unit 200 , a reorder buffer 300 , a physical register file 400 , and an operation execution unit 500 .

First, the instruction issue unit 100 may include an instruction cache unit 110 , an instruction fetch unit 120 , an instruction decoder unit 130 , a rename unit 140 , and a dispatch unit 150 .

The instruction cache unit 110 temporarily stores the applied instruction, and the instruction fetch unit 120 sequentially receives and stores the instructions stored in the instruction cache unit 110 . The command fetch unit 120 may receive, store, and output commands in a first-in-first-out manner as a kind of queue. That is, the command fetch unit 120 may first output the input command first. And the output command is removed from the command fetch unit 120 . In addition, the instruction fetch unit 120 may also perform branch prediction on a path branched from a branch instruction among a plurality of instructions during an instruction fetch process. In branch prediction, the instruction blocker 200, which will be described later, is used to set an instruction block.

The instruction decoder unit 130 converts the instruction applied from the instruction fetch unit 120 into an internally used opcode and source and destination register addresses for decoding. Here, the number of destination registers that one instruction can have is one, the number of source registers is two, and both the destination and source registers are logical registers. The converted commands are transferred to the rename unit 140 .

The rename unit 140 is a configuration provided to resolve data dependency between instructions executed out of order in the out of order execution core, and converts logical registers into a physical register file (hereinafter referred to as PRF) 400 . Convert to register. That is, a physical destination register of the PRF 400 is allocated to a logical destination register of the instruction command applied from the instruction decoder unit 130, and a corresponding physical source register of the PRF 400 is allocated to the logical source register. (physical source register).

In general, the rename unit 140 directly transfers an instruction converted from a logical register to a physical register to the dispatch unit 150 , but in the present embodiment, the rename unit 140 transmits the converted instruction to the instruction block unit 200 . Then, the instruction to which the physical register is reallocated by the instruction blocking unit 200 is transferred to the dispatch unit 150 .

The dispatch unit 150 receives and stores the instructions reassigned by the rename unit 140 , and sequentially dispatches the stored instructions to the operation execution unit 500 . The dispatch unit 150 stores each command transmitted from the rename unit 140 as an entry, and an opcode, a physical destination register address, and a physical source register address may be stored in each entry. The dispatch unit 150 executes the instruction when all the data of the physical source registers of the physical register file 400 are prepared for the stored instruction and the operation execution unit 500 to be used is available. issue with

The instruction blocking unit 200 is a physical register file management device of the out-of-order execution core of the present embodiment, and analyzes a plurality of instructions issued by the instruction issue unit 100 and blocks them according to a predetermined method, and blocks the plurality of instructions. , to distinguish between a final write operation instruction for each logical object register and a non-final write operation instruction among a plurality of instructions in the block. Then, it is checked whether the value written to the corresponding logical object register among the commands analyzed in the same block is only read once by another command. That is, in a plurality of instructions in a block, a specific physical object register is allocated to a specific logical object register, and it is determined that the allocated physical object register is used as a physical source register only once by another instruction thereafter, and is used as a physical source register. explore

When an instruction used as a physical source register is searched for, the instruction blocker 200 reallocates the physical source register of the searched instruction to be used immediately as a physical object register in the same instruction. That is, the physical source register of the searched instruction is immediately released when a read operation is performed, and is immediately reallocated to the physical object register within the same instruction so that the operation result is stored in the previously released physical source register. This can be seen as renaming a specific physical register of the physical register file so that it can be reused as a physical object register immediately after it is used as a physical source register within the same instruction.

As described above, since the number of destination registers and the number of source registers that one instruction can have in the out-of-order execution core is two, conventionally, three different physical registers are required and allocated for each instruction. In the present embodiment, the instruction blocking unit 200 allows the same physical registers to be allocated without allocating different physical registers of the physical register file to the physical source register and the physical destination register in the same searched instruction.

This allows to greatly reduce the number of physical registers that must be allocated for a particular instruction block in the physical register file. Therefore, by increasing the effective size of the physical register file so that the idle computational resources inside the pipeline can be fully utilized, parallelism is improved, so that the core can have a high level of instruction execution performance. It is also possible to reduce manufacturing cost and power consumption.

The command block unit 200 may include a block setting unit 210 , a block history table 220 , a block order queue 230 , and a handover unit 240 .

The block setting unit 210 receives and analyzes a command to be executed by the operation execution unit 500 from the command issue unit 100 . For example, the block setting unit 210 may receive a plurality of commands from the command decoder unit 130 of the command issue unit 100 , but in some cases, the rename unit 140 or the dispatch unit 150 may receive commands from the can be authorized

When a command is applied, the block setting unit 210 searches a block history table (hereinafter, BLHT) 220 to determine whether a command block including the applied command exists in the BLHT 220 .

If it is determined that the command block does not exist, the block setting unit 210 blocks a plurality of applied commands to generate the command block. Here, the block setting unit 210 searches for a branch instruction among a plurality of applied instructions, and when the branch instruction is confirmed, sets all previous instructions until the branch instruction is applied as one instruction group. And the set command block is allocated to the BLHT 220 as a BLHT entry and stored. Here, each instruction group divided based on the branch instruction is called a basic block. That is, the basic block refers to an instruction group in which a plurality of instructions positioned between two adjacent branch instructions are grouped.

At this time, the block setting unit 210 instructs a block definer defining a command block in the BLHT entry and a command for performing a last write operation on each of a plurality of logical registers among a plurality of commands inside the command block. You can include a final write directive.

The block setting unit 210 may first receive a memory address for a first instruction among a plurality of instructions included in the block from a program counter (hereinafter referred to as a PC) and include it in the BLHT entry as a block definer. In addition, the position of each command performing the final write operation among a plurality of commands may be written in a bit vector format and included in the BLHT entry as a final write indicator. For example, if the command block includes 5 commands, and the 3rd and 4th commands are the final write commands for each logical register, the block setting unit 210 writes the last commands in a bit vector format such as “00110”. You can write directives and include them in BLHT entries. Also, the block setting unit 210 may include a branch indicator indicating a branch path of a branch instruction inside the block in the BLHT entry. In the pipeline technique, the branch path of a branch instruction is divided into a taken, which moves to the branch destination when the condition of the branch instruction is determined to be true, and a not taken, which executes the next instruction when the condition is determined to be false, The block setting unit 210 may express a branch indicator indicating a branch path of a branch instruction in a block as a bit value and include it in the BLHT entry.

On the other hand, when it is determined that the command block including the applied command already exists in the BLHT 220 , the block setting unit 210 determines the BLHT ( 220), that is, adjacent blocks among a plurality of instruction blocks may be merged, or some instruction blocks may be split separately from a previously merged instruction block.

BLHT 220 stores each of the command blocks set by the block setting unit 210 as a BLHT entry. And the BLHT 220 transmits and stores the commands corresponding to the final write indicator and the branch indicator to the ROB 300, respectively, based on the BLHT entry. That is, each of the instructions corresponding to the last write indicator and the branch indicator included in the BLHT entry is stored as an entry of the ROB 300 . In addition, the BLHT 220 transmits the stored BLHT entry to the block order queue 230 according to the request of the block order queue 230 .

The block order queue 230 receives the BLHT entry generated or searched for by the block setting unit 210 from the BLHT 220 . When the first instruction among a plurality of instructions included in the instruction block corresponding to the BLHT entry is dispatched from the dispatch unit 150, the block order queue 230 requests the BLHT 220 to receive and allocate the corresponding instruction block, It is monitored whether all instructions included in the instruction block are normally executed by the operation execution unit 500 . And when it is determined that all commands of the command block have been normally executed, a commit acknowledgment signal for the commands included in the command block is transmitted to the ROB 300 and the dispatch unit 150 . That is, the ROB 300 and the dispatch unit 150 release the assignment to the instruction included in the corresponding instruction block.

However, if it is determined that the instruction of the instruction block is not normally executed, an execution error signal is transmitted to the ROB 300 and the dispatch unit 150 to invalidate the execution of the instruction of the instruction block (pipeline flush) and to be re-executed . That is, the assignment of instructions included in the instruction block is maintained.

For example, the block order queue 230 outputs an execution error signal to the ROB 300 and the dispatch unit 150 when an error occurs in the branch path or an exception occurs while executing the instruction of the instruction block designated by the BLHT entry. This invalidates the BLHT entry, that is, the execution result of all instructions in the instruction block, and causes the instruction block to be re-executed.

In addition, the block order queue 230 transmits a commit acknowledgment signal or an execution error signal to the block setting unit 210, and the block setting unit 210 merges or divides the command block in response to the commit acknowledgment signal or the execution error signal. let it do In this case, the block order queue 230 may transmit, to the block setting unit 210 , instruction information (eg, instruction location information) in which an execution error occurs in the instruction block together with the execution error signal.

Accordingly, when a commit approval signal is applied to the same command block by a predetermined reference number of commits (eg, 5 times) or more, the block setting unit 210 may merge the next command block adjacent to the corresponding command block. However, if an execution error signal is applied to the same instruction block for more than a predetermined reference number of errors (for example, twice), the instruction block can be divided based on the previous branch instruction adjacent to the instruction in which the execution error occurred in the corresponding instruction block. . This is because the block setting unit 210 generates a basic block based on the branch instruction as described above.

The handover unit 240 receives the BLHT entry from the block order queue 230 and checks a command to which a final write indicator is not specified in the command block designated as the BLHT entry. That is, for each logical object register, check the instruction, not the last write. Then, the value written to the logical object register by the checked instruction is checked for an instruction in which only one single read operation is performed by another instruction thereafter.

The handover unit 240 receives a command for which a checked read operation is performed among the commands converted from the logical register to the physical register by the rename unit 140, and sets the applied physical object register to the same physical register as the physical source register. It is reassigned and transferred to the rename unit 140 .

Here, when the handover unit 240 checks the instruction other than the final write, the value of the logical object register will be updated again in the instruction block, so a specific physical register until all operations of the instruction block are completed and outputted as a result. This is because it does not have to be assigned to and maintained. In addition, checking the instruction in which only one single read operation is performed releases the physical source register on which the read operation is performed early by determining in advance that the value stored in a specific physical register is not reused after the read operation is performed. This is to prevent an error in operation even when reassigned to a physical object register.

The ROB 300 stores each of the commands corresponding to the last write indicator and the branch indicator as ROB entries based on the BLHT entry designated by the block setting unit 210 among a plurality of BLHT entries stored in the BLHT 220 . The ROB 300 may allocate and deallocate a plurality of commands as ROB entries according to a first-in, first-out method.

Here, the ROB 300 stores each of the commands corresponding to the final write indicator and the branch indicator as ROB entries based on the BLHT entry designated by the block setting unit 210 .

In this embodiment, the command block unit 200 merges a plurality of commands into a command block, includes a final write indicator in the command block, allocates it as a BLHT entry, and the ROB 300 executes a command corresponding to the last write indicator Allocating and storing the ROB entry is to increase the effective size of the ROB 300 .

The PRF 400 is a structure that stores a value to be calculated according to an instruction executed by the operation execution unit 500 and a result value of which operation is completed, and a plurality of physical registers are stored in one logical register when the operation is executed in the out-of-order execution core. Allocating registers ensures correct out-of-order execution between different instructions that update the same logical register.

The PRF 400 includes a plurality of physical registers, and an operand value of an instruction or an operation result value may be stored in each of the plurality of physical registers. Here, a physical register in which an operand value is stored in a specific instruction is called a physical source register, and a physical register in which an operation result value of an instruction is stored is called a physical object register.

When an instruction is issued by the dispatch unit 150 , the PRF 400 reads a value stored in a physical source register designated for the issued instruction and transmits it to the operation execution unit 500 , and the operation result value is obtained from the operation execution unit 500 . When applied, the applied operation result value is stored in the physical destination register specified in the issued instruction.

The arithmetic execution unit 500 performs an arithmetic operation according to a dispatch entry issued from the dispatch unit 150 . The operation execution unit 500 obtains the operand value by reading the value stored in the physical register of the PRF 400 designated according to the physical source register address among the opcode included in the dispatch entry, the physical destination register address, and the physical source register address. Then, by calculating the obtained operand value according to the opcode, the PRF 400 allocates and updates the value of the register designated by the physical object register address.

Herein, the operation execution unit 500 is illustrated as a single block for convenience of explanation, but the operation execution unit 500 may include a plurality of operation function units, and each of the plurality of operation function units has different functions depending on the opcode. may be configured to perform The operation execution unit 500 may perform a plurality of operations in parallel according to a pipeline technique.

Conventionally, a physical register of the PRF 400 is allocated by a command for updating a logical register in the rename unit 140 of the command issue unit 100, and a physical register is allocated until the same logical register is updated by another instruction thereafter. of the allocation was maintained. That is, the previously allocated physical register is not released until the corresponding logical register is updated. This is to prevent an arithmetic error from occurring by stably maintaining the physical registers allocated to the logical registers.

In contrast, in the present embodiment, the instruction block unit 200 operates as a physical register file management device, and in the case of an instruction searched according to the above-described condition, it is stored in a physical register of the PRF 400 designated according to the physical source register address. After the read operation is performed, the physical register is immediately released when the stored value is transferred to the operation execution unit 500 in consideration of the fact that the value is not reused in the instruction block thereafter. In addition, the effect of increasing the effective size of the PRF 400 without increasing the physical size of the PRF 400 can be obtained by using the released physical register directly as a physical object register to store the operation result value performed by the operation execution unit 500 . As a result of analyzing the instructions executed in the actual out-of-order execution core, it was confirmed that 88% of the instructions were instructions that use the physical object register of the instruction as the physical source register, not the final write instruction. Therefore, the physical register file management apparatus according to the present embodiment can allocate physical registers for 7.3 times more instructions using the PRF 400 of the same size. That is, the same effect as that of increasing the size of the PRF 400 by 7.3 may be induced.

In the above description, for convenience of explanation, the block setting unit 210 and the handover unit 240 are illustrated as separate components, but the handover unit 240 may be included in the block setting unit 210 . Also, in the above description, it has been described that the handover unit 240 receives the command converted from the logical register to the physical register from the rename unit 140 , reallocates the applied physical register, and transfers it to the rename unit 140 . However, the handover unit 240 transmits, to the rename unit 140 , a reassignment indicator indicating that the command to be converted by the rename unit 140 is a command for which a confirmed read operation is performed. It is also possible to allocate the same physical register for the physical source register and the physical destination register in the corresponding instruction.

Also, in some cases, since the rename unit 140 and the handover unit 240 are integrated and configured, one of the rename unit 140 and the handover unit 240 may be omitted.

FIG. 2 shows an example of early release and reallocation of physical registers to increase the effective size of a physical register file in the out-of-order execution core of FIG. 1 .

In FIG. 2 , R1 to R4 represent logical registers, respectively, and P1 to P9 respectively represent physical registers of the PRF. Referring to FIG. 2 , (a) shows a case in which the commands I ₁ to I ₅ applied to the command issue unit 100 are sequentially listed without performing blocking according to the conventional method. And (b) shows a case in which blocking is performed on the five applied commands (I ₁ to I _{5 ). As shown in (a) and (b), the first and second instructions I 1} stored in the first and second logical registers R1 and R2 both when blocking is performed or when blocking is not performed. , I ₂ ), it can be seen that the operation result value is overwritten and updated by the third and fourth instructions I ₃ and I _{4 .} However, in case of (a) in which blocking is not performed, it is not _{possible to determine whether the third and fourth commands I 3} and I ₄ are the last write commands for the first and second logical registers R1 and R2, whereas , in the case of block (b), the third and fourth commands I ₃ and I ₄ may be determined as final write commands for the first and second logical registers R1 and R2.

Meanwhile, (c) shows an instruction block in which a logical register is converted into a physical register according to the existing PRF management technique for the blocked instruction block, and (d) is an instruction block in which a logical register is converted into a physical register according to the present embodiment. indicates

In the case of (c), the fifth and sixth physical registers P5 and P6 are physically written to the first and second logical object registers R1 and R2 of the first and _{second instructions I 1} and I _{2 , respectively.} It is allocated as a destination register. In addition, the third and fourth instructions I ₃ and I ₄ allocate the seventh and eighth physical registers P7 and P8 as physical object registers for the first and second logical registers R1 and R2, respectively.

However, (c) a first logical destination register (R1) of the first instruction (I ₁₎ in the are updated by the first instruction (I ₃₎ in the block of instructions, it is not a final write command. In addition, in the case of the fifth physical register P5 allocated in the first instruction I _{1 , it is used only once as a physical source register of the second instruction I 2} , and is not used again in the instruction block thereafter. That is, the fifth physical register P5 is not used after being read from _{the second instruction I 2 .} Nevertheless, conventionally, as shown in (c), as the fifth physical register (P5) is not released, the sixth physical register ( R2) as the second logical object register (R2) of the _{second instruction (I 2 )} P5) was further allocated.

In contrast, looking at (d) according to the present embodiment, the fifth physical register P5 from which the stored value is read by being used as a physical source register in _{the second instruction I 2 is immediately released, and the released fifth physical register (} P5) is reallocated to the second logical object register R2. In (d), a ' mark is added to differentiate the fifth physical register (P5') reallocated _{in the second instruction (I 2 ) from the fifth physical register (P5) allocated in the first instruction (I 1 ).} . That is, the reallocated fifth physical register P5' is a physical register that stores a value separate from the fifth physical register P5.

And as the fifth physical register P5' is reallocated to the second logical object register R2 of the second instruction I _{2 , third and fourth using the second logical object register R2 as a logical source register} It can be seen that the instructions I ₃ and I ₄ use the reallocated fifth physical register P5' as a physical source register.

As a result, according to the apparatus for managing the physical register file of the out-of-order execution core according to the present embodiment, since the sixth physical register P6 can be used as an extra physical register, the effective size of the physical register file is increased without increasing the physical size. to improve the execution performance of out-of-order execution cores.

FIG. 3 shows another example of early release and reallocation of physical registers to increase the effective size of the physical register file in the out-of-order execution core of FIG. 1 .

In FIG. 3, (a) shows an instruction block composed of a plurality of instructions, (b) shows an instruction block in which logical registers are converted into physical registers according to the existing PRF management technique, (c) shows an instruction block according to the present embodiment Represents an instruction block converted to a physical register.

In FIG. 2 , as a simple example, the fifth physical register P5 allocated to the first logical object register R1 _{of the first instruction I 1} is stored in the second logical object register R2 _{of the second instruction I 2 .} A case in which one sixth physical register P6 can be used in excess by reallocation is illustrated.

However, the reallocated physical register may continue to be reallocated repeatedly if the instruction satisfies the above condition.

Referring to (c) of FIG. 3 , first physical registers P1 and P1' _{allocated as logical object registers in the first instruction I 1} and reallocated as logical object registers in the second instruction I _{2 .} may be iteratively additionally reassigned when the above conditions are satisfied. In (c) of FIG. 3 , _{the first physical register P1 ′ reallocated in the second instruction I 2} is further reallocated in the third instruction I ₃ , thereby repeating three times in one instruction block. has been allocated, so that the PRF 400 can utilize two more physical registers as a spare.

In addition, the effective size of the PRF 400 according to the present embodiment can be increased more effectively as the size of the instruction block increases. This is because the ratio of the number of final write instructions to the total number of instructions in the instruction block decreases as the size of the instruction block increases.

FIG. 4 is a diagram for explaining a process of merging or dividing command blocks by the block setting unit of FIG. 1 .

4(a) shows a control flow graph according to blocks B1 to B6 divided based on a branch instruction in a program. As shown in (a), a program may include a plurality of branch instructions B1 to B6, and the plurality of branch instructions B1 to B6 may be branched to an instruction to be next executed. In (a), the first branch instruction B1 is not taken (NT) and branched, and in the third branch instruction (B3), it is taken and branched, and the fourth branch instruction (B4) is also taken (T). A case in which the program is executed by a path branching in the direction of the sixth branch instruction B6 is shown.

In addition, the block setting unit 210 may generate a plurality of instruction blocks iB1 to iB6 based on the branch instructions B1 to B6 as shown on the left side of (b). At this time, each of the plurality of instruction blocks iB1 to iB6 is a reference block including one corresponding branch instruction B1 to B6, and the branch path of each branch instruction B1 to B6 is predicted in advance.

In addition, when the same branch path is selected and a commit approval signal is applied more than a predetermined reference number of commits (here, for example, 5 times) or more for the same instruction block, instruction blocks adjacent to each other on the branch path are combined with each other. In (b), as shown in the middle, the third instruction block iB3 and the sixth instruction block iB3 are merged into the first instruction block iB1 and the fourth instruction block iB4, respectively. And even after that, if a commit approval signal is continuously applied to the same branch path, as shown on the right side of (b), the merged instruction blocks iB1 and iB4 can be merged back into one instruction block iB1. .

On the other hand, while repeatedly executing one merged instruction block (iB1), a predetermined reference error count (for example, If an execution error signal is applied more than twice), the merged instruction block (iB1) is divided from the reference block (iB3) before the reference block (iB4) containing the instruction at the location where the error occurred, and the second on the other branch path is divided. The branch path can be changed with 5 instruction blocks (iB5).

Although not shown, when the commit approval signal is applied again by the reference commit number or more in the changed branch path, the block setting unit 210 may additionally merge the fifth instruction block iB5 into the merged instruction block iB1 .

By repeating this process for a number of times required by the program, the block setting unit 210 may obtain an optimal instruction block combination.

In the case of program instructions, although the compiler may block a number of instructions while compiling, actual blocking cannot be performed because the compiler does not execute the instructions. That is, there is a limitation in that it is impossible to obtain an optimal instruction block because blockization cannot be performed in consideration of several branch instructions or exception conditions. However, as described above, in the present embodiment, since the block is performed based on the execution result of the previous instruction block based on the fact that the program instruction is repeatedly executed, the instruction block can be optimized.

5 illustrates a method for managing a physical register file of an out-of-order execution core according to an embodiment of the present invention.

Referring to FIGS. 1 to 4 , the physical register file management method of FIG. 5 is described. First, a plurality of instructions according to a pre-written program are applied ( S11 ). The applied plurality of instructions are fetched and decoded by the instruction issue unit 100 . The instruction blocker 200, which is a physical register file management apparatus, receives the decoded instruction and blocks it (S12). The instruction blocker 200 may search for a branch instruction among a plurality of decoded instructions and block the instruction into instruction blocks based on the searched branch instruction. The instruction blocker 200 may receive the decoded instruction, but in some cases, the physical register of the physical register file is allocated to the logical register of the decoded instruction and may receive the renamed instruction.

When the instruction is blocked, the physical register file management apparatus analyzes the instruction in the instruction block, and identifies a non-final write instruction that is not a final write to each logical object register among a plurality of instructions in the block ( S13 ). Then, the value written to the logical object register by the identified non-final write instruction is checked whether only one single read operation is performed in all instructions in the instruction block, and a single read instruction that performs a read operation on the value is determined. (S14).

Here, the non-last write instruction is renamed by allocating the physical register of the physical register file to the logical object register in the identified non-last write instruction as a physical object register, and a single read instruction is renamed from the identified non-last write instruction to the physical object renamed. This is an instruction whose register is renamed to be used as a physical source register.

And, in the physical register file management apparatus of this embodiment, the physical source register of a single read command is reallocated to a physical object register within the same command (S15). That is, within one instruction, a physical source register can be re-allocated and renamed so that it can be used again as a physical object register.

Thereafter, it is determined whether the command determined by the command issue unit 100 is dispatched (S16). If the determined instruction is dispatched, the value stored in the allocated physical source register is read and transferred to the operation execution unit 500 to execute the operation, and the physical source register is immediately released for reuse (S17) .

Then, the operation execution unit 500 executes an operation corresponding to the instruction using the instruction issued by the instruction issue unit 100 and the value read from the physical source register (S18). When the operation is executed by the operation execution unit 500 and the operation result is obtained, the operation result is stored in the reallocated physical object register, that is, the same physical register as the physical source register in the physical register file (S19).

Thereafter, the instruction block is optimized according to the operation result (S20). Here, the operation optimization may be optimized by merging or dividing adjacent instruction blocks based on the number of times the operation of the instruction block composed of a plurality of instructions is normally executed or the number of errors that are not normally executed.

However, since the above-described optimization of the instruction block is to further increase the efficiency of the physical register file management by increasing the size of the instruction block, it may be omitted in some cases.

The method according to the present invention may be implemented as a computer program stored in a medium for execution by a computer. Here, the computer-readable medium may be any available medium that can be accessed by a computer, and may include all computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, and read dedicated memory), RAM (Random Access Memory), CD (Compact Disk)-ROM, DVD (Digital Video Disk)-ROM, magnetic tape, floppy disk, optical data storage, and the like.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

100: instruction issue unit 200: instruction block unit
300: reorder buffer 400: physical register file
500: operation execution unit 110: instruction cache unit
120: instruction fetch unit 130: instruction decoder unit
140: rename unit 150: dispatch unit
210: block setting unit 220: block history table
230: block order queue 240: handover unit

Claims (16)

A device for managing a physical register file of an out-of-order execution core, comprising:
Classifies a plurality of instructions applied to the core into instruction blocks according to a predetermined criterion, identifies a non-final write instruction within the divided instruction block, and writes to a logical object register of the non-final write instruction identified within the instruction block Determines a single read command that uniquely performs a read operation on the value specified, and rewrites the physical register allocated as a physical source register in a single read command among multiple physical registers of the physical register file to a physical object register within the same instruction. Allocating physical register file management device. The apparatus of claim 1, wherein the physical register file management device is
A block setting for searching for a branch instruction among the plurality of instructions, classifying the plurality of instructions into the instruction block based on the searched branch instruction, and identifying a last write instruction performing a final write operation among the plurality of instructions in the instruction block wealth; and
In addition to the last write command identified in the block setting unit, a non-final write command that performs a write operation within a command block is checked, and a physical register that is a physical register of a physical register file allocated to a logical target register of the non-final write command. is used as a physical source register to determine a single read command that reads the value written to the physical source register, and when a read operation is performed on the value of the physical source register in the determined single read command, the physical source register is released early , a physical register file management apparatus comprising a handover unit for reallocating a physical object register in which an operation result of the single read command is stored. The method of claim 2, wherein the handover unit
A plurality of instructions applied to the core receives the decoded instruction as an opcode and a logical source register and logical destination register address, and a physical register of a physical register file is stored in each of the logical source register and logical object register of the decoded instruction as a physical source. A physical register file management apparatus for allocating a register and a physical object register, wherein for the single read instruction, the same physical register is allocated to one of a physical source register and a physical object register to obtain a renamed instruction. 4. The method of claim 3, wherein the core is
When the value stored in the physical source register of the single read instruction by dispatching the renamed instruction is transferred to the operation execution unit that performs the operation on the instruction, the physical source register is immediately released, and the instruction is issued to the operation execution unit. The physical register file management apparatus further comprising an instruction issue unit configured to store an operation execution result of the operation execution unit in a released physical source register. 4. The apparatus of claim 3, wherein the physical register file management device comprises:
a block history table storing at least one instruction block as an entry; and
The core monitors whether instructions included in the instruction block are normally executed, and when it is determined that all instructions have been normally executed, a physical register further comprising a block order queue that approves commits for all instructions corresponding to the instruction block file management device. The method of claim 5, wherein the block setting unit
The block definer indicating the memory address of the first instruction among the plurality of instructions included in the instruction block, the last write indicator indicating the location information of the instruction performing the last write operation among the plurality of instructions, and the location and predicted branch path of the branch instruction storing the indicated branch indicator in the information of the instruction block in the entry of the block history table,
A physical register for merging adjacent instruction blocks and restoring information of the merged instruction blocks to the block history table when commits are continuously approved for more than a predetermined reference commit number of consecutive identical instruction blocks from the block order queue file management device. 7. The method of claim 6, wherein the block order queue is
When it is determined that an error has occurred in at least one of the instructions of the instruction block, the apparatus for managing a physical register file transfers location information of an error occurring instruction in the instruction block to a block setting unit. The method of claim 7, wherein the block setting unit
Based on the location information of the instruction in which the error occurred transmitted from the block order queue, two instruction blocks are divided based on the branch instruction before the instruction in which the error occurred, and the information of the divided instruction block is rewritten in the block history table. Physical register file management device that stores. A physical register file management method performed in a physical register file management device of an out-of-order execution core, comprising:
Classifies a plurality of instructions applied to the core into instruction blocks according to a predetermined criterion, identifies a non-final write instruction within the divided instruction block, and writes to a logical object register of the non-final write instruction identified within the instruction block determining a single read command that uniquely performs a read operation on the read value;
A physical register file management method comprising reallocating a physical register allocated as a physical source register in a determined single read instruction among a plurality of physical registers of a physical register file to a physical object register in the same instruction. The method of claim 9, wherein determining the single read command comprises:
searching for a branch instruction among the plurality of instructions and classifying the plurality of instructions into the instruction block based on the searched branch instruction;
distinguishing between a final write command for performing a final write operation among a plurality of commands in the command block and a non-final write command for performing a write operation in the command block in addition to the final write command;
and determining a single read command for reading a value written to a physical source register by using a physical object register, which is a physical register of a physical register file allocated to the logical object register of the non-final write instruction, as a physical source register; How to manage files. The method of claim 10, wherein the reallocating to the physical destination register comprises:
Physical registers of the physical register file are allocated as physical source registers and physical object registers, respectively, to logical source registers and logical destination registers of instructions in which a plurality of instructions applied to the core are decoded into opcodes and logical source registers and logical destination register addresses However, for the single read command, a physical register file management method for acquiring the renamed command by allocating the same physical register with one of the physical source registers and the physical destination register. 12. The method of claim 11, wherein the physical register file management method comprises:
dispatching the renamed instruction to read a value stored in a physical source register of the single read instruction to perform an operation corresponding to the instruction;
releasing the physical source register immediately after reading the value stored in the physical source register; and
and storing the result of the operation corresponding to the instruction in a released physical source register designated as a physical object register. 13. The method of claim 12, wherein the physical register file management method comprises:
determining whether the instruction block including the instruction applied to the core is stored in a block history table storing at least one instruction block including a plurality of instructions as an entry;
storing information of the divided instruction block in the block history table;
Monitoring whether the instructions included in the instruction block are normally executed by the core, and when it is determined that all instructions are normally executed, committing all instructions corresponding to the instruction block Way. 14. The method of claim 13, wherein the information of the instruction block is
The block definer indicating the memory address of the first instruction among the plurality of instructions included in the instruction block, the last write indicator indicating the location information of the instruction performing the last write operation among the plurality of instructions, and the location and predicted branch path of the branch instruction A method of managing a physical register file containing branch directives indicating 15. The method of claim 14, wherein the physical register file management method comprises:
merging adjacent instruction blocks when commits are continuously approved for more than a predetermined reference number of commits for consecutive identical instruction blocks; and
and restoring information of the merged instruction block to the block history table. 16. The method of claim 15, wherein the physical register file management method comprises:
if it is determined that an error has occurred in at least one of the instructions of the instruction block, obtaining location information of the instruction in which the error has occurred in the instruction block;
dividing the two instruction blocks based on the branch instruction prior to the instruction in which the error occurred based on the obtained location information of the instruction in which the error occurred; and
The method of managing a physical register file further comprising the step of re-storing the divided instruction block information in the block history table.

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