KR102309349B1 - Semiconductor device and method for forming the same - Google Patents

Abstract

The method includes receiving a first design for a conductive bump on a first surface of an interposer, the conductive bumps in the first design having the same cross-sectional area; grouping the conductive bumps of the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface; grouping the conductive bumps, the pattern density being lower than the bump pattern density of the first region; forming a second design by modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second region; and forming a conductive bump on the first surface of the interposer according to a second design, wherein after forming the conductive bump on the first surface of the interposer according to the second design, the conductivity of the first group The bumps and the second group of conductive bumps have different cross-sectional areas.

Description

A semiconductor device and a method of manufacturing a semiconductor device

Priority Claims and Cross-References

This application claims priority to U.S. Provisional Patent Application No. 62/738,929, filed on September 28, 2018 under the title of "Bump Layout for Coplanarity Improvement".

The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density is due to iterative reduction in minimum feature size, which allows more components to be integrated in a given area.

As the demand for miniaturization of electronic devices increases, the need for smaller and more creative semiconductor die packaging technologies has emerged. An example of the above-described packaging system is a Package-on-Package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package, providing a high level of integration and component density. Another example is a Chip-On-Wafer-On-Substrate (CoWoS) structure. In some embodiments, a plurality of semiconductor chips are attached to a wafer to form a CoWoS structure, and then a dicing process is performed to separate the wafer into a plurality of interposers, each interposer having one or more A semiconductor chip is attached. The interposer to which the semiconductor chip(s) is attached is referred to as a Chip-On-Wafer (CoW) structure in some embodiments. The CoW structure is then attached to a substrate (eg, a printed circuit board) to form the CoWoS structure. These and other advanced packaging technologies enable the production of semiconductor devices with improved functionality and small footprints.

In an embodiment, a method comprises: receiving a first design for a conductive bump on a first surface of an interposer, the conductive bumps in the first design having the same cross-sectional area; grouping the conductive bumps of the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface; grouping the conductive bumps, wherein the pattern density is less than the bump pattern density of the first region; forming a second design by modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second region; and forming a conductive bump on the first surface of the interposer according to a second design, wherein after forming the conductive bump on the first surface of the interposer according to the second design, the conductivity of the first group The bumps and the second group of conductive bumps have different cross-sectional areas. In an embodiment, the size of the conductive bumps of the first group remains unchanged in the first design and the second design. In an embodiment, forming the conductive bumps comprises: forming, over the first surface of the interposer, a patterned mask layer having bump openings; and performing a plating process to form a conductive material within the bump openings of the patterned mask layer. In an embodiment, the size of the bump opening in the first region is smaller than the size of the bump opening in the second region. In an embodiment, the bump pattern density of the first region is greater than about 25%. In an embodiment, in a second design, the first group of conductive bumps has a first cross-section having a first dimension, the second group of conductive bumps has a second cross-section having a second, distinct dimension, and When the bump pattern density is from about 15% to about 25%, the second dimension is from about 1.1 times to about 1.25 times the first dimension, and when the bump pattern density of the second region is less than about 15%, the second dimension is the first dimension from about 1.35 times to about 1.55 times the dimension. In an embodiment, grouping the conductive bumps of the first design further comprises grouping the third group of conductive bumps in a third region of the first surface, wherein the bump pattern density of the third region is the second region. lower than the bump pattern density of In an embodiment, forming the second design further comprises modifying the cross-sectional area of the third group of conductive bumps in the third region. In an embodiment, the bump pattern density of the first region is greater than about 25%, the bump pattern density of the second region is between about 15% and about 25%, and the bump pattern density of the third region is less than about 15%. In an embodiment, in a second design, the first group of conductive bumps has a first cross-section having a first dimension, the second group of conductive bumps has a second cross-section having a second, distinct dimension, and The conductive bumps have a third cross-section having a third distinct dimension, the second dimension being from about 1.1 times to about 1.25 times the first dimension, and the third dimension being from about 1.35 times to about 1.55 times the first dimension. In an embodiment, the first cross-section, the second cross-section and the third cross-section have geometrically similar shapes. In an embodiment, the method further comprises attaching the substrate to the conductive bump of the interposer.

In an embodiment, the method comprises analyzing a first design for a conductive bump on a first surface of a workpiece, wherein the analysis comprises a first surface of the workpiece with a first region having a first conductive bump and a second conductive bump dividing into a second region having bumps, wherein a first bump pattern density of first conductive bumps in the first region is greater than a second bump pattern density of second conductive bumps in the second region, and wherein analyzing the first design, wherein a first bump pitch of the first conductive bumps in the second region is less than a second bump pitch of the second conductive bumps in the second region; modifying the first design to form a second design, wherein modifying the first design includes adding dummy bumps to the second region to reduce the second bump pitch; forming a conductive bump and a dummy bump on the first surface of the workpiece according to a second design; and bonding the workpiece to the substrate through the conductive bumps. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the dummy bumps are formed of the same material as the conductive bumps, and the dummy bumps are electrically isolated.

In an embodiment, a semiconductor device includes a die attached to a top surface of an interposer; a first conductive bump in a first region of the lower surface of the interposer, the first region having a first bump pattern density; a second conductive bump in a second region of the lower surface of the interposer, the second region having a second bump pattern density less than the first bump pattern density; and a dummy bump in a perimeter region of the lower surface of the interposer, the perimeter region surrounding the first region and the second region. In an embodiment, the first conductive bumps in the first region have a first bump pitch, the second conductive bumps in the second region have a second bump pitch greater than the first bump pitch, and the dummy bumps in the perimeter region have the first bump pitch. and a third bump pitch matching the bump pitch. In an embodiment, the semiconductor device comprises a second region in a third region of the lower surface of the interposer, wherein the third region has a third bump pattern density less than the second bump pattern density and a fourth bump pitch greater than the second bump pitch. 3 further conductive bumps, wherein the perimeter region surrounds the first region, the second region and the third region. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the first conductive bump and the second conductive bump have the same cross-sectional area.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.
1 illustrates a cross-sectional view of a semiconductor device, in accordance with some embodiments.
2 illustrates the layout of conductive bumps on a surface of an interposer, in some embodiments.
3 illustrates conductive bumps in the surface area of an interposer, in some embodiments.
4A and 4B illustrate top views of conductive bumps with different shapes in some embodiments.
5 illustrates an embodiment of a method for improving coplanarity of conductive bumps.
6 illustrates an embodiment of a method for improving coplanarity of conductive bumps.
7A and 7B illustrate embodiments of conductive bumps in the surface area of an interposer before and after applying the method illustrated in FIG. 6 .
8A illustrates the layout of conductive bumps on the surface of an interposer in some embodiments.
8B illustrates an enlarged view of a portion of the layout illustrated in FIG. 8A .
9 illustrates a flow diagram for a method of forming a semiconductor device in some embodiments.
10 illustrates a flow diagram for a method of forming a semiconductor device in some embodiments.
11 illustrates a flow diagram for a method of forming a semiconductor device in some embodiments.

The disclosure below presents several different embodiments or examples for implementing different features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the description that follows, the formation of a first feature on or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and the first feature and Embodiments may also be included in which other features may be formed between the first and second features such that the second features cannot be in direct contact. Also, the present disclosure may repeat reference signs and/or letters in various examples. Throughout the description, unless otherwise specified, like reference numerals refer to the same or similar components formed by the same or similar methods using the same or similar material(s).

Moreover, spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper”, etc. are used herein as exemplified in the drawings. It may be used for convenience of description that describes the relationship of one element or feature to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or in processing, as well as orientations shown in the figures. The device may be otherwise oriented (rotated 90 degrees or oriented at other orientations), and spatially relative descriptors used herein may be interpreted accordingly.

Embodiments of the present disclosure are described in relation to forming a conductive bump, and in particular, in relation to forming a conductive bump having improved flatness on a surface (eg, a lower surface) of an interposer. In some embodiments, the size (eg, cross-sectional area) of the conductive bumps in the area with the low bump pattern density is increased compared to the size of the conductive bumps in the area with the high bump pattern density. In some embodiments, dummy bumps are formed between the conductive bumps in regions with low bump pattern density to reduce bump pitch in regions with low bump pattern density, and dummy bumps are not formed in regions with high bump pattern density. does not In some embodiments, dummy bumps are formed in a perimeter region of the surface of the interposer to reduce bump pitch in the perimeter region, while the bump pitch in other regions of the surface surrounded by the perimeter region remains unchanged. For example, no dummy bumps are formed in other regions).

1 illustrates a cross-sectional view of a portion of a semiconductor device 100 , in accordance with some embodiments. The semiconductor device 100 has a chip-on-wafer-on-substrate (CoWoS) structure. For the sake of brevity, FIG. 1 shows only the left portion of the semiconductor device 100 , and the right portion of the semiconductor device 100 is identical (eg, symmetrical) to the left portion shown in FIG. 1 as will be readily understood by those skilled in the art. or similar.

To form the semiconductor device 100, one or more dies 101 (which may also be referred to as semiconductor dies, chips, or integrated circuit (IC) dies) are attached to an interposer 200 to form a chip-on-wafer (CoW) structure. formed, and then the CoW structure is attached to a substrate 300 (eg, a printed circuit board) to form a chip on wafer on substrate (CoWoS) structure. Die 101 is, in some embodiments, the same type of die (eg, a memory die or a logic die). In other embodiments, the dies 101 are of different types, eg, some dies 101 are logic dies and other dies 101 are memory dies.

Each die 101 has a substrate, electrical components formed in/on the substrate (eg, transistors, resistors, capacitors, diodes, etc.) and interconnects over the substrate that connect the electrical components to form a functional circuit of the die 101 . includes structure. The die 101 also includes a conductive pillar 103 (also referred to as a die connector) that provides electrical connections to the circuitry of the die 101 . For the sake of brevity, not all features of die 101 are illustrated.

The substrate of the die 101 may be a semiconductor substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or a combination thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

The electrical components of die 101 include a wide variety of active devices (eg, transistors) and passive devices (eg, capacitors, resistors, inductors), and the like. The electrical components of the die 101 may be formed in or on the substrate of the die 101 using any suitable method. The interconnect structure of die 101 includes one or more metallization layers (eg, copper layers) formed on one or more dielectric layers and is used to connect various electrical components to form functional circuits. In embodiments, the interconnect structure is formed of alternating layers of dielectric and conductive material (eg, copper), and may be formed through any suitable process (deposition, damascene, dual damascene, etc.).

To provide some degree of protection for the underlying structure of the die 101 , one or more passivation layers may be formed over the interconnect structure of the die 101 . The passivation layer may be made of low-k dielectrics such as silicon oxide, silicon nitride, or carbon-doped oxide, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, a combination thereof, or the like. The passivation layer may be formed through a process such as Chemical Vapor Deposition (CVD), although any suitable process may be utilized.

A conductive pad may be formed over the passivation layer and may extend through the passivation layer into electrical contact with the interconnect structure of the die 101 . The conductive pad may comprise aluminum, although other materials such as copper may alternatively be used.

A conductive filler 103 of the die 101 is formed on the conductive pads to provide conductive regions for electrical connection to the circuitry of the die 101 . The conductive pillars 103 may be copper pillars, contact bumps such as micro bumps, or the like, and may include materials such as copper, tin, silver, or other suitable materials.

Looking at the interposer 200 (which may also be referred to as a workpiece), a substrate 211 , a through-via 215 (also called a through-substrate via (TSV)), a conductive pad 213 on the top surface of the substrate 211 , an Under-Bump-Metallurgy (UBM) structure 230 on the lower surface of the substrate 211 , and conductive bumps 231 (which may also be referred to as bumps, connectors, or conductive pillars) on the UBM structure 230 . 1 also illustrates a surface dielectric layer 219 (eg, a bottommost dielectric layer) of the substrate 211 . UBM structure 230 extends through surface dielectric layer 219 and is electrically coupled with conductive features (eg, through vias 215 ) of interposer 200 .

The substrate 211 may be, for example, a silicon substrate, a doped or undoped type, or an active layer of a silicon on insulator (SOI) substrate. However, the substrate 211 may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate capable of providing suitable protection and/or interconnection functionality.

In some embodiments, the substrate 211 may include electrical components such as resistors, capacitors, signal distribution circuits, combinations thereof, and the like. These electrical components may be active, passive or a combination thereof. In another embodiment, the substrate 211 is devoid of both active and passive electrical components therein. All such combinations are entirely intended to be included within the scope of this disclosure.

The through via 215 extends from the top surface of the substrate 211 to the bottom surface of the substrate 211 , and provides an electrical connection between the conductive pad 213 and the conductive pump 231 . The through via 215 may be formed of a suitable conductive material, such as copper, tungsten, aluminum, an alloy, doped polysilicon, combinations thereof, or the like. A barrier layer may be formed between the through via 215 and the substrate 211 . The barrier layer may comprise a suitable material such as titanium nitride, but alternatively other materials such as tantalum nitride, titanium, etc. may be utilized.

In an embodiment, the UBM structure 230 includes three layers of conductive material, such as a titanium layer, a copper layer and a nickel layer. However, disposition of various suitable materials and layers suitable for forming the UBM structure 230, such as a chromium/chromium-copper alloy/copper/gold arrangement, a titanium/titanium tungsten/copper arrangement, or a copper/nickel/gold arrangement. there is Any suitable material or material layer usable for the UBM structure 230 is intended to be included entirely within the scope of this disclosure.

The UBM structure 230 includes forming openings in the surface dielectric layer 219 to expose conductive features in the substrate 211 (eg, conductive pads electrically coupled to the through vias 215 ); forming a seed layer over the surface dielectric layer 219 and along the interior of the openings in the surface dielectric layer 219; forming a patterned mask layer (eg, photoresist) over the seed layer; forming (eg, by plating) conductive material(s) in the opening of the patterned mask layer and over the seed layer; removing the mask layer; and removing the portion of the seed layer where the conductive material(s) is not formed. Other methods for forming the UBM structure 230 are possible and are intended to be included entirely within the scope of the present disclosure.

The conductive bumps 231 include micro bumps, copper fillers, controlled collapse chip connection (C4) bumps, copper layers, nickel layers, lead free (LF) layers, ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) layers, Cu/LF It can be any suitable type of external contact, such as a layer, a Sn/Ag layer, a Sn/Pb layer, combinations thereof, and the like.

In some embodiments, the conductive bumps 231 may be, or may include, a metal pillar such as a copper pillar formed by a plating process such as electroplating or electroless plating, for example. The conductive bumps 231 are formed by forming a patterned mask layer (eg, photoresist) having openings exposing the UBM structure 230; forming the conductive material(s) in the opening of the patterned mask layer and over the UBM structure 230 (eg, by plating); and removing the mask layer. Other methods for forming the conductive bumps 231 are possible and are intended to be included entirely within the scope of the present disclosure. In the example of FIG. 1 , the UBM structure 230 and each conductive bump 231 have the same width.

In some embodiments, the size of the opening in the mask layer (eg, photoresist) used to form the conductive bumps 231 (eg, via a plating process) corresponds to a cross-sectional area of the conductive bumps 231 (eg, via a plating process). , equal to), thus determining the cross-sectional area of this conductive bump. The cross-sectional area of the conductive bump 231 refers, in some embodiments, to the cross-sectional area of the conductive bump 231 along the cross-section A-A of FIG. 1 . The cross-section of the conductive bump 231 may have, for example, a circular shape or an elliptical shape. For ease of explanation, openings in the patterned mask layer (eg, photoresist) used to form conductive bumps 231 (eg, via a plating process) may be referred to hereinafter as bump openings.

As illustrated in FIG. 1 , the conductive pillars 103 of the die 101 are bonded to the conductive pads 213 of the interposer 200 by, for example, solder regions 105 . A reflow process may be performed to bond the die 101 to the interposer 200 .

After the die 101 is bonded to the interposer 200 , an underfill material 107 is formed between the die 101 and the interposer 200 . The underfill material 107 may include a liquid epoxy that is dispensed into the gap between the die 101 and the interposer 200 using, for example, a dispensing needle or other suitable dispensing tool and then cured. As illustrated in FIG. 1 , the underfill material 107 fills the gap between the die 101 and the interposer 200 , and may also fill the gap between the sidewalls of the dies 101 .

Next, a molding material 109 is formed over the interposer 200 and around the die 101 . The molding material 109 also surrounds the underfill material 107 . The molding material 109 may include, for example, an epoxy, an organic polymer, a polymer with or without a silica-based filler or glass filler, or other materials. In some embodiments, the molding material 109 includes Liquid Molding Compound (LMC) that is a gel-type liquid when applied. The molding material 109 may also contain a liquid or a solid when applied. Alternatively, the molding material 109 may include other isolating and/or encapsulating materials. Molding material 109 is applied using a wafer level molding process in some embodiments. The molding material 109 may be molded using, for example, compression molding, transfer molding, Molded UnderFill (MUF), or other methods.

The molding material 109 is then cured using a curing process in some embodiments. The curing process may include heating the molding material 109 to a defined temperature for a defined period of time using an annealing process or other heating process. The curing process may also include an ultraviolet (UV) light exposure process, an infrared (IR) energy exposure process, a combination thereof, or a combination of these and a heating process. Alternatively, the molding material 109 may be cured using other methods. In some embodiments, no curing process is included.

After the molding material 109 is formed, a planarization process such as chemical and mechanical planarization (CMP) may be performed to remove an excess portion of the molding material 109 over the die 101 , thus the molding material 109 . ) and the die 101 have the same top surface. As illustrated in FIG. 1 , the molding material 109 is adjacent the substrate 211 .

In the example of FIG. 1 , the CoW structure includes an interposer 200 , a die 101 , an underfill material 107 , and a molding material 109 . Next, the CoW structure may be bonded to a substrate 300 - which may be a printed circuit board (PCB) - to form a CoWoS structure.

Turning to substrate 300 , in some embodiments substrate 300 is a multilayer circuit board. For example, the substrate 300 may be one formed of Bismaleimide Triazine (BT) resin, FR-4 (composite made of glass fiber fabric with a flame retardant epoxy resin binder), ceramic, glass, plastic, tape, film, or other support material. The above dielectric layers 321/323/325 may be included. Substrate 300 may include electrically conductive features (eg, conductive lines 327 and vias 329 ) formed in/on substrate 300 . As illustrated in FIG. 1 , a substrate 300 has a conductive pad 326 formed on an upper surface of the substrate 300 and a conductive pad 328 formed on a lower surface of the substrate 300 , the conductive pad 326/238 are electrically coupled with conductive features of the substrate 300 . An external connector 331, such as a solder ball, copper pillar, or copper pillar with solder thereon, is formed on the conductive pad 328 as illustrated in FIG.

The interposer 200 is bonded to the substrate 300 . A reflow process may be performed to electrically and mechanically couple the interposer 200 to the substrate 300 via, for example, a solder region 217 . Next, an underfill material 112 is formed between the interposer 200 and the substrate 300 . The underfill material 112 may be the same as or similar to the underfill material 107 , and may be formed by the same or similar forming method as the underfill material 107 , so the details thereof will not be repeated. After the interposer 200 is bonded to the substrate 300 , the CoWoS structure of FIG. 1 is formed.

As the integration density of the semiconductor device 100 increases, more dies 101 can be attached to the interposer 200 to achieve more functions within the semiconductor package. As a result, the interposer 200 may increase in size. As the size of the interposer 200 increases, the coplanarity (eg, flatness and level) of the conductive bumps of the interposer 200, such as the conductive bumps 231 on the lower surface of the interposer 200, is reduced. It becomes increasingly difficult to maintain. The coplanarity of the conductive bumps 231 may be measured by the maximum offset between the end surfaces of the conductive bumps distal to the substrate 211 . For example, the coplanarity of the conductive bumps 231 can be measured by calculating the maximum difference (eg, maximum offset) between the lowermost surfaces of the conductive bumps 231 located in the central region and the peripheral region of the interposer 200 . have. As another example, the coplanarity of the conductive bumps 231 may be measured using commercially available equipment using an appropriate measurement method such as a peak-to-least mean square (LMS) method. Therefore, a large difference between the lowermost surfaces of the conductive bumps indicates poor coplanarity, which may cause problems such as cold-joints or bridging (eg, short circuit between conductive bumps). and, accordingly, the yield of the manufacturing process may be reduced. Various embodiment methods and structures in the present disclosure improve the coplanarity of the conductive bumps 231 , thereby improving the reliability of the semiconductor device 100 formed thereby and improving the production yield.

FIG. 2 illustrates a layout (which may also be referred to as a layout design or design) for a conductive pump 231 on the underside of the interposer 200 of FIG. 1 in some embodiments. Accordingly, FIG. 2 is a plan view of the lower surface of the interposer 200 . In particular, FIG. 2 illustrates regions (eg, 401 , 402 , 403 ) of the lower surface of interposer 200 in which conductive bumps 231 are formed, each region having a different bump pattern density, as shown in FIG. Details regarding the layout of 2 (eg, how to determine the boundaries of different regions) are described later. For the sake of brevity, conductive bumps 231 in regions (eg, 401 , 402 , 403 ) are not illustrated in FIG. 2 , but are illustrated in FIG. 3 .

3 shows the region of the lower surface of the interposer 200 in which the conductive bumps 231 are formed. The region illustrated in FIG. 3 may be any of the regions illustrated in FIG. 2 or part of the regions illustrated in FIG. 2 (eg, 401 , 402 , 403 ). An example of the shape of the bump 231 of FIG. 3 is illustrated in FIGS. 4A and 4B . In particular, FIG. 4A illustrates a bump 231 having a circular cross-section with a diameter R, and FIG. 4B illustrates a bump 231 having an elliptical cross-section having a first dimension R1 and a second dimension R2. For example, the second dimension R2 is measured along a longitudinal direction of the elliptical shape (eg, a direction along a major axis of the elliptical shape), and the first dimension R1 is measured along a direction perpendicular to the longitudinal direction. In the illustrated embodiment, the shape and size of the bump 231 in the top view of FIG. 3 is the same as the shape and size of the cross section of the bump 231 (along the cross section A-A of FIG. 1 ). Accordingly, the shape and size of the bump 231 corresponds to (eg, is equal to) the shape and size of the bump opening in the mask layer used to form the bump 231 as described above in some embodiments.

Referring again to FIG. 2 , region 401 represents an area having a first pattern density for bumps 231 , and region 402 represents an area having a second pattern density for bumps 231 , Region 403 denotes a region having a third pattern density for bump 231 , and the term “pattern density” refers to bump 231 within a predetermined region (eg, the region of the lower surface of interposer 200 ). refers to the density of

The pattern density of the bumps 231 in the predetermined region may be calculated by dividing the total area of the bumps 231 in the corresponding region by the area of the corresponding region. In the example of FIG. 3 , the illustrated region is a rectangular region having a width b and a length a, and thus has an area of a×b. The total area of the bumps 231 in the region is the sum of the areas of the bumps 231 inside this region (eg, the areas of the circular shape or the elliptical shape of the bumps 231 in the plan view of FIG. 3 ). In the following description, the pattern density of the bumps 231 in a predetermined region may be referred to as the pattern density of the corresponding region or the bump pattern density of the corresponding region. In the illustrated embodiment, region 401 has a pattern density greater than about 25%, region 402 has a pattern density of between about 15% and about 25%, and region 403 has a pattern density of less than about 15%. It has a pattern density. In the description below, region 401 may be referred to as a high pattern density region, region 402 may be referred to as a medium pattern density region, and region 403 may be referred to as a low pattern density region.

In the example of FIG. 2 , region 401 includes a continuous region (eg, rectangular-shaped region), region 402 includes four distinct regions (eg, four rectangular-shaped regions), and region ( 403 includes regions of the lower surface of interposer 200 other than regions 401 and 402 . The number of regions (eg, 401 , 402 , 403 ) in FIG. 2 , positions of regions, and shapes of regions are illustrative only and not limiting, and different numbers of regions, different positions of regions, and different shapes of regions are also shown. It is also possible and is intended to be included entirely within the scope of this disclosure.

In previous processing not using the present disclosure, the sizes of bump openings for forming bumps 231 in different regions (eg, 401, 402, 403) are the same, and thus conductive bumps 231 formed in different regions. has the same cross-sectional area. However, it is observed that by using the same bump opening size, bumps 231 formed in regions with higher pattern density can have a lower height than bumps 231 formed in regions with lower pattern density. The difference in height of the conductive bumps 231 in regions having different pattern densities may be referred to as a loading effect of (the height of) the conductive bumps 231 due to a change in the pattern density. The loading effect contributes to deterioration of coplanarity of the conductive bumps 231 . Without wishing to be bound by a particular theory, during the plating process to form bumps 231 , the chemical fluid has a substantially uniform metal ion concentration, so that regions with high pattern density have less metal per bump 231 . ions, and thus the bumps 231 formed in the high pattern density region may have a lower height than the bumps 231 formed in the low pattern density region.

Various methods of the present disclosure reduce the height difference between the bumps 231 in regions having different pattern densities, and thus improve the coplanarity of the bumps 231 . 5 shows that the bumps 231 reduce the height difference by adjusting the size (eg, cross-section) of the bumps 231 so that the sizes of the bumps 231 in different regions (eg, 401 , 402 , 403 ) are different. exemplify the method. In particular, the size of the bump 231 in the low pattern density region 403 and the size of the bump 231 in the medium density region 402 are increased compared to the size of the bump 231 in the high pattern density region ( See below for details). Adjusting the size of the bump 231 may be accomplished by adjusting the size of the bump opening in the mask layer used to form the bump 231 as described above.

In some embodiments, the method illustrated in FIG. 5 includes accepting a first layout design for conductive bumps 231 (eg, an existing design used as a starting point to improve coplanarity using the methods disclosed herein). is started by The first layout design (which may be referred to as a first design) may include a size (eg, a cross-sectional area) of the bump 231 and a location of the bump 231 . In the description below, the layout design of FIG. 2 is used as an example of the first design, assuming that the bumps 231 in all regions (eg, 401, 402, 403) have the same size (eg, cross-sectional area). can be The design of FIG. 2 is modified to eventually form a second design that achieves improved coplanarity for bumps 231 , the details of which are described below.

Next, the method of FIG. 5 evaluates (eg, calculates) the bump pattern density in different areas on the underside of the interposer 200 . Based on the pattern density of bumps 231 in different regions, the method of FIG. 5 divides bumps 231 into high pattern density regions 401 (e.g., 25% or greater pattern density), medium pattern density regions ( 402) (eg, having a pattern density of about 15% to about 25%) or low pattern density regions 403 (eg, having a pattern density of 15% or less). That is, the method described above describes the lower surface of the interposer 200 into three regions (401, 402 in FIG. 2 , 401, 402 in FIG. 403)).

In some embodiments, determining the boundaries of the different regions (eg, 401 , 402 , 403 ) may include dividing the lower surface of interposer 200 into a plurality of non-overlapping grid-like small regions (eg, about 1 mm in size by about 1 mm in size). 0.5 mm rectangular area), calculating the bump pattern density in each small area, and assigning each small area to one of the areas (e.g., 401, 402, 403) based on the calculated pattern density. may include In some embodiments, the first design may have bumps 231 formed in clusters, each bump cluster having a different bump pattern density, in which case the boundaries of each bump 231 cluster are assigned by the bump clusters. It can be used as a boundary for an area to be These and other ways of determining the boundaries of different regions are entirely intended to be included within the scope of the present disclosure.

Next, the method of FIG. 5 modifies the first layout design to form a second layout design (which may also be referred to as a second design). In particular, in the second layout design, the size (eg, cross-sectional area) of the bumps 231 in the low pattern density region 403 and the size (eg, cross-sectional area) of the bumps 231 in the medium pattern density region 402 (eg, cross-sectional area) is adjusted (eg, increased) to be greater than the size (eg, cross-sectional area) of the bumps 231 in the high density region 401 . The size of the bumps 231 in the high pattern density region 401 remains unchanged between the first and second layout designs in the illustrated embodiment.

In some embodiments, increasing the size (eg, cross-sectional area) of the bumps 231 in the low and medium pattern density regions may increase the size (eg, cross-sectional area) of a mask layer used to form the bumps 231 , eg, in a plating process. This is achieved by increasing the size of the bump opening. In particular, applying the method of FIG. 5 , assuming that the bump 231 in the first layout design has a circular shape with a diameter R in all regions (eg, 401 , 402 , 403 ), the medium pattern density region The diameter R' of the bump opening (eg, circular shape) in 402 is adjusted to be from about 1.1R to about 1.25R, and the diameter R" of the bump opening in low pattern density region 403 is It is adjusted to be about 1.35 R to about 1.55 R. The diameter of the bump openings in the high pattern density region 401 is kept at R.

If the openings in the first layout design have an elliptical shape with a first dimension R1 and a second dimension R2 in all regions (eg, 401 , 402 , 403 ), then the intermediate pattern density region 402 in the second design. ) is adjusted to have a first dimension (R1') and a second dimension (R2'), wherein R1' is about 1.1R1 to 1.25R1, and a second dimension R2' ) is from about 1.1R2 to about 1.25R2. Additionally, the bump openings (eg, oval-shaped) in the low density region 403 are adjusted to have a first dimension R1″ and a second dimension R2″, wherein R1″ is between about 1.35R1 and about 1.55. R1, and the second dimension R2″ is from about 1.35R2 to about 1.55R2. The openings in the high pattern density region 401 still have a first dimension R1 and a second dimension R2.

As described above, the size of the bump openings in the medium pattern density region 402 and the low pattern density region 403 is adjusted to be a predetermined percentage greater than the size of the bump openings in the high pattern density region 401 . Because the size of the bump openings corresponds (eg, the same) to the cross-sectional area of the subsequently formed bumps 231 , the conductive bumps 231 formed in regions with different pattern densities using the second layout design have different cross-sectional areas. has In addition, the relationship between the dimensions of the bump openings in the different regions described above also depends on the dimensions of the conductive bumps 231 formed in the different regions using the second layout design (eg, the diameter of the circular shape in FIG. 4A or the diameter of the circular shape in FIG. 4B ). The first dimension and the second dimension of the elliptical shape in ) also apply.

The method of FIG. 5 may include additional processing steps, such as forming conductive bumps 231 according to the second layout design. In the example of FIG. 2 , region 401 is a high pattern density region, region 402 is a medium pattern density region, and region 403 is a low pattern density region. Therefore, after forming the conductive bumps 231 according to the second layout design, the conductive bumps 231 in the region 403 have a larger cross-sectional area than the conductive bumps 231 in the region 402, and the region 402 The conductive bumps 231 in ) have a larger cross-sectional area than the conductive bumps 231 in the region 401 .

As an example, consider a first design where the bumps 231 in the high pattern density region 401 have a first dimension R1 of 70 μm and a second dimension R2 of 90 μm. After the bump sizes in the low pattern density region 403 and the medium pattern density region 402 are adjusted, in the second design, the bumps 231 in the medium pattern density region 402 have a first dimension of 82 μm and 105 . The bumps 231 having a second dimension of μm and in the low pattern density region 403 have a first dimension of 98 μm and a second dimension of 125 μm.

6 illustrates a method of improving the coplanarity of the conductive bumps 231 in another embodiment. In the embodiment of FIG. 6 , processing begins by accepting a first design for conductive bumps 231 and evaluating the bump pattern density for different regions on the underside of interposer 200 . Based on the bump pattern density in the different regions, the conductive bumps 231 can be divided into high pattern density regions 401 (eg, having a pattern density greater than or equal to about 25%), medium pattern density regions 402 (eg, pattern density). are grouped into different regions, such as from about 15% to about 25%) or low pattern density regions 403 (eg, having a pattern density of 15% or less). The processing is similar to that described above with reference to FIG. 5 , so details are not repeated. In the illustrated embodiment, in the first design, the bump pitch P1 in the high pattern density region 401 is less than the bump pitch P2 in the medium pattern density region 402 , and in the medium pattern density region 402 , the bump pitch P1 is smaller. The bump pitch P2 of is smaller than the bump pitch P3 in the low pattern density region 403 .

Next, the first design is modified to form a second design. In particular, the pitch of bumps 231 in the low pattern density region 403 and the pitch of bumps 231 in the medium density region 402 match the pitch of the bumps 231 in the high pattern density region 401 . adjusted to be In some embodiments, to adjust (eg, reduce) bump pitch between adjacent bumps 231/231D, eg, in low pattern density regions 403 and medium pattern density regions 402 to adjust (eg, reduce) existing bumps ( A dummy bump 231D (see FIG. 7B ) is added between the 231 , so that the adjusted bump pitch in the low pattern density region 403 and the medium pattern density region 402 is increased in the high pattern density region 401 . Matching bump pitch, where dummy bumps 231D are conductive bumps that are electrically isolated (eg, not electrically coupled with other electrically conductive features). In contrast, each conductive bump 231 is electrically coupled to at least one electrically conductive feature (eg, contact pad, through via 215 , etc.) of interposer 200 . Dummy bumps 231D may be formed using the same material(s) as bumps 231 and with the same processing steps as bumps 231 . The term “matching” herein may be a match between pitches within a manufacturing limit or a match between pitches within a certain percentage. For example, the bump pitch in the low pattern density region 403 and the medium pattern density region 402 is within a predetermined percentage of the bump pitch in the high pattern density region 401 (eg, ±15%, ±10%, or ±5). % within).

For example, the bump pitch P1 in the high pattern density region 401 is 150 μm, the bump pitch P2 in the medium pattern density region 402 is 180 μm, and the bump pitch P1 in the low pattern density region 403 is Consider the first design where the bump pitch P3 is 250 μm. After correcting the bump pitch, the bump pitch for the bump 231 in all regions (eg, 401 , 402 , 403 ) has the same bump pitch of 150 μm.

In the illustrated embodiment, the cross-sectional area of bumps 231 in different regions (eg, 401 , 402 , 403 ) does not change between the first design and the second design. In some embodiments, the cross-sectional areas of bumps 231 in different regions (eg, 401 , 402 , 403 ) are the same. The method of FIG. 6 may include additional processing steps, such as forming bumps 231 and dummy bumps 231D according to the second design.

7A and 7B respectively illustrate an embodiment of a design for a conductive bump 231 in the region of the lower surface of the interposer 200 before and after applying the method illustrated in FIG. 6 . The regions illustrated in FIGS. 7A and 7B may be, for example, a region of the low pattern density region 403 and a region of the medium pattern density region 402 . As illustrated in FIG. 7A , the pitch between the bumps 231 of the first design is, for example, 250 μm. 7B shows a dummy bump 231D formed between the bumps 231 . For example, the dummy bumps 231D may be formed between adjacent bumps 231 in the same column. Additionally, FIG. 7B also illustrates a row of dummy bumps 231D formed between two adjacent rows of bumps 231 . In the formed dummy bumps 231D, the pitch of the bumps (eg, 231 and 231D) is reduced to match the pitch density of the high pattern density region 401, for example, to 125 μm.

8A illustrates a layout design for conductive bumps 231 on the underside of interposer 200 using an embodiment method. In the example of FIG. 8A , a first design (eg, see FIG. 2 ) is accepted and evaluated. Pattern densities for different areas of the first design are calculated. Based on the calculated pattern density, the bumps 231 are located in high pattern density regions 401 (eg, having a pattern density of 25% or more), medium pattern density regions 402 (eg, having a pattern density of about 15% to about 25%). %) and low pattern density regions 403 (eg, having a pattern density of 15% or less). In the embodiment of FIG. 8A , the cross-sectional areas of bumps 231 in different regions (eg, 401 , 402 , 403 ) are the same. In FIG. 8A , the high pattern density region 401 has a bump pitch P1 , the medium pattern density region has a bump pitch P2 , and the low pattern density region has a bump pitch P3 . In the illustrated embodiment, the bump pitch P1 is smaller than the bump pitch P2, and the bump pitch P2 is smaller than the bump pitch P3.

In order to reduce the height difference of the conductive bumps 231 in regions with different pattern densities, the embodiment method of FIG. 8A cuts the perimeter 200P (eg, sidewalls) of the interposer 200 to form a second design. The first design is modified by adding a dummy bump 231D (see FIG. 8B ) to the region 404 (illustrated as a shaded pattern in FIG. 8A ) along which it is placed. As used herein, the term “matching” refers to matching between pitches within manufacturing limits or within a certain percentage of the bump pitch in the high pattern density region 401 (eg, within ±15%, ±10%, or ±5%). may be a match between pitches in .

As illustrated in FIG. 8A , region 404 has a hollow rectangular shape, although other suitable shapes are also contemplated within the scope of the present disclosure. Region 404 may be selected to include N outermost bump columns and/or N outermost bump rows 231 on the underside of interposer 200 in a first design, where N is 5 , 10 or 15, that is, there is no bump 231 or 231D between the area 404 of the interposer 200 and the perimeter 200P. Thus, in the second design, region 404 has both dummy bumps 231D and conductive bumps 231 formed therein, and other regions (eg, 401, 402, 403) of FIG. 8A are internally [eg, dummy bumps]. (not 231D)] only conductive bumps 231 are formed.

In the embodiment illustrated in FIG. 8A , region 404 surrounds high pattern density region 401 , medium pattern density region 402 and low pattern density region 403 . Note that in FIG. 8A , region 404 includes a region that previously belonged to low pattern density region 403 . Accordingly, in the second design illustrated in FIG. 8A , region 403 includes, in addition to region 401 / 402 , a portion of the lower surface of interposer 200 located inside region 404 .

For example, the bump pitch P1 in the high pattern density region 401 is 150 μm, the bump pitch P2 in the medium pattern density region 402 is 180 μm, and the bump pitch P1 in the low pattern density region 403 is Consider the first design where the bump pitch P3 is 250 μm. In the second design, dummy bumps 231D are formed in region 404, so that bump pitch P4 between bumps (eg, between 231 and 231D) is 150 μm. The method of FIG. 8A may include additional processing steps, such as forming bumps 231 and dummy bumps 231D according to the second design.

In the embodiment of FIG. 8A , the cross-sectional area of bumps 231 in all regions 401 , 402 , 403 is the same and does not change between the first design and the second design. Moreover, in the illustrated embodiment, the cross-sectional area of the dummy bump 231D in the region 404 is equal to the cross-sectional area of the conductive bump 231 .

8B illustrates an enlarged view of a portion 210 of the region 404 illustrated in FIG. 8A . As illustrated in FIG. 8B , dummy bumps 231D are formed between the bumps 231 . 8B also illustrates a row of dummy bumps 231D formed between two rows of conductive bumps 231 . The bump pitch (eg, between 231 and 231D) of region 404 is P4 , P4 matches bump pitch P1 of high pattern density region 401 .

Modifications to the disclosed embodiments are possible and are intended to be included entirely within the scope of the present disclosure. For example, although various embodiment methods adjust bump size (eg, cross-sectional area) or bump pitch, it is also possible to improve the coplanarity of bumps 231 by adjusting both bump size and bump pitch. For example, the bump opening size in the various regions (eg, 401 , 402 , 403 ) may be adjusted while the bump pitch in the various regions is adjusted. Additionally, while the present disclosure is described in the context of forming conductive bumps 231 on the lower surface of interposer 200 , the disclosed method may be used to form other components and/or other surfaces (eg, a top surface instead of a bottom surface). It can be used to improve the coplanarity of the conductive bumps formed thereon.

Embodiments may achieve several advantages. By adjusting the bump size (eg, cross-sectional area) or bump pitch in the design of the conductive bumps 231 , the height difference of the bumps in regions with different pattern densities is reduced, and the coplanarity of the conductive bumps is improved. Improved coplanarity prevents or reduces problems such as cold joints of bumps (e.g., poorly formed solder regions that fail to properly bond the conductive bumps of two devices) and bridging, thereby improving the reliability of the formed device; Improve production yield. To meet the requirements for coplanarity of conductive bumps without using the presently disclosed method, the reference method may have to reduce the electroplating rate and/or metal ions in the chemical fluid used for electroplating. It may be necessary to increase the concentration (eg, the concentration of Ag), which reduces production throughput and increases manufacturing costs. The present disclosure avoids these problems and thus achieves increased throughput (eg, higher electroplating rates) and reduced manufacturing costs.

9 , 10 , and 11 each illustrate a flowchart of a method 1000 , 2000 , and 300 of manufacturing a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment methods shown in FIGS. 9 , 10 and 11 are merely examples of several possible embodiment methods. Numerous variations, alternatives, and modifications will be apparent to those skilled in the art. For example, the various steps illustrated in FIGS. 9 , 10 and 11 may be added, removed, replaced, reconfigured, and repeated.

Referring to FIG. 9 , a block 1010 of method 1000 receives a first design for conductive bumps on a first surface of an interposer, the conductive bumps of the first design having the same cross-sectional area. At a block 1020, the conductive bumps of the first design are grouped into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, wherein the second The bump pattern density of the region is lower than the bump pattern density of the first region. At a block 1030, a second design is formed by modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second region. At a block 1040, conductive bumps are formed on the first surface of the interposer according to a second design, wherein the first group of conductive bumps and the second group of conductive bumps have different cross-sectional areas after being formed.

Referring to FIG. 10 , at block 2010 of method 2000, a first design for a conductive bump on a first surface of a workpiece is analyzed, wherein the analysis causes the first surface of the workpiece to form a first conductive bump. and dividing into a first region having a first region and a second region having a second conductive bump, wherein the first bump pattern density of the first conductive bumps in the first region is a second bump pattern of the second conductive bumps in the second region greater than the density, and a first bump pitch of the first conductive bumps in the first region is less than a second bump pitch of the second conductive bumps in the second region. At block 2020, the first design is modified to form a second design, and modifying the first design includes adding dummy bumps to the second region to reduce the second bump pitch. At a block 2030, conductive bumps and dummy bumps are formed on the first surface of the workpiece according to the second design. At a block 2040, the workpiece is bonded to the substrate via the conductive bumps.

Referring to FIG. 11 , at block 3010 of method 3000, a first design for conductive bumps on a first surface of a workpiece, the conductive bumps having the same cross-sectional area, is received, wherein the conductive bumps have the same cross-sectional area as the first surface. a first conductive bump in a first region of and a second bump pitch greater than the pitch. At a block 3020, the first design is changed to the second design by adding dummy bumps to the second region to reduce the second bump pitch such that the second bump pitch substantially matches the first bump pitch. At a block 3030, a conductive bump is formed on the first surface of the workpiece according to a second design.

In an embodiment, a method comprises: receiving a first design for a conductive bump on a first surface of an interposer, the conductive bumps in the first design having the same cross-sectional area; grouping the conductive bumps of the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface; grouping the conductive bumps, wherein the pattern density is less than the bump pattern density of the first region; forming a second design by modifying the first design, wherein modifying the first design includes modifying the cross-sectional area of the second group of conductive bumps in the second region; and forming a conductive bump on the first surface of the interposer according to a second design, wherein after forming the conductive bump on the first surface of the interposer according to the second design, the conductivity of the first group The bumps and the second group of conductive bumps have different cross-sectional areas. In an embodiment, the size of the conductive bumps of the first group remains unchanged in the first design and the second design. In an embodiment, forming the conductive bumps comprises: forming, over the first surface of the interposer, a patterned mask layer having bump openings; and performing a plating process to form a conductive material within the bump openings of the patterned mask layer. In an embodiment, the size of the bump opening in the first region is smaller than the size of the bump opening in the second region. In an embodiment, the bump pattern density of the first region is greater than about 25%. In an embodiment, in a second design, the first group of conductive bumps has a first cross-section having a first dimension, the second group of conductive bumps has a second cross-section having a second, distinct dimension, and When the bump pattern density is from about 15% to about 25%, the second dimension is from about 1.1 times to about 1.25 times the first dimension, and when the bump pattern density of the second region is less than about 15%, the second dimension is the first dimension from about 1.35 times to about 1.55 times the dimension. In an embodiment, grouping the conductive bumps of the first design further comprises grouping the third group of conductive bumps in a third region of the first surface, wherein the bump pattern density of the third region is the second region. lower than the bump pattern density of In an embodiment, forming the second design further comprises modifying the cross-sectional area of the third group of conductive bumps in the third region. In an embodiment, the bump pattern density of the first region is greater than about 25%, the bump pattern density of the second region is between about 15% and about 25%, and the bump pattern density of the third region is less than about 15%. In an embodiment, in a second design, the first group of conductive bumps has a first cross-section having a first dimension, the second group of conductive bumps has a second cross-section having a second, distinct dimension, and The conductive bumps have a third cross-section having a third distinct dimension, the second dimension being from about 1.1 times to about 1.25 times the first dimension, and the third dimension being from about 1.35 times to about 1.55 times the first dimension. In an embodiment, the first cross-section, the second cross-section and the third cross-section have geometrically similar shapes. In an embodiment, the method further comprises attaching the substrate to the conductive bump of the interposer.

In an embodiment, the method comprises analyzing a first design for a conductive bump on a first surface of a workpiece, wherein the analysis comprises a first surface of the workpiece with a first region having a first conductive bump and a second conductive bump dividing into a second region having bumps, wherein a first bump pattern density of first conductive bumps in the first region is greater than a second bump pattern density of second conductive bumps in the second region, and wherein analyzing the first design, wherein a first bump pitch of the first conductive bumps in the second region is less than a second bump pitch of the second conductive bumps in the second region; modifying the first design to form a second design, wherein modifying the first design includes adding dummy bumps to the second region to reduce the second bump pitch; forming a conductive bump and a dummy bump on the first surface of the workpiece according to a second design; and bonding the workpiece to the substrate through the conductive bumps. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the dummy bumps are formed of the same material as the conductive bumps, and the dummy bumps are electrically isolated.

In an embodiment, a semiconductor device includes a die attached to a top surface of an interposer; a first conductive bump in a first region of the lower surface of the interposer, the first region having a first bump pattern density; a second conductive bump in a second region of the lower surface of the interposer, the second region having a second bump pattern density less than the first bump pattern density; and a dummy bump in a perimeter region of the lower surface of the interposer, the perimeter region surrounding the first region and the second region. In an embodiment, the first conductive bumps in the first region have a first bump pitch, the second conductive bumps in the second region have a second bump pitch greater than the first bump pitch, and the dummy bumps in the perimeter region have the first bump pitch. and a third bump pitch matching the bump pitch. In an embodiment, the semiconductor device comprises a second region in a third region of the lower surface of the interposer, wherein the third region has a third bump pattern density less than the second bump pattern density and a fourth bump pitch greater than the second bump pitch. 3 further conductive bumps, wherein the perimeter region surrounds the first region, the second region and the third region. In an embodiment, the first bump pattern density is greater than about 25%. In an embodiment, the first conductive bump and the second conductive bump have the same cross-sectional area.

The preceding description outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they may readily use the present disclosure as a basis for constructing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. only do Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims (10)

A method for forming a semiconductor device, comprising:
receiving a first design for conductive bumps, wherein the conductive bumps in the first design are on a first surface of an interposer, the conductive bumps in the first design have the same cross-sectional area;
The conductive bumps are
a first group of conductive bumps in a first region of the first surface, the first region having a first bump pattern density; and
a second group of conductive bumps in a second region of the first surface, wherein the second region having a second bump pattern density is lower than the first bump pattern density in the first region;
including,
modifying the first design, wherein modifying the first design comprises modifying a cross-sectional area of the second group of conductive bumps in the second region; forming; and
forming the conductive bumps on the first surface of the interposer according to the second design, after the conductive bumps are formed on the first surface of the interposer according to the second design, the first the group of conductive bumps and the second group of conductive bumps have different cross-sectional areas;
A method for forming a semiconductor device comprising: The method of claim 1 , wherein the size of the conductive bumps of the first group remains unchanged in the first design and the second design. The method of claim 1 , wherein the forming of the conductive bumps comprises:
forming a patterned mask layer having bump openings over the first surface of the interposer; and
performing a plating process to form a conductive material in the bump openings of the patterned mask layer;
A method for forming a semiconductor device comprising: 2. The method of claim 1, wherein the conductive bumps in the first design further comprise a third group of conductive bumps in a third region of the first surface, wherein a third bump pattern density of the third region is the third region of the third region. and less than the second bump pattern density in two regions. A method for forming a semiconductor device, comprising:
accepting a first design, wherein the first design includes conductive bumps on an interposer, the conductive bumps in the first design have the same cross-sectional area, and the conductive bumps in the first design include conductive bumps on the interposer. a first group of conductive bumps in a first area on a first side and a second group of conductive bumps in a second area on the first side of the interposer, wherein the first group of conductive bumps comprises a first 1 has a first bump pattern density within a predetermined range, the second group of conductive bumps has a second bump pattern density within a second predetermined range, wherein the first bump pattern density is the second bump pattern density higher than -;
to form a second design for the conductive bumps by increasing the cross-sectional area of the second group of conductive bumps while leaving the cross-sectional area of the first group of conductive bumps unchanged from the first design. 1 modify the design; and
and forming the conductive bumps on the interposer according to the second design. The semiconductor device of claim 5 , wherein after the conductive bumps are formed on the interposer according to the second design, the first group of conductive bumps and the second group of conductive bumps have different cross-sectional areas. how to form The method of claim 5 , wherein the first predetermined range is greater than 25% and the second predetermined range is between 15% and 25%. 8. The method of claim 7, wherein modifying the first design comprises increasing the dimension of the second group of conductive bumps by 10% to 25%. A method of forming a semiconductor device, comprising:
modifying the first design for conductive bumps to a second design for the conductive bumps, wherein the conductive bumps in the first design have the same cross-sectional area and are on a first side of an interposer; and
The conductive bumps of the first design are,
a first group of conductive bumps having a first bump pattern density and in a first area on the first side of the interposer; and
a second group of conductive bumps having a second bump pattern density and in a second region of the first side of the interposer, wherein the first bump pattern density is higher than the second bump pattern density;
modifying the first design to the second design for the conductive bumps comprises increasing the cross-sectional area of the second group of conductive bumps in the second region;
and forming the conductive bumps on the first side of the interposer according to the second design. 10. The method of claim 9, wherein the cross-sectional area of the conductive bumps of the first group remains unchanged between the first design and the second design.

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