KR102311482B1 - Organic light emitting display device - Google Patents

Abstract

An embodiment of the present invention relates to an organic light emitting diode display capable of compensating for a kickback voltage and a threshold voltage of a scan transistor as well as characteristics of a driving transistor such as a threshold voltage and electron mobility of a driving transistor. An organic light emitting diode display according to an embodiment of the present invention includes: a display panel including pixels connected to data lines, sensing lines, scan lines, and sensing signal lines; and a sensing data output unit configured to sense currents flowing from the pixels to the sensing lines and output sensing data. The pixel includes: a driving transistor for adjusting the amount of current flowing to the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage; a first transistor turned on by the scan signal of the scan line to supply the data voltage of the data line to the gate electrode of the driving transistor; and a second transistor turned on by the sensing signal of the sensing signal line to connect the source electrode of the driving transistor to the sensing line. The sensing data output unit senses a current of the driving transistor flowing through the sensing line in a state in which the first and second transistors are turned on in a first sensing mode to output sensing data.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

An embodiment of the present invention relates to an organic light emitting display device.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, in recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

Among them, the organic light emitting display device can be driven at a low voltage, is thin, has an excellent viewing angle, and has a fast response speed. An organic light emitting diode display includes a display panel including data lines, scan lines, a plurality of pixels formed at intersections of data lines and scan lines, a scan driver supplying scan signals to the scan lines, and data lines. and a data driver supplying data voltages. Each of the pixels includes an organic light emitting diode, a driving transistor that adjusts the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, and data of the data line in response to the scan signal of the scan line. and a scan transistor supplying a voltage to the gate electrode of the driving transistor.

The threshold voltage and electron mobility of the driving transistor may vary for each pixel due to a process deviation during manufacturing of the organic light emitting display device or a shift in threshold voltage of the driving transistor due to long-term driving. Accordingly, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode should be the same. The current supplied to the organic light emitting diode varies for each pixel. As a result, even when the same data voltage is applied to the pixels, the luminance emitted by the organic light emitting diode varies for each pixel. In order to solve this problem, a compensation method for compensating for the threshold voltage and electron mobility of the driving transistor has been proposed.

Also, even if the threshold voltage and electron mobility of the driving transistor are compensated, a problem may occur when the voltage of the gate electrode of the driving transistor is changed by the kickback voltage of the scan signal. Specifically, since the scan signal is supplied in the form of a pulse, when the scan signal is lowered from the high level voltage to the low level voltage, the voltage of the gate electrode of the driving transistor is lowered under the influence of the scan signal. Here, the kickback voltage may be defined as a voltage that is lowered under the influence of a scan signal at the gate electrode of the driving transistor. When the voltage of the gate electrode of the driving transistor is lowered by the kickback voltage, the voltage of the source electrode of the driving transistor may also be changed, and thus the gate-source voltage Vgs of the driving transistor may be changed. As a result, when the voltage of the gate electrode of the driving transistor is changed by the kickback voltage, a problem in that the current flowing to the organic light emitting diode through the driving transistor is changed may occur.

Also, the kickback voltage depends on how sharply the pulse of the scan signal falls from the high-level voltage to the low-level voltage. FIG. 1A shows the scan signal SCAN at the center of the display panel, and FIG. 1B shows the scan signal SCAN at the outside of the display panel. The RC delay at the center of the display panel is greater than the RC delay at the outside of the display panel. Accordingly, the polling delay width fw1 of the scan signal SCAN at the center of the display panel is wider than the polling delay width fw2 at the outer side of the display panel. The falling delay width of the scan signal SCAN means the width of the period in which the pulse of the scan signal SCAN falls from the gate high voltage VGH to the gate low voltage VGL. That is, the pulse of the scan signal SCAN falls sharply outside the center of the display panel.

As a result, the kickback voltage may vary depending on the position of the display panel, and thus may vary for each pixel. Therefore, there is a need for a compensation method for compensating for the kickback voltage. Furthermore, when the threshold voltage of the scan transistor is shifted due to long-term driving, the kickback voltage may vary, so a compensation method for compensating for the threshold voltage of the scan transistor is also required.

An embodiment of the present invention provides an organic light emitting diode display capable of compensating for a kickback voltage and a threshold voltage of a scan transistor as well as characteristics of a driving transistor such as a threshold voltage and electron mobility of the driving transistor.

An organic light emitting diode display according to an embodiment of the present invention includes: a display panel including pixels connected to data lines, sensing lines, scan lines, and sensing signal lines; and a sensing data output unit configured to sense currents flowing from the pixels to the sensing lines and output sensing data, wherein the pixel adjusts the amount of current flowing to the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage. driving transistor; a first transistor turned on by the scan signal of the scan line to supply the data voltage of the data line to the gate electrode of the driving transistor; and a second transistor turned on by a sensing signal of the sensing signal line to connect a source electrode of the driving transistor to the sensing line, wherein the sensing data output unit is the first and second transistors in the first sensing mode. In a state in which the transistors are turned on, a current of the driving transistor flowing through the sensing line is sensed to output sensed data.

In an embodiment of the present invention, the current of the driving transistor that is not affected by the kickback voltage and the threshold voltage of the scan transistor may be sensed and output as sensed data in the first sensing mode. In addition, in the embodiment of the present invention, the current of the driving transistor affected by the kickback voltage and the threshold voltage of the scan transistor may be sensed and output as sensed data in the second sensing mode. As a result, in the embodiment of the present invention, digital video data is corrected with correction data based on sensing data reflecting the kickback voltage and the threshold voltage of the scan transistor as well as characteristics of the driving transistor such as the threshold voltage and electron mobility of the driving transistor. Therefore, it is possible to compensate not only the characteristics of the driving transistor but also the kickback voltage and the threshold voltage of the scan transistor.

1A and 1B are waveform diagrams showing a scan signal at the center and the outside of a display panel;
2 is a block diagram illustrating an organic light emitting display device according to an embodiment of the present invention.
3 is a block diagram illustrating the data driver of FIG. 2 in detail;
FIG. 4 is a circuit diagram showing the pixel and the sensing unit of FIG. 2 in detail;
5 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a display mode, a gate voltage and a source voltage of a driving transistor, and second to fourth switch signals;
6A to 6C are exemplary views showing a pixel and a sensing unit during first to third periods of a display mode;
7 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a first sensing mode, a gate voltage and a source voltage of a driving transistor, a voltage of a sensing node, and second to fourth switch signals;
8A to 8C are exemplary views illustrating a pixel and a sensing unit during first to third periods of a first sensing mode;
9 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a second sensing mode, a gate voltage and a source voltage of a driving transistor, a voltage of a sensing node, and second to fourth switch signals;
10A to 10C are exemplary views illustrating a pixel and a sensing unit during first to third periods of a second sensing mode;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. The names of the components used in the following description are selected in consideration of the ease of writing the specification, and may be different from the names of the actual products.

2 is a block diagram illustrating an organic light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 2 , an organic light emitting display device according to an embodiment of the present invention includes a display panel 10 , a data driver 20 , a scan driver 30 , a sensing driver 40 , a timing controller 50 , and a digital and a data correction unit 60 .

The display panel 10 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area in which pixels P are provided to display an image. The display panel 10 includes data lines D1 to Dm, where m is a positive integer greater than or equal to 2), sensing lines SE1 to SEm, scan lines S1 to Sn, n is a positive integer greater than or equal to 2), and Sensing signal lines SS1 to SSn are provided. The data lines D1 to Dm and the sensing lines SE1 to SEm may cross the scan lines S1 to Sn and the sensing signal lines SS1 to SSn. The data lines D1 to Dm and the sensing lines SE1 to SEm may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SS1 to SSn may be parallel to each other.

Each of the pixels P is any one of the data lines D1 to Dm, any one of the sensing lines SE1 to SEm, any one of the scan lines S1 to Sn, and the sensing signal lines SS1 ~SSn) can be connected to any one of. Each of the pixels P of the display panel 10 includes an organic light emitting diode (OLED) and a pixel driver PD supplying current to the organic light emitting diode (OLED) as shown in FIG. 4 . As shown in FIG. 4 , the pixel driver PD includes a driving transistor DT, a first transistor T1 controlled by a scan signal of a scan line, and a second transistor T2 controlled by a sensing signal of a sensing signal line. ), and a capacitor (C). A detailed description of the pixel P will be described later with reference to FIG. 4 .

When a scan signal is supplied from the scan line connected to the pixel P in the display mode, the pixel driver PD receives the light emitting data voltage of the data line connected to the pixel P, and according to the light emitting data voltage, the organic light emitting diode (OLED) supplies current. When a scan signal is supplied from the scan line connected to the pixel P in the first sensing mode, the pixel driver PD receives the first sensing data voltage of the data line connected to the pixel P, and receives the kickback voltage and the first A current flows through the sensing line connected to the pixel P in a state that is not affected by the threshold voltage of the transistor T1. When the scan signal is supplied from the scan line connected to the pixel P in the second sensing mode, the pixel driver PD receives the first sensing data voltage of the data line connected to the pixel P, and receives the kickback voltage and the first A current flows through the sensing line connected to the pixel P while being affected by the threshold voltage of the transistor T1. A detailed description of the operation of the pixel P in the display mode will be described later with reference to FIGS. 5 and 6A to 6C , and detailed description of the operation of the pixel P in the first sensing mode will be provided in FIGS. 7 and 8A to FIG. 8A to FIG. It will be described later with reference to FIG. 8C , and detailed description of the operation of the pixel P in the second sensing mode will be described later with reference to FIGS. 9 and 10A to 10C .

The data driver 20 includes a data voltage supply unit 21 , an initialization voltage supply unit 22 , and a sensing data output unit 23 as shown in FIG. 3 .

The data voltage supply unit 21 is connected to the data lines D1 to Dm to supply data voltages. The data voltage supply unit 21 receives the correction data CDATA, the first sensing data SDATA1 , or the second sensing data SDATA2 and the data timing control signal DCS from the timing control unit 50 .

The data voltage supply unit 21 converts the correction data CDATA into light emitting data voltages according to the data timing control signal DCS in the display mode and supplies the converted data to the data lines D1 to Dm. The emission data voltage is a voltage for emitting light with a predetermined luminance of the organic light emitting diode (OLED) of the pixel (P). When the correction data CDATA supplied to the data driver 20 is 8 bits, the light emitting data voltage may be supplied as any one of 256 voltages.

The data voltage supply unit 21 converts the first sensing data SDATA1 into a first sensing data voltage according to the data timing control signal DCS in the first sensing mode and supplies it to the data lines D1 to Dm. The first sensing data voltage is a voltage for sensing the current of the driving transistor DT of the pixel P that is not affected by the kickback voltage and the threshold voltage of the first transistor T1 .

The data voltage supply unit 21 converts the second sensing data SDATA2 into a second sensing data voltage according to the data timing control signal DCS in the second sensing mode and supplies it to the data lines D1 to Dm. The second sensing data voltage is a voltage for sensing the current of the driving transistor DT of the pixel P affected by the kickback voltage and the threshold voltage of the first transistor T1 .

The initialization voltage supply unit 22 is connected to the sensing lines SE1 to SEm to supply the first initialization voltage VREF1. The initialization voltage supply unit 22 receives the first switch signal SCS1 from the timing controller 50 and receives the first initialization voltage VREF1 from a power supply source (not shown). The initialization voltage supply unit 22 may include first switches SW11 to SW1m connected to the sensing lines SE1 to SEm as shown in FIG. 3 . When the first switches SW11 to SW1m are turned on, the first initialization voltage VREF1 is supplied to the sensing lines SE1 to SEm.

The first switches SW11 to SW1m are switched by the first switch signal SCS1. For example, the first switches SW11 to SW1m are turned on when the first switch signal SCS1 of the first logic level voltage is input, and the first switch signal SCS1 of the second logic level voltage is turned on. When input, it may be turned off.

The sensing data output unit 23 is connected to the sensing lines SE1 to SEm to convert currents flowing from the pixels P to the sensing lines SE1 to SEm into voltages, and converts the converted voltages into digital data. It is converted into sensing data (SD). The sensing data output unit 23 outputs the sensing data SD to the digital data correction unit 60 .

Specifically, the sensing data output unit 23 may include sensing units SU1 to SUm. Each of the sensing units SU1 to SUm is connected to each of the sensing lines SE1 to SEm. Each of the sensing units SU1 to SUm is connected to the sensing line as shown in FIG. 4 to convert a current flowing from the pixel P to the sensing line into a voltage. A current-voltage converter CVC and a current-voltage converter CVC. It may include an analog-to-digital converter (ADC) that converts the output voltage of the digital data to the sensing data SD.

The current-voltage converter CVC of each of the sensing units SU1 to SUm receives the second to fourth switch signals SCS2 , SCS3 and SCS4 from the timing controller 50 , and receives the second to fourth switch signals SCS2 , SCS3 and SCS4 from the power supply source (not shown). A second initialization voltage VREF2 is received. The second initialization voltage VREF2 may be the same DC voltage as the first initialization voltage VREF1 , but is not limited thereto, and may be a DC voltage different from the first initialization voltage VREF1 . The second to fourth switches SW2 , SW3 , and SW4 of the current-voltage converter CVC are switched according to the second to fourth switch signals SCS2 , SCS3 , and SCS4 . The second initialization voltage VREF2 may be supplied to the non-inverting terminal (+) of the operational amplifier OA of the current-voltage converter CVC. A detailed description of each of the sensing units SU1 to SUm will be described later with reference to FIG. 4 .

The scan driver 30 is connected to the scan lines S1 to Sn to supply scan signals. The scan driver 30 supplies scan signals to the scan lines S1 to Sn according to the scan timing control signal SCS input from the timing controller 50 . The scan driver 30 may sequentially supply scan signals to the scan lines S1 to Sn, and in this case, may include a shift register.

The scan signal waveform of the scan driver 30 in the display mode, the scan signal waveform of the scan driver 30 in the first sensing mode, and the scan signal waveform of the scan driver 30 in the second sensing mode may be different from each other. In this case, it should be noted that the scan timing control signal SCS in the display mode, the scan timing control signal SCS in the first sensing mode, and the scan timing control signal SCS in the second sensing mode are different from each other. A detailed description of the scan signal waveform of the scan driver 30 will be described later with reference to FIGS. 5, 7 and 9 .

The sensing driver 40 is connected to the sensing signal lines SE1 to SEn to supply sensing signals. The sensing driver 40 supplies sensing signals to the sensing signal lines SS1 to SSn according to the sensing timing control signal SENCS input from the timing controller 50 . The sensing driver 40 may sequentially supply sensing signals to the sensing lines SE1 to SEn, and in this case, may include a shift register.

The sensing signal waveform of the sensing driver 40 in the display mode, the scan signal waveform of the scan driver 30 in the first sensing mode, and the scan signal waveform of the scan driver in the second sensing mode may be different from each other. In this case, it should be noted that the sensing timing control signal SENCS in the display mode, the sensing timing control signal SENCS in the first sensing mode, and the sensing timing control signal SENCS in the second sensing mode are different from each other. A detailed description of the sensing signal waveform of the sensing driver 40 will be described later with reference to FIGS. 5, 7 and 9 .

The scan driver 30 and the sensing driver 40 are formed in the form of a driving chip and mounted on a flexible film connected to the display panel 10 , or include a plurality of transistors in a gate driver in panel (GIP) method. may be directly formed in the non-display area of the display panel 10 . In addition, each of the scan driver 30 and the sensing driver 40 may be provided on one side or both sides of the display panel 10 . When the display panel 10 is a 40-inch or larger large-screen display panel, each of the scan driver 30 and the sensing driver 40 is preferably provided at both edges of the display panel 10 . In this case, the scan drivers 30 provided on both sides simultaneously supply scan signals to the scan lines S1 to Sn, and the sensing drivers 40 provided on both sides simultaneously transmit sensing signals to the sensing lines SS1 to SSn. By supplying it, it is possible to reduce the delay of the scan signal and the sensing signal due to the RC delay.

The timing controller 50 receives the correction data CDATA, the first sensing data SDATA1 or the second sensing data SDATA2 and a timing signal from the digital data correction unit 60 . The timing signal may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 50 generates timing control signals for controlling operation timings of the data driver 20 , the scan driver 30 , and the sensing driver 40 . The timing control signals are the data timing control signal DCS for controlling the operation timing of the data driver 20 , the scan timing control signal SCS for controlling the operation timing of the scan driver 30 , and the sensing driver 40 . and a sensing timing control signal SENCS for controlling the operation timing.

The timing controller 50 controls the data driving unit 20, the scan driving unit 30, and the sensing driving unit 40 in any one of the display mode, the first sensing mode, and the second sensing mode according to the mode signal MODE. make it work The display mode is a mode in which the pixels P of the display panel 10 display an image, and the first and second sensing modes control the current of each of the driving transistors DT of the pixels P of the display panel 10 . This is the sensing mode. In particular, the first sensing mode is a mode for sensing the kickback voltage and the current of the driving transistor DT not affected by the threshold voltage of the first transistor T1, and the second sensing mode is the kickback voltage and the first transistor T1. ) is a mode for sensing the current of the driving transistor DT affected by the threshold voltage.

When the waveform of the scan signal supplied to each of the pixels P and the waveform of the sensing signal are changed in each of the display mode, the first sensing mode, and the second sensing mode, the display mode, the first sensing mode, and the second sensing mode, respectively In , the timing control signal DCS, the scan timing control signal SCS, and the sensing timing control signal SENCS may also be changed. Accordingly, the timing control unit 50 controls the data timing control signal DCS, the scan timing control signal SCS, and the sensing timing control signal SENCS according to any of the display mode, the first sensing mode, and the second sensing mode. create

The timing controller 50 outputs the correction data CDATA, the first sensing data SDATA1 or the second sensing data SDATA2 and the data timing control signal DCS to the data driver 20 . The timing controller 50 outputs the scan timing control signal SCS to the scan driver 30 . The timing controller 50 outputs the sensing timing control signal SENCS to the sensing driver 40 .

In addition, the timing control unit 50 includes a first switching control signal SCS1 for controlling the first switches SW11 to SW1m of the initialization voltage supply unit 22 of the data driver 20 , and a sensing data output unit 23 . Generates and outputs second to fourth switching control signals SCS2, SCS3, and SCS4 for controlling the second to fourth switches SW2, SW3, and SW4 of the sensing units SU1 to SUm, respectively.

In addition, the timing controller 50 controls the data driving unit 20 , the scan driving unit 30 , the sensing driving unit 40 , and the digital data correcting unit 60 in any one of the display mode, the first sensing mode, and the second sensing mode. A mode signal MODE is generated depending on whether to drive in mode. The timing controller 50 internally operates the data driver 20 and the scan driver 30 in any one of the display mode, the first sensing mode, and the second sensing mode according to the mode signal MODE according to the mode signal MODE. ), and the sensing driving unit 40 is operated. The timing controller 50 outputs the mode signal MODE to the digital data correction unit 60 .

The digital data compensator 60 receives sensing data SD from the data driver 20 . The digital data corrector 60 may store the sensing data SD in a memory (not shown). The sensing data SD includes the characteristics of each of the pixels P, for example, the kickback voltage and the threshold voltage of the first transistor T1. It is a value sensed by the current of the driving transistor DT that is not affected by T1).

In addition, the digital data compensator 60 receives digital video data DATA from the outside and receives the mode signal MODE from the timing controller 50 . The digital data correction unit 60 outputs digital data to the timing control unit 50 according to the mode signal MODE.

The digital data compensator 60 corrects the digital video data DATA with the correction data CDATA based on the sensed data SD in the display mode, so that the threshold voltage, electron mobility, and kickback voltage of the driving transistor DT are performed. , and the threshold voltage of the first transistor T1 may be externally compensated. Specifically, the digital data correction unit 60 calculates the threshold voltage and electron mobility of the driving transistor DT, the kickback voltage, and the threshold voltage of the first transistor T1 from the sensing data SD using a predetermined algorithm. Compensation data may be calculated, and compensation data CDATA may be calculated by applying the calculated data to digital video data DATA. The correction data CDATA is data obtained by compensating for the threshold voltage, electron mobility, kickback voltage, and threshold voltage of the first transistor T1 of the driving transistor DT of each of the pixels P. The digital data correction unit 60 supplies the correction data CDATA to the timing control unit 50 in the display mode.

The digital data corrector 60 supplies the first sensing data SDATA1 stored in a memory (not shown) to the timing controller 50 in the first sensing mode. The first sensing data SDATA1 is data for sensing the current of the driving transistor DT that is not affected by the kickback voltage and the threshold voltage of the first transistor T1 in each of the pixels P.

The digital data corrector 60 supplies the second sensing data SDATA2 stored in a memory (not shown) to the timing controller 50 in the second sensing mode. The second sensing data SDATA2 is data for sensing the current of the driving transistor DT affected by the kickback voltage and the threshold voltage of the first transistor T1 in each of the pixels P. The second sensing data SDATA2 is data obtained by compensating for the threshold voltage and electron mobility of the driving transistor DT. The digital data corrector 60 may calculate the second sensing data SDATA2 by performing another algorithm using the sensing data SD sensed in the first sensing mode and the first sensing data SDATA1 . . The digital data compensator 60 stores the second sensing data SDATA2 in a memory (not shown).

The digital data corrector 60 may be built into the timing controller 50 .

FIG. 4 is a circuit diagram illustrating in detail the pixel and the sensing unit of FIG. 2 . In FIG. 4 , for convenience of explanation, the jth (j is a positive integer satisfying 1≤j≤m) data line Dj, the jth sensing line SEj, and the kth (k is 1≤k≤n) Only the pixel P connected to the scan line Sk, the k-th sensing signal line SSk, and the j-th sensing unit SUj connected to the j-th sensing line SEj are shown.

Referring to FIG. 4 , the pixel P of the display panel 10 includes an organic light emitting diode (OLED), an organic light emitting diode (OLED), and a pixel driver (PD) supplying current to the j-th sensing line (SEj). do. The pixel driver PD may include a driving transistor DT, first and second transistors ST1 and ST2, and a capacitor C as shown in FIG. 4 .

The organic light emitting diode OLED emits light according to a current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT, and the cathode electrode may be connected to the low potential voltage line VSSL to which a low potential voltage lower than the high potential voltage is supplied.

An organic light emitting diode (OLED) may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In an organic light emitting diode (OLED), when a voltage is applied to an anode electrode and a cathode electrode, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light. An anode electrode of the organic light emitting diode OLED may be connected to a source electrode of the driving transistor DT, and a cathode electrode may be connected to a second power voltage line ELVSSL to which a second power voltage is supplied.

The driving transistor DT is provided between the first power voltage line VDDL and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the first power voltage line VDDL to the organic light emitting diode OLED according to a voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first transistor ST1 , the source electrode is connected to the anode electrode of the organic light emitting diode OLED, and the drain electrode is the first electrode to which the first power voltage is supplied. 1 may be connected to the power voltage line ELVDDL.

The first transistor ST1 is turned on by the k-th scan signal of the k-th scan line Sk to supply the voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. The gate electrode of the first transistor T1 is connected to the k-th scan line Sk, the first electrode is connected to the gate electrode of the driving transistor DT, and the second electrode is connected to the j-th data line Dj. can be The first transistor ST1 may be collectively referred to as a scan transistor.

The second transistor ST2 is turned on by the k-th sensing signal of the k-th sensing signal line SSk to connect the j-th sensing line SEj to the source electrode of the driving transistor DT. The gate electrode of the second transistor ST2 is connected to the k-th initialization line SENk, the first electrode is connected to the j-th sensing line SEj, and the second electrode is connected to the source electrode of the driving transistor DT. can be

A first electrode of each of the first and second transistors ST1 and ST2 may be a source electrode, and the second electrode may be a drain electrode, but it should be noted that the present invention is not limited thereto. That is, the first electrode of each of the first and second transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The first capacitor C1 is provided between the gate electrode and the source electrode of the first driving transistor DT1 . The first capacitor C1 stores a difference voltage between the gate voltage and the source voltage of the first driving transistor DT1 .

In FIG. 4 , the driving transistor DT and the first and second transistors ST1 and ST2 have been mainly described as being formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but it should be noted that the present invention is not limited thereto. The driving transistor DT and the first and second transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the timing diagrams of FIGS. 5, 7 and 9 are appropriate for the characteristics of the P-type MOSFET. can be modified to

The j-th sensing unit SUj includes a current-voltage converter CVC and an analog-to-digital converter ADC. The current-voltage converter CVC converts a current flowing from the pixel P to the j-th sensing line SEj into a voltage. The current-voltage converter CVC may include an operational amplifier OA, a feedback capacitor Cf, and second to fourth switches SW2 , SW3 , and SW4 .

The operational amplifier OA includes an inverting terminal (-), a non-inverting terminal (+), and an output terminal (o). The inverting terminal (-) is connected to the fourth switch SW4, and the non-inverting terminal (+) is connected to the second initialization voltage line VREFL2 to which the second initialization voltage VREF2 is supplied. The output terminal o is connected to the third switch SW3. The second initialization voltage VREF2 may be the same DC voltage as the first initialization voltage VREF1 , but is not limited thereto, and may be a DC voltage different from the first initialization voltage VREF1 .

The second switch SW2 is switched according to the second switch signal SCS2. The second switch SW2 is turned on by the second switch signal SCS2 to connect the inverting terminal (-) and the output terminal (o) of the operational amplifier OA.

The third switch SW3 is switched according to the third switch signal SCS3. The third switch SW3 is turned on by the third switch signal SCS3 to connect the output terminal o of the operational amplifier OA and the analog-to-digital converter ADC.

The fourth switch SW4 is switched according to the fourth switch signal SCS4. The fourth switch SW4 is turned on by the fourth switch signal SCS4 to connect the inverting terminal (-) of the operational amplifier OA and the j-th sensing line SEj.

The feedback capacitor Cf is connected between the inverting terminal (-) and the output terminal o of the operational amplifier OA. When the second switch SW2 is turned on, the feedback capacitor Cf is initialized to zero voltage (OV) because the inverting terminal (-) and the output terminal (o) of the operational amplifier OA are shorted. can be Also, when the second switch SW2 is turned off and the third and fourth switches SW3 and SW4 are turned on, the feedback capacitor Cf is connected from the pixel P to the j-th sensing line SEj. The voltage output to the output terminal o of the operational amplifier OA is changed by charging the current flowing through the . A detailed description thereof will be described later with reference to FIGS. 7 and 9 .

The storage capacitor Cs is connected between the sensing node Nsen and the ground voltage source GND. The storage capacitor Cs is a voltage output from the operational amplifier OA when the second switch SW2 is turned off and the third and fourth switches SW3 and SW4 are turned on, that is, the sensing node ( Nsen) of the voltage (Vsen) is stored.

The analog-to-digital converter ADC converts the voltage Vsen of the sensing node Nsen into digital data to generate the sensing data SD. The analog-to-digital converter ADC outputs the sensed data SD to the digital data corrector 60 .

The organic light emitting display device according to an embodiment of the present invention is driven in a display mode, a first sensing mode, and a second sensing mode, and the pixel ( Waveforms of the scan signal and the sensing signal supplied to P) are different. Due to this, the operation of the pixel P is different. Hereinafter, the operation of the pixel P in the display mode will be examined in conjunction with FIGS. 5 and 6A to 6C, and the operation of the pixel P in the first sensing mode will be described in conjunction with FIGS. 7 and 8A to 8C. Looking at it, the operation of the pixel P in the second sensing mode will be described in conjunction with FIGS. 9 and 10A to 10C .

5 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a display mode, a gate voltage and a source voltage of a driving transistor, and second to fourth switch signals. In FIG. 5 , for convenience of explanation, the kth scan signal SCANk supplied to the kth scan line Sk connected to the pixel P of FIG. 4 and the kth sensing signal supplied to the kth sensing signal line SSk of FIG. The signal SENSk, the gate voltage Vg and the source voltage Vs of the driving transistor DT, and the second to fourth switches of the current-voltage converter CVC connected to the j-th sensing line SEj ( Only the second to fourth switch signals SCS2, SCS3, and SCS4 supplied to SW2, SW3, and SW4 are exemplified.

Referring to FIG. 5 , in the display mode, one frame period may be divided into first to third periods t1 to t3 . The first period t1 is a period in which the source electrode of the driving transistor DT is initialized to the first initialization voltage VREF1. The second period t2 is a period in which the light emitting data voltage Vdata is supplied to the gate electrode of the driving transistor DT. The second period t2 may be one horizontal period. One horizontal period indicates a period in which data voltages are supplied to pixels P of one horizontal line, and the pixels P of one horizontal line may be connected to the same scan line. The third period t3 is a period in which the organic light emitting diode OLED emits light according to the current of the driving transistor DT.

The scan driver 30 supplies the k-th scan signal SCANk of the gate-off voltage Voff to the k-th scan line Sk during the first and third periods t1 and t3, and the second period t2 ), the k-th scan signal SCANk of the gate-on voltage Von may be supplied. The sensing driver 40 supplies the k-th sensing signal SENSk of the gate-on voltage Von to the k-th sensing signal line SSk during the first and second periods t1 and t2, and the third period ( During t3), the k-th sensing signal SENSk of the gate-off voltage Voff may be supplied. When the first and second transistors T1 and T2 of each of the pixels P are formed of an N-type MOSFET as shown in FIG. 4 , the gate-on voltage Von is applied to the first and second transistors of the pixels P, respectively. A gate high voltage capable of turning on the two transistors T1 and T2 , and the gate-off voltage Voff turns off the first and second transistors T1 and T2 of the pixels P, respectively. It may be a gate-low voltage that can make

The data voltage supply unit 21 supplies the data voltage to the pixel P connected to the k-th scan line Sk, the light-emitting data voltage Vdata is applied to the j-th data line Dj during the second period t2. can supply

The timing controller 50 applies the second switch signal SCS2 of the second logic level voltage V2 to the j-th sensing line SEj in the display mode to the second switch SW2 of the current-voltage converter CVC connected to the j-th sensing line SEj. ), and supply the third switch signal SCS3 of the second logic level voltage V2 to the third switch SW3 of the current-voltage converter CVC connected to the j-th sensing line SEj, and , the fourth switch signal SCS4 of the first logic level voltage V1 is supplied to the fourth switch SW4.

Hereinafter, the operation of the pixel P in the display mode will be described in detail with reference to FIGS. 6A to 6C .

6A to 6C are exemplary views illustrating a pixel and a sensing unit during first to third periods of a display mode. 6A to 6C, the turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in a display mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 4, 5, and 6A to 6C.

In the display mode, in the second and third switches SW2 and SW3, the second and third switch signals SCS2 and SCS3 of the second logic level voltage V2 are turned off, and the fourth switch SW4 is turned off. is turned on by the fourth switch signal SCS4 of the first logic level voltage V1. Due to the turn-on of the fourth switch SW4, the j-th sensing line SEj is connected to the inverting terminal (-) of the operational amplifier OA. On the other hand, since the second initialization voltage VREF2 is supplied to the non-inverting terminal (+) of the operational amplifier OA, the second initialization voltage ( VREF2) is supplied. Accordingly, the second initialization voltage VREF2 is supplied to the j-th sensing line SEj.

Referring to FIG. 6A , during the first period t1 , the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk. .

During the first period t1 , the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during the first period t1 , the second initialization voltage VREF2 of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT. That is, during the first period t1 , the source electrode of the driving transistor DT is initialized to the second initialization voltage VREF2 .

Referring to FIG. 6B , during the second period t2 , the first transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. . Due to the turn-on of the first transistor ST1 during the second period t2 , the light emission data voltage Vdata of the j-th data line Dj is supplied to the gate electrode of the driving transistor DT. The emission data voltage Vdata is a voltage in which the threshold voltage and electron mobility of the driving transistor DT, the kickback voltage, and the threshold voltage of the first transistor T1 are compensated.

During the second period t2, the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during the second period t2 , the second initialization voltage VREF2 of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT.

Referring to FIG. 6C , during the third period t3 , the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk. . During the third period t3, the second transistor ST2 is turned off by the k-th sensing signal SENSk of the gate-off voltage Voff supplied to the k-th sensing signal line SSk.

A current Ids according to a voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT flows to the organic light emitting diode OLED during the third period t3. Accordingly, the organic light emitting diode (OLED) emits light. Hereinafter, for convenience of explanation, “current flowing through the driving transistor DT according to the voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT” is defined as “the current of the driving transistor”. do.

At this time, since the emission data voltage Vdata is a voltage in which the threshold voltage and electron mobility of the driving transistor DT, the kickback voltage, and the threshold voltage of the first transistor T1 are compensated, the organic light emitting diode during the third period t3 The current Ids of the driving transistor DT flowing through the OLED does not depend on the threshold voltage and electron mobility of the driving transistor DT, the kickback voltage, and the threshold voltage of the first transistor T1 .

As described above, in the embodiment of the present invention, in the display mode, the light emitting data voltage in which the threshold voltage and electron mobility of the driving transistor DT, the kickback voltage, and the threshold voltage of the first transistor T1 are compensated for are converted to the pixel (P). supply to As a result, in the embodiment of the present invention, the organic light emitting diode (OLED) of the pixel (P) is driven not depending on the threshold voltage and electron mobility of the driving transistor (DT), the kickback voltage, and the threshold voltage of the first transistor (T1). Light may be emitted according to the current Ids of the transistor DT. Accordingly, according to the exemplary embodiment of the present invention, the luminance uniformity of the pixels P may be increased.

7 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a first sensing mode, a gate voltage and a source voltage of a driving transistor, a voltage of a sensing node, and second to fourth switch signals. In FIG. 7 , for convenience of explanation, the k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P of FIG. 4 and the k-th sensing signal supplied to the k-th sensing signal line SSk are shown in FIG. The signal SENSk, the gate voltage Vg and the source voltage Vs of the driving transistor DT, the voltage Vsen of the sensing node Nsen, and the current-voltage converter connected to the j-th sensing line SEj ( Only the second to fourth switch signals SCS2, SCS3, and SCS4 supplied to the second to fourth switches SW2, SW3, and SW4 of the CVC are exemplified.

Referring to FIG. 7 , in the first sensing mode, one frame period may be divided into first to third periods t1' to t3'. The first period t1' is a period in which the first sensing data voltage Vdata_S1 is supplied to the gate electrode of the driving transistor DT and the source electrode is initialized to the second initialization voltage VREF2. In the second period t2', the current Isen1 of the driving transistor DT flowing from the pixel P to the j-th sensing line SEj is applied to a voltage according to a voltage difference between the gate voltage and the source voltage of the driving transistor DT. is the period of conversion to The third period t3' is a period in which the voltage Vsen of the sensing node Nsen is converted into digital data.

The scan driver 30 supplies the k-th scan signal SCANk of the gate-on voltage Von to the k-th scan line Sk during the first and second periods t1' and t2', and the third period. During (t3'), the k-th scan signal SCANk of the gate-off voltage Voff may be supplied. The sensing driver 40 supplies the k-th sensing signal SENSk of the gate-on voltage Von to the k-th sensing signal line SSk during the first and second periods t1' and t2', and the third During the period t3', the kth sensing signal SENSk of the gate-off voltage Voff may be supplied. When the first and second transistors T1 and T2 of each of the pixels P are formed of an N-type MOSFET as shown in FIG. 4 , the gate-on voltage Von is applied to the first and second transistors of the pixels P, respectively. A gate high voltage capable of turning on the two transistors T1 and T2 , and the gate-off voltage Voff turns off the first and second transistors T1 and T2 of the pixels P, respectively. It may be a gate-low voltage that can make

The data voltage supply unit 21 supplies the data voltage to the pixel P connected to the k-th scan line Sk, during the first and second periods t1' and t2', the j-th data line Dj. ) may be supplied with the first sensing data voltage Vdata_S1.

The timing controller 50 transmits the second switch signal SCS2 of the first logic level voltage V1 to the second switch SW2 of the current-voltage converter CVC during the first period t1 ′ of the first sensing mode. ) and supply the second switch signal SCS2 of the second logic level voltage V2 during the second and third periods t2' and t3'. The timing controller 50 transmits the first logic level voltage V1 to the third switch SW3 of the current-voltage converter CVC during the first and second periods t1' and t2' of the first sensing mode. of the third switch signal SCS3 is supplied, and the third switch signal SCS3 of the second logic level voltage V2 is supplied during the third period t3'. The timing controller 50 transmits the first logic level voltage V1 to the fourth switch SW4 of the current-voltage converter CVC during the first to third periods t1' to t3' of the first sensing mode. of the fourth switch signal SCS4 is supplied to the fourth switch SW4.

Hereinafter, the operation of the pixel P in the first sensing mode will be described in detail with reference to FIGS. 8A to 8C .

8A to 8C are exemplary views illustrating a pixel and a sensing unit during first to third periods of the first sensing mode. 8A to 8C, the turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in the first sensing mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 4, 7, and 8A to 8C.

During the first to third periods t1' to t3' of the first sensing mode, the fourth switch SW4 is turned on by the fourth switch signal SCS4 of the first logic level voltage V1. Due to the turn-on of the fourth switch SW4 during the first to third periods t1' to t3' of the first sensing mode, the j-th sensing line SEj is connected to the inverting terminal (−) of the operational amplifier OA. ) is connected to

Referring to FIG. 8A , during a first period t1', the first transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. do. Due to the turn-on of the first transistor ST1 during the first period t1 ′, the first sensing data voltage Vdata_S1 is supplied to the gate electrode of the driving transistor DT. The first sensing data voltage Vdata_S1 is a voltage for sensing characteristics of the driving transistor DT, such as the threshold voltage and electron mobility of the driving transistor DT.

During the first period t1', the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during the first period t1 ′, the second initialization voltage VREF2 of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT. That is, during the first period t1 ′, the source electrode of the driving transistor DT is initialized to the second initialization voltage VREF2 .

Meanwhile, the reason why the voltage of the j-th sensing line SEj is the second initialization voltage VREF2 during the first period t1' will be described below.

During the first period t1', the second switch SW2 of the current-voltage converter CVC is turned on by the second switch signal SCS2 of the first logic level voltage V1, and the third switch SW3 is turned on by the third switch signal SCS3 of the first logic level voltage V1. In addition, due to the turn-on of the second and third switches SW2 and SW3 during the first period t1', the inverting terminal (-) of the operational amplifier OA of the current-voltage converter CVC and The output terminal o is shorted. Therefore, the feedback capacitor Cf of the current-voltage converter CVC is initialized to zero voltage (OV). In particular, since the second initialization voltage VREF2 is supplied to the non-inverting terminal (+) of the operational amplifier OA, the second initialization voltage ( VREF2) is supplied. Accordingly, the second initialization voltage VREF2 is supplied to the output terminal o of the operational amplifier OA, the sensing node Nsen, and the j-th sensing line SEj.

Referring to FIG. 8B , during the second period t2', the first transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. do. Due to the turn-on of the first transistor ST1 during the second period t2', the gate electrode of the driving transistor DT maintains the first sensing data voltage Vdata_S1.

During the second period t2', the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during the second period t2 ′, the source electrode of the driving transistor DT maintains the second initialization voltage VREF2 .

During the second period t2', the second switch SW2 of the current-voltage converter CVC is turned off by the second switch signal SCS2 of the second logic level voltage V2, and the third switch SW3 is turned on by the third switch signal SCS3 of the first logic level voltage V1. Due to the turn-off of the second switch SW2, the inverting terminal (-) and the output terminal (o) of the operational amplifier OA of the current-voltage converter CVC are no longer connected, so that the operational amplifier OA works as an integrator. Accordingly, the operational amplifier OA converts the current Isen1 of the driving transistor DT flowing through the j-th sensing line SEj into a voltage. At this time, since the j-th sensing line SEj maintains the second initialization voltage VREF2 from the first period t1 ′, the current Isen1 of the driving transistor DT does not change and the current-voltage converter CVC does not change. ) can be quickly charged to the feedback capacitor (Cf). Accordingly, the voltage Vsen output from the output terminal o of the operational amplifier OA to the sensing node Nsen decreases linearly at the second initialization voltage VREF2.

Referring to FIG. 8C , during the third period t3 ′, the second switch SW2 of the current-voltage converter CVC is turned by the second switch signal SCS2 of the second logic level voltage V2 - is turned off, and the third switch SW3 is turned off by the third switch signal SCS3 of the second logic level voltage V2.

The analog-to-digital converter ADC converts the voltage Vsen of the sensing node Nsen stored in the storage capacitor Cs into the sensing data SD, which is digital data, during the third period t3'. The analog-to-digital converter ADC outputs the sensed data SD to the digital data corrector 60 .

As described above, in the embodiment of the present invention, in the first sensing mode, in a state in which the first and second transistors T1 and T2 are turned on, the driving transistor DT flowing to the j-th sensing line SEj is The current Isen1 is sensed and sensed data SD is output. As a result, in the embodiment of the present invention, in the first sensing mode, sensing data ( SD) can be printed.

9 is a waveform diagram illustrating a scan signal and a sensing signal supplied to a pixel in a first sensing mode, a gate voltage and a source voltage of a driving transistor, a voltage of a sensing node, and second to fourth switch signals. In FIG. 9 , for convenience of explanation, the k-th scan signal SCANk supplied to the k-th scan line Sk connected to the pixel P of FIG. 4 and the k-th sensing signal supplied to the k-th sensing signal line SSk are shown in FIG. The signal SENSk, the gate voltage Vg and the source voltage Vs of the driving transistor DT, the voltage Vsen of the sensing node Nsen, and the current-voltage converter connected to the j-th sensing line SEj ( Only the second to fourth switch signals SCS2, SCS3, and SCS4 supplied to the second to fourth switches SW2, SW3, and SW4 of the CVC are exemplified.

Referring to FIG. 9 , in the second sensing mode, one frame period may be divided into first to third periods t1″ to t3″. The first period t1″ is a period in which the first sensing data voltage Vdata_S1 is supplied to the gate electrode of the driving transistor DT and the source electrode is initialized to the second initialization voltage VREF2. The second period t2 ") is the driving that flows from the pixel P to the j-th sensing line SEj according to the voltage difference between the gate voltage and the source voltage of the driving transistor DT affected by the kickback voltage and the threshold voltage of the first transistor T1. It is a period in which the current Isen2 of the transistor DT is converted into a voltage. The third period t3 ″ is a period in which the voltage Vsen of the sensing node Nsen is converted into digital data.

The scan driver 30 supplies the k-th scan signal SCANk of the gate-on voltage Von to the k-th scan line Sk during the first period t1", and for the second and third periods t2" . The k-th sensing signal SENSk of the gate-on voltage Von may be supplied during t2"), and the k-th sensing signal SENSk of the gate-off voltage Voff may be supplied during the third period t3". When the first and second transistors T1 and T2 of each of the pixels P are formed of an N-type MOSFET as shown in FIG. 4 , the gate-on voltage Von is applied to the first and second transistors of the pixels P, respectively. A gate high voltage capable of turning on the two transistors T1 and T2 , and the gate-off voltage Voff turns off the first and second transistors T1 and T2 of the pixels P, respectively. It may be a gate-low voltage that can make

The data voltage supply unit 21 supplies the data voltage to the pixel P connected to the k-th scan line Sk, the second sensing data voltage is applied to the j-th data line Dj during the first period t1'. (Vdata_S2) can be supplied.

The timing controller 50 transmits the second switch signal SCS2 of the first logic level voltage V1 to the second switch SW2 of the current-voltage converter CVC during the first period t1 ″ of the second sensing mode. ) and supply the second switch signal SCS2 of the second logic level voltage V2 during the second and third periods t2" and t3". The timing controller 50 converts current-voltage The third switch signal SCS3 of the first logic level voltage V1 is supplied to the third switch SW3 of the sub CVC during the first and second periods t1″ and t2″ of the second sensing mode. and the third switch signal SCS3 of the second logic level voltage V2 is supplied during the third period t3 ″. The timing controller 50 transmits the first logic level voltage V1 to the fourth switch SW4 of the current-voltage converter CVC during the first to third periods t1″ to t3″ of the second sensing mode. of the fourth switch signal SCS4 is supplied.

Hereinafter, the operation of the pixel P in the second sensing mode will be described in detail with reference to FIGS. 10A to 10C .

10A to 10C are exemplary views illustrating a pixel and a sensing unit during first to third periods of the second sensing mode. In FIGS. 10A to 10C , the turned-off transistor is illustrated with a dotted line for convenience of description. Hereinafter, a method of driving a pixel in the second sensing mode according to an embodiment of the present invention will be described in detail in conjunction with FIGS. 4, 9 and 10A to 10C.

During the first to third periods t1" to t3" of the second sensing mode, the fourth switch SW4 is turned on by the fourth switch signal SCS4 of the first logic level voltage V1. Due to the turn-on of the fourth switch SW4 during the first to third periods t1″ to t3″ of the second sensing mode, the jth sensing line SEj is connected to the inverting terminal (−) of the operational amplifier OA. ) is connected to

Referring to FIG. 10A , during a first period t1 ″, the first transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. The second sensing data voltage Vdata_S2 is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first transistor ST1 during the first period t1″. The second sensing data voltage Vdata_S1 is a voltage for sensing the kickback voltage ΔVp and the threshold voltage of the first transistor ST1 .

During the first period t1", the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during (t1″), the second initialization voltage VREF2 of the j-th sensing line SEj is supplied to the source electrode of the driving transistor DT. That is, during the first period t1 ′, the source electrode of the driving transistor DT is initialized to the second initialization voltage VREF2 .

Meanwhile, the reason why the voltage of the j-th sensing line SEj is the second initialization voltage VREF2 during the first period t1 ″ will be described below.

During the first period t1", the second switch SW2 of the current-voltage converter CVC is turned on by the second switch signal SCS2 of the first logic level voltage V1, and the third switch SW3 is turned on by the third switch signal SCS3 of the first logic level voltage V1. Also, during the first period t1 ″, the second and third switches SW2 and SW3 are turned on. Due to the turn-on, the inverting terminal (-) and the output terminal (o) of the operational amplifier OA of the current-voltage converter CVC are short-circuited. Therefore, the feedback capacitor Cf of the current-voltage converter CVC is initialized to zero voltage (OV). In particular, since the second initialization voltage VREF2 is supplied to the non-inverting terminal (+) of the operational amplifier OA, the second initialization voltage ( VREF2) is supplied. Accordingly, the second initialization voltage VREF2 is supplied to the output terminal o of the operational amplifier OA, the sensing node Nsen, and the j-th sensing line SEj.

Referring to FIG. 10B , during the second period t2″, the first transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk. At the beginning of the second period t2", the k-th scan signal SCANk falls from the gate-on voltage Von to the gate-off voltage Voff, thereby causing the gate voltage Vg of the driving transistor DT. is affected by the kickback voltage (ΔVp). Here, the kickback voltage ΔVp may be defined as a voltage lowered by a pulse of a scan signal polled from the gate electrode of the driving transistor. That is, the gate voltage Vg of the driving transistor DT drops to “Vdata_S2-ΔVp”. The kickback voltage ΔVp increases as the k-th scan signal SCANk sharply drops from the gate-on voltage Von to the gate-off voltage Voff. As described in the background of the invention, the kickback voltage ΔVp may vary depending on the position of the display panel due to the RC delay, and thus it is necessary to compensate for this.

In addition, during the second period t2″, the gate voltage Vg of the driving transistor DT is changed according to the threshold voltage of the first transistor T1 such that the kickback voltage ΔVp is the same as the threshold voltage of the first transistor T1. Since it can be different, it can be said that it is also affected by the threshold voltage of the first transistor T1, so it is necessary to compensate for the threshold voltage of the first transistor T1.

During the second period t2", the second transistor ST2 is turned on by the k-th sensing signal SENSk of the gate-on voltage Von supplied to the k-th sensing signal line SSk. Due to the turn-on of the second transistor ST2 during (t2'), the source electrode of the driving transistor DT maintains the second initialization voltage VREF2.

During the second period t2", the second switch SW2 of the current-voltage converter CVC is turned off by the second switch signal SCS2 of the second logic level voltage V2, and the third switch SW3 is turned on by the third switch signal SCS3 of the first logic level voltage V1 Due to the turn-off of the second switch SW2, the operation of the current-voltage converter CVC Since the inverting terminal (-) and the output terminal (o) of the amplifier OA are no longer connected, the operational amplifier OA operates as an integrator. Converts the current Isen2 of the driving transistor DT into a voltage, in this case, since the j-th sensing line SEj maintains the second initialization voltage VREF2 from the first period t1', the driving transistor DT ) of the current Isen2 can be quickly charged in the feedback capacitor Cf of the current-voltage converter CVC without fluctuation, from the output terminal o of the operational amplifier OA to the sensing node Nsen. The output voltage Vsen linearly decreases from the second initialization voltage VREF2.

Referring to FIG. 10C , during the third period t3″, the second switch SW2 of the current-voltage converter CVC is turned by the second switch signal SCS2 of the second logic level voltage V2. is turned off, and the third switch SW3 is turned off by the third switch signal SCS3 of the second logic level voltage V2.

The analog-to-digital converter ADC converts the voltage Vsen of the sensing node Nsen stored in the storage capacitor Cs during the third period t3″ into sensing data SD, which is digital data. Analog-to-digital converter The ADC outputs the sensed data SD to the digital data correction unit 60 .

As described above, in the embodiment of the present invention, the current Isen2 of the driving transistor DT is in a state in which the first transistor T1 is turned off and the second transistor T2 is turned on in the second sensing mode. is sensed and the sensed data SD is output. As a result, in the embodiment of the present invention, the driving transistor is affected by the kickback voltage generated while the scan signal of the scan line is polled to turn off the first transistor T1 and the threshold voltage of the first transistor T1. The sensed data SD may be output by sensing the current Isen2 of (DT).

On the other hand, the sensing data output unit 23 according to the embodiment of the present invention supplies the reference current supplied from the initialization voltage source through the first switch SW1 to the current-voltage converter CVC and the reference data and the jth By comparing the sensing data SD obtained by supplying the current Isen2 of the driving transistor Isen flowing through the sensing line SEj to the current-voltage converter CVC, the kickback voltage and the threshold of the first transistor T1 are compared. The second sensing data voltage Vdata_S2 reflecting the characteristics of the driving transistor DT affected by the voltage may be sensed. Specifically, it is compared whether the same sensing data as reference data is output while changing the second sensing data voltage Vdata_S2 supplied to the pixel P. Through this, the embodiment of the present invention may calculate the second sensing data voltage Vdata_S2 that outputs the same sensing data as the reference data. In this case, since it can be said that the second sensing data voltage Vdata_S2 reflects the characteristics of the driving transistor DT affected by the kickback voltage and the threshold voltage of the first transistor T1, it can be said that the Using the sensing data SD and the second sensing data voltage Vdata_S2 calculated in the second sensing mode, not only the driving transistor DT characteristics, but also the kickback voltage ΔVp and the threshold voltage of the first transistor T1 are compensated. can do.

As a result, in the embodiment of the present invention, the current of the driving transistor DT that is not affected by the kickback voltage ΔVp and the threshold voltage of the first transistor T1 can be sensed as the sensing data SD in the first sensing mode. In the second sensing mode, the current of the driving transistor DT affected by the kickback voltage ΔVp and the threshold voltage of the first transistor T1 may be sensed as the sensing data SD. As a result, the embodiment of the present invention corrects the digital video data DATA with the correction data CDATA based on the sensed data SD, so that the driving transistor DT has the same threshold voltage and electron mobility as the driving transistor DT. ) as well as the kickback voltage ΔVp and the threshold voltage of the first transistor T1 may be compensated.

Those skilled in the art from the above description will be able to see that various changes and modifications can be made without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: display panel 20: data driver
21: data voltage supply unit 22: initialization voltage supply unit
23: sensing data output unit 30: scan driving unit
40: sensing driving unit 50: timing control unit
60: digital data correction unit

Claims (10)

a display panel including pixels connected to data lines, sensing lines, scan lines, and sensing signal lines;
a scan driver supplying scan signals to the scan lines;
a sensing signal driver supplying sensing signals to the sensing signal lines;
a data voltage supply unit supplying data voltages to the data lines; and
a sensing data output unit configured to sense currents flowing from the pixels to the sensing lines and output sensing data;
The pixel is
organic light emitting diode;
a driving transistor for adjusting an amount of current flowing through the organic light emitting diode according to a voltage difference between a gate voltage and a source voltage;
a first transistor turned on by the scan signal of the scan line to supply the data voltage of the data line to the gate electrode of the driving transistor; and
a second transistor turned on by a sensing signal of the sensing signal line to connect a source electrode of the driving transistor to the sensing line;
During the first and second periods of the first sensing mode, the scan signal of the gate-on voltage is supplied to the scan line and the sensing signal of the gate-on voltage is supplied to the sensing line, and during the third period of the first sensing mode A scan signal of a gate-off voltage is supplied to the scan line and a sensing signal of a gate-off voltage is supplied to the sensing line,
The sensing data output unit converts the current of the driving transistor flowing through the sensing line into a voltage while the first and second transistors are turned on during the second period of the first sensing mode, and converts it during the third period An organic light emitting display device that outputs the sensed voltage as the sensed data. delete The method of claim 1,
The sensing data output unit senses the current of the driving transistor flowing through the sensing line in a state in which the first transistor is turned off and the second transistor is turned on in a second sensing mode to output sensed data; display device. 4. The method of claim 3,
During the first period of the second sensing mode, the scan signal of the gate-on voltage is supplied to the scan line and the sensing signal of the gate-on voltage is supplied to the sensing line, and during the second period of the second sensing mode, the A scan signal of a gate-off voltage is supplied to the scan line and a sensing signal of the gate-on voltage is supplied to the sensing line, and a scan signal of the gate-off voltage is supplied to the scan line during a third period of the second sensing mode. is supplied and the sensing signal of the gate-off voltage is supplied to the sensing line,
The sensing data output unit converts the current of the driving transistor into a voltage during a second period of the second sensing mode. The method of claim 1,
and a current of the driving transistor flows to the organic light emitting diode in a display mode. 6. The method of claim 5,
During the first period of the display mode, the scan signal of the gate-off voltage is supplied to the scan line, and the sensing signal of the gate-on voltage is supplied to the sensing line, and the gate-on voltage is lowered during the second period of the display mode. A scan signal is supplied to the scan line and a sensing signal of the gate-on voltage is supplied to the sensing line, and a scan signal of the gate-off voltage is supplied to the scan line and the gate-off voltage is supplied to the scan line during a third period of the display mode of the sensing signal is supplied to the sensing line. The method of claim 1,
The sensing data output unit includes a plurality of sensing units connected to sensing lines,
The sensing unit,
a current-voltage converter for converting a current flowing from the pixel to the sensing line into a voltage and outputting it; and
and an analog-to-digital converter converting the voltage output from the current-voltage converter into sensing data that is digital data. 8. The method of claim 7,
The current-voltage converter,
an operational amplifier having an inverting terminal, a non-inverting terminal to which a second initialization voltage is supplied, and an output terminal connected to the analog-to-digital converter;
a feedback capacitor connected between the inverting terminal of the operational amplifier and the output terminal;
a second switch switched according to a second switch signal to connect the inverting terminal of the operational amplifier and the output terminal;
a third switch switched according to a third switch signal to connect an output terminal of the operational amplifier to the analog-to-digital converter; and
and a fourth switch switched according to a fourth switch signal to connect an inverting terminal of the operational amplifier to the sensing line. 9. The method of claim 8,
During a first period of each of the first and second sensing modes, the second and third switches are turned on, and during a second period, the second switch is turned off and the third switch is turned on. , the second and third switches are turned off during a third period,
and the fourth switch is turned on during the first to third periods. The method of claim 1,
In the display mode, the digital video data is corrected with correction data based on the sensed data and the correction data is output, the first sensing data stored in the memory is output in the first sensing mode, and the memory is stored in the memory in the second sensing mode. Further comprising a digital data correction unit for outputting the stored second sensed data,
The data voltage supply unit converts the correction data into light emitting data voltages in the display mode and supplies the data lines to the data lines, and converts the first sensed data into a first sensed data voltage in the first sensing mode to convert the data The organic light emitting display device according to claim 1, wherein the second sensing data is converted into a second sensing data voltage in the second sensing mode and supplied to the data lines.

Images