KR102327667B1 - Methods of manufacturing semiconductor devices - Google Patents

Abstract

A method of forming a pattern for a semiconductor device, wherein sacrificial layer patterns are formed on an etch target layer, spacer-shaped preliminary mask patterns are formed on both sidewalls of the sacrificial layer patterns, and gaps between the preliminary mask patterns are filled. to form a buried film. The upper surfaces of the preliminary mask patterns are partially etched back to convert the preliminary mask patterns into mask patterns, and the mask pattern extends in the first direction along a center in a second direction perpendicular to the first direction. It should have a symmetrical shape based on the line. Thereafter, the sacrificial layer patterns and the buried layer are removed, and the etch target layer is etched using the mask patterns to form patterns. Since the mask pattern has a symmetrical shape, a line width distribution of the pattern formed using the mask pattern may be reduced.

Description

Method of manufacturing a semiconductor device {METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES}

The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device including a fine pattern.

As semiconductor devices are highly integrated, it is required to form fine patterns having a width of several to tens of nm. Accordingly, various pattern forming methods have been developed.

An object of the present invention is to provide a method of manufacturing a semiconductor device including patterns having improved dispersion.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, line-shaped sacrificial layer patterns extending in a first direction are formed on an etch target layer, and both sidewalls of the sacrificial layer patterns are formed. Spacer-shaped preliminary mask patterns are formed thereon, a filling layer is formed to fill gaps between the preliminary mask patterns, and upper surfaces of the preliminary mask patterns are partially etched back to form the preliminary mask patterns as mask patterns. , and the mask pattern has a symmetrical shape with respect to a line extending in the first direction along a center of a second direction perpendicular to the first direction, and the sacrificial layer patterns and the buried layer are removed, , and the etch target layer is etched using the mask patterns to form patterns.

In example embodiments, the method may further include forming an upper mask pattern on each of the sacrificial layer patterns.

In example embodiments, in the process of etch-backing a portion of upper surfaces of the preliminary mask patterns, all of the upper mask patterns may be removed.

In example embodiments, the sacrificial layer patterns and the buried layer may be formed of the same material.

In example embodiments, the sacrificial layer patterns and the buried layer may be formed of a carbon-containing layer or a polysilicon layer.

In example embodiments, forming the preliminary mask patterns may include conformally forming a mask layer on the sacrificial layer patterns and the etch target layer, and anisotropically etching the mask layer.

In example embodiments, the sacrificial layer patterns have a width equal to a first distance that is a target separation distance of the patterns, and a separation distance between the first sacrificial layer patterns is equal to a first line width that is a target line width of the patterns. It may be formed to be equal to the sum of 2 times and the first distance.

In example embodiments, the preliminary mask patterns may be formed to have the first width.

In example embodiments, the sacrificial layer patterns have a width wider than a first distance that is a target separation distance of the patterns, and the separation distance of the photoresist patterns is about twice a first line width that is a target line width of the patterns and It may be formed to have a smaller distance than the sum of the first distances.

In example embodiments, the preliminary mask patterns may be formed to have a width smaller than the first width.

In example embodiments, a separation distance between the preliminary mask patterns may be greater than the first distance.

In example embodiments, after removing the sacrificial layer patterns and the buried layer, additional mask patterns may be formed on both sidewalls of the mask pattern.

In example embodiments, the additional mask pattern may be formed such that a width of the mask structure including the mask pattern and the additional mask pattern formed on both sidewalls of the mask pattern is the same as the first width.

In example embodiments, forming the additional mask pattern may include conformally forming an additional mask layer on the mask pattern and the etch target layer, and anisotropically etching the additional mask layer.

In example embodiments, the additional mask layer may be formed by an atomic layer lamination method.

In example embodiments, the method may further include forming a lower mask layer on the etch target layer.

In a method for manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, line-shaped sacrificial layer patterns extending in a first direction are formed on an etch target layer, and the sacrificial layer patterns and etching are performed. A mask layer is conformally formed on the target layer, a buried layer is formed to fill a gap between the mask layers, and an upper surface of the mask layer is etched back to expose an upper surface of the sacrificial layer pattern, a first line; Mask patterns including a second line and a connection portion connecting the lower portions of the first and second lines are formed, the sacrificial layer patterns and the buried layer are removed, and the connection portion of the mask pattern is anisotropically etched, and the lower portion thereof patterns are formed by etching the etch target layer of

In example embodiments, the method may further include forming an upper mask pattern on each of the sacrificial layer patterns.

In example embodiments, in the process of etch-backing the upper surface of the mask layer, all of the upper mask pattern may be removed.

In example embodiments, the method may further include forming a lower mask layer on the etch target layer.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, a first sacrificial layer and a first mask layer are formed on an etch target layer, and a first sacrificial layer and a first mask layer are formed on the first mask layer in a first direction. Forming extended second sacrificial layer patterns, forming spacer-shaped second preliminary masks on both sidewalls of the second sacrificial layer patterns, and first filling the gaps between the second preliminary mask patterns A layer is formed, upper surfaces of the second preliminary mask patterns are partially etched back to form the second masks, the second sacrificial layer patterns and the first buried layer are removed, and the second mask patterns are used to form the second masks. The first mask layer is etched to form first masks, and a third sacrificial layer is formed to fill a gap between the first masks, and the third sacrificial layer is perpendicular to the first direction on the first masks and the third sacrificial layer. forming second masks extending in a second direction, forming a sacrificial mask pattern including holes by etching the first and third sacrificial layers between the first and second masks, and forming the sacrificial mask pattern The etch target layer is etched using the etchant to form a pattern including holes.

In example embodiments, the method may further include forming a lower mask layer on the etch target layer.

In example embodiments, the forming of the second mask pattern includes forming a second mask layer on the first masks and the third sacrificial layer, and extending on the second mask layer in the second direction. forming a fourth sacrificial layer pattern to be used, forming second preliminary mask patterns on both sides of the fourth sacrificial layer pattern, and forming a second buried layer to fill a gap between the second preliminary mask patterns; partially etch-back the upper surfaces of the second preliminary mask patterns, convert the second preliminary mask patterns into second mask patterns, and remove the fourth sacrificial layer patterns and the second buried layer can

In example embodiments, the method may further include forming an upper mask pattern on each of the second sacrificial layer patterns.

In example embodiments, in the etch-back process of the upper surfaces of the second preliminary mask patterns, all of the upper mask patterns may be removed.

According to the present invention, the mask patterns provided as an etch mask for forming the patterns may have a symmetrical shape with respect to a line extending in the first direction along the center of the second direction. Also, a height difference between the upper surfaces of the lower layers exposed between the mask patterns is reduced. Accordingly, each of the patterns formed by etching the lower layers using the mask patterns has a very uniform critical dimension and a very small distribution of the critical dimension. Therefore, it is possible to manufacture a semiconductor device having a high degree of integration including the patterns.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
9 to 16 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
17 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.
21 to 27 are perspective views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.
28 to 36 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In each drawing of the present invention, the dimensions of the structures are enlarged than the actual size for clarity of the present invention.

In the present invention, terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

The terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

In the present invention, each layer (film), region, electrode, pattern or structure is formed “on”, “on” or “under” the object, substrate, each layer (film), region, electrode or pattern. Each layer (film), region, electrode, pattern or structures, when referred to as being, is meant to be formed directly over or beneath the substrate, each layer (film), region, or patterns, or to another layer (film). , other regions, other electrodes, other patterns, or other structures may be additionally formed on the object or substrate.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions are only exemplified for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be embodied in various forms. It should not be construed as being limited to the embodiments described in

That is, since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

1 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , an etch target layer 102 is formed on a substrate 100 . A lower mask layer 104 , a sacrificial layer 106 , and an upper mask layer 108 are formed on the etch target layer 102 . A photo process is performed on the upper mask layer 108 to form photoresist patterns 110 .

In an exemplary embodiment, the target to be etched may be the substrate 100 , and in this case, the target layer 102 may not be formed.

The substrate 100 is, for example, a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI). A semiconductor substrate such as a substrate or the like can be used.

The etch target layer 102 may refer to a layer that is converted into a pattern through a photolithography process. In example embodiments, the etch target layer 102 may be formed to include an insulating material such as silicon oxide. In example embodiments, the etch target layer 102 may include a conductive material such as a metal, a metal nitride, a metal silicide, or a metal silicide nitride layer. In example embodiments, the etch target layer 102 may be formed to include a semiconductor material such as polysilicon.

The etch target layer 102 may be formed by, for example, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition) process. : LPCVD process, High Density Plasma Chemical Vapor Deposition (HDP-CVD) process, spin coating process, sputtering process, Atomic Layer Deposition (ALD) process, It may be formed through at least one of physical vapor deposition (PVD) processes.

The lower mask layer 104 may be formed of a material suitable for etching the target layer 102 . That is, the lower mask layer 104 may be formed of a material having an etch selectivity to the etch target layer. Therefore, the lower mask layer 104 may be formed of a different material depending on the etch target layer 102 .

For example, the lower mask layer 104 may include silicon nitride or silicon oxynitride. In this case, the lower mask layer 104 may also be used as an anti-reflection layer. As another example, the lower mask layer 104 may include silicon oxide. In example embodiments, the lower mask layer 104 may not be formed.

The sacrificial layer 106 is provided as a mold layer for forming a mask pattern used for etching, and may be removed in a subsequent process. Accordingly, the sacrificial layer 106 may be formed of a material having an etch selectivity to the material provided as the mask pattern. Also, the sacrificial layer 106 may be formed of a material that can be selectively and easily removed.

In example embodiments, the sacrificial layer 106 may include an amorphous carbon layer (ACL) or a carbon-containing layer. Specifically, an organic compound layer including a hydrocarbon compound including an aromatic ring such as phenyl, benzene, or naphthalene or a derivative thereof is formed through a spin coating process. Thereafter, a bake process may be performed to form the sacrificial layer. The ACL or carbon-containing film is generally referred to as a spin on carbon hard mask (SOH) film.

As another example, the sacrificial layer 106 may be formed of a polysilicon layer. The polysilicon layer may be formed through, for example, a chemical vapor deposition process.

The upper mask layer 108 may be formed of a material suitable for etching the sacrificial layer 106 . That is, the upper mask layer 108 may be formed of a material having an etch selectivity to the sacrificial layer. For example, the upper mask layer 108 may include silicon nitride or silicon oxynitride. In this case, the upper mask layer 108 may also be used as an anti-reflection layer.

The photoresist patterns 110 may be formed to have a line shape extending in the first direction. The photoresist patterns 110 may be formed to have the same line width as the first distance D1 that is the target separation distance of the final patterns. In addition, the separation distance of the photoresist patterns 110 may be formed to be the same as the second distance D2 equal to the sum of the first distance D1 and about twice the first width, which is the target line width of the final pattern. have. For example, when the first distance D1 and the first width are the same, the second distance D2 may be formed to be about three times the first width.

In order to form the photoresist patterns 110 , a photoresist is coated and cured to form a photoresist film. The photoresist patterns 110 may be formed by performing exposure and development processes on the photoresist layer. The light source used in the exposure process is not particularly limited, but may include, for example, ArF, KrF, electron beam, I-line, extreme ultraviolet (EUV) light source, and the like.

Referring to FIG. 2 , the upper mask layer is anisotropically etched using the photoresist patterns 110 as an etching mask to form upper mask patterns 108a. By performing the above process, most of the photoresist patterns 110 may be removed. The sacrificial layer 106 is anisotropically etched using the upper mask patterns 108a as an etch mask to form sacrificial layer patterns 106a, respectively. The upper mask pattern 108a may remain on each of the sacrificial layer patterns 106a.

The sacrificial layer patterns 106a may be formed to have a line shape extending in the first direction. A line width of the sacrificial layer patterns 106a may be the same as the first distance D1 , and a separation distance between the sacrificial layer patterns 106a may have the second distance D2 .

Referring to FIG. 3 , a mask layer 112 is conformally formed along the surfaces of the sacrificial layer patterns 106a , the upper mask patterns 108a , and the lower mask layer 104 . Even if the mask layer 112 is formed to have a uniform thickness, the mask layer 112 may have a curvature at a corner portion of the upper surface of the upper mask pattern 108a. For example, the radius of curvature of the mask layer 112 at the edge of the upper surface of the upper mask pattern 108a may be the thickness of the mask layer.

The mask layer 112 may be formed through an atomic layer deposition process or a chemical vapor deposition process. In order to form an ultra-fine pattern of several to several tens of nm, the mask layer 112 is preferably formed through an atomic layer deposition process.

In example embodiments, the mask layer 112 may be provided as a mask pattern for etching the lower mask layer 104 through a subsequent process. Accordingly, the mask layer 112 may be formed of a material having an etch selectivity to the lower mask layer 104 .

In example embodiments, when the lower mask layer 104 is not formed, the mask layer 112 may serve as a mask pattern for etching the etch target layer 102 . In this case, the mask layer 112 may be formed of a material having an etch selectivity to the etch target layer 102 .

In an exemplary embodiment, the mask layer 112 may include silicon oxide. Since the silicon oxide can be formed very uniformly with a thin thickness of several to several tens of nm through the atomic layer deposition process, it may be suitable for use as the mask layer 112 .

The mask layer 112 may be formed to have the same thickness as the first width W1 . Accordingly, the mask layer 112 formed on the sidewalls of the sacrificial layer patterns 106a may have the first width W1 . In addition, a gap portion between the mask layers 112 formed on sidewalls of the sacrificial layer patterns 106a may have the first distance D1 .

Referring to FIG. 4 , the mask layer 112 is anisotropically etched to expose the lower mask layer 104 to form a spacer-shaped preliminary mask pattern 112a on sidewalls of the sacrificial layer patterns 106a. do.

Since the mask 112 layer formed at the edge of the upper surface of the upper mask pattern 108a has a curvature, the adjacent preliminary mask patterns may not have the same shape.

The preliminary mask pattern 112a has an asymmetric shape with respect to the line L1 extending in the first direction along the center of the second direction perpendicular to the first direction. That is, the upper surface of the preliminary mask pattern 112a on the side that is in contact with the sidewalls of the sacrificial film patterns 106a has a relatively high height, and the upper surface of the preliminary mask pattern 112a increases as it moves away from the sidewalls of the sacrificial film patterns 106a. height can be lowered.

Even after the preliminary mask pattern 112a is formed, the upper mask patterns 108a may remain on each of the sacrificial layer patterns 106a.

Referring to FIG. 5 , a buried layer (not shown) is formed to fill a gap between the preliminary mask patterns 112a.

In an exemplary embodiment, the buried layer may be formed using the same material as the sacrificial layer pattern 106a. For example, the buried layer may include an amorphous carbon layer (ACL) or a carbon-containing layer. In this case, the buried layer may be formed through a spin coating process. As another example, the buried layer may be formed of a polysilicon layer. In this case, the buried layer may be formed through a chemical vapor deposition process.

The buried layer is etched back to expose the upper mask pattern 108a to form a buried layer pattern 114 in a gap between the preliminary mask patterns 112a.

Referring to FIG. 6 , the upper mask pattern 108a is etched back so that the upper mask pattern 108a is completely removed. In addition, an upper portion of the preliminary mask pattern 112a is etched back to form a mask pattern 112b. The mask patterns 112b may have substantially the same shape. In the etch-back process, the sacrificial layer pattern 106a and the buried layer pattern 114 may also be etched to a partial thickness.

The mask pattern 112b may have a symmetrical shape with respect to the line L1 extending in the first direction along the center of the second direction. In an exemplary embodiment, the top surface of the mask pattern 112b may have substantially the same height.

As another example, although not shown, the mask pattern 112b may have a shape in which the height of the upper surface of the central portion in the second direction is high and the height of the upper surface decreases toward both sidewalls of the mask pattern 112b.

If the mask pattern has an asymmetric shape with respect to a line extending in the first direction along the center of the second direction, patterns formed using the mask pattern as an etching mask may have non-uniform sidewall surfaces. Therefore, a large deviation in line width may occur. However, in an embodiment of the present invention, since the mask pattern 112b has a symmetrical shape with respect to a line extending in the first direction along the center of the second direction, the mask pattern 112b is Variation in line widths of patterns formed by using them can be reduced.

Also, when the upper mask pattern 108a is removed through the etch-back process, the lower mask layer 104 is formed by the sacrificial layer pattern 106a, the buried layer pattern 114, and the preliminary mask pattern 112a. all covered Accordingly, the surface of the lower mask layer 104 may not be damaged or etched while the upper mask pattern 108a is removed.

If the surface of the lower mask layer is partially damaged or etched, a height difference between the damaged portion and the upper surface of the remaining portion of the lower mask layer is generated. Accordingly, a height difference and a line width deviation may occur in final patterns formed through a subsequent etching process. However, in an embodiment of the present invention, since the surface of the lower mask layer 104 is not damaged in the etch-back process, a height difference and a line width deviation of the final patterns may be reduced.

Referring to FIG. 7 , the sacrificial layer pattern 106a and the buried layer pattern 114 are removed. Accordingly, mask patterns 112b having the first width W1 may be formed on the lower mask layer 104 . Also, the mask patterns 112b may be spaced apart from each other by the first distance D1.

In an exemplary embodiment, when the sacrificial layer pattern 106a and the buried layer pattern 114 include an ACL or a carbon-containing layer, the sacrificial layer pattern 106a and the buried layer pattern 114 are formed through a plasma ashing process. can be removed

In an exemplary embodiment, when the sacrificial layer pattern 106a and the buried layer pattern 114 include polysilicon, the polysilicon may be removed through an isotropic etching process.

Referring to FIG. 8 , the lower mask layer 104 is anisotropically etched using the mask patterns 112b as an etch mask to form lower mask patterns 104a.

Thereafter, the target layer 102 is anisotropically etched using the mask patterns 112b and the lower mask patterns 104a as etch masks to form target patterns 102a. Some or all of the mask patterns 112b may be removed during the anisotropic etching process.

The target patterns 102a may have the first width W1 and may be spaced apart by the first distance D1.

As described above, the mask patterns 112b may have a symmetrical shape with respect to a line extending in the first direction along the center of the second direction. Therefore, the target patterns 102a formed using the mask patterns 112b as an etch mask may have a uniform line width. In addition, when the etch-back process of removing the upper mask pattern 108a is performed, partial damage to the surface of the lower mask layer 104 may not occur. Accordingly, a height difference and line width distribution between the target patterns 102a may be reduced.

9 to 16 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 9 , an etch target layer 102 is formed on the substrate 100 . A lower mask layer 104 , a sacrificial layer, and an upper mask layer are formed on the etch target layer 102 . The etch target layer 102 , the lower mask layer 104 , the sacrificial layer, and the upper mask layer may be formed in substantially the same manner as described with reference to FIG. 1 .

A photo process is performed on the lower mask layer 104 to form photoresist patterns (not shown). The photoresist patterns may be formed to have a line shape extending in the first direction. The photoresist patterns may be formed to have a second width W2. The second width W2 may be wider than the first distance, which is the separation distance of the target pattern to be formed.

The first pitch P1, which is the distance from the first sidewall of the one photoresist pattern to the first sidewall of the photoresist pattern adjacent to the photoresist pattern, is approximately twice the first distance and the target of the final pattern It may be formed to be equal to the sum of about twice the first width W1, which is the line width. In an exemplary embodiment, the separation distance of the photoresist patterns may have a third distance D3 smaller than a sum of about twice the first width and the first distance.

An upper mask pattern 132 is formed by anisotropically etching the upper mask layer using the photoresist pattern as an etching mask. By performing the above process, most of the photoresist patterns may be removed. The sacrificial layer is anisotropically etched using the upper mask pattern 132 as an etching mask to form sacrificial layer patterns 130 , respectively. The upper mask pattern 132 may remain on each of the sacrificial layer patterns 130 .

The sacrificial layer patterns 130 may be formed to have a line shape extending in the first direction. The sacrificial layer patterns 130 may have the second width W2 , and an interval between the sacrificial layer patterns 130 may have the third distance D3 . Also, the first pitch P1 between the sacrificial layer patterns 130 may be equal to the sum of about twice the first distance and about twice the first width.

As such, since the sacrificial layer patterns 130 have a second width W2 that is wider than the first width, the aspect ratio is reduced compared to the case where the sacrificial layer patterns 130 have the first width. Accordingly, problems in which the sacrificial layer patterns 130 are collapsed or tilted may be reduced. In addition, the limit height of the sacrificial layer patterns 130 may be increased.

Referring to FIG. 10 , a mask layer 134 is conformally formed along the surfaces of the sacrificial layer pattern 130 , the upper mask pattern 132 , and the lower mask layer 104 .

In example embodiments, the mask layer 134 may be provided as a mask pattern for etching the lower mask layer 104 through a subsequent process. Accordingly, the mask layer 134 may be formed of a material having an etch selectivity to the lower mask layer 104 . In an exemplary embodiment, the mask layer 134 may be formed of silicon oxide by an atomic layer deposition method.

The mask layer 134 may be formed to have a thickness smaller than the first width. Accordingly, the mask layer 134 formed on the sidewalls of the sacrificial layer patterns 130 may have a fourth width W4 that is narrower than the first width W1 . In addition, a gap portion between the masks 134 formed on the sidewalls of the sacrificial layer patterns 130 may be formed to have the same distance as the second width W2 .

Referring to FIG. 11 , the mask layer 134 is anisotropically etched to expose the lower mask layer 104 to form a spacer-shaped first preliminary mask pattern 134a on the sidewall of the sacrificial layer pattern 130 . to form The first preliminary mask pattern 134a may have the fourth width W4 .

Since the mask layer 134 has a thickness smaller than the first width, the mask layer 134 may be easily etched. In addition, when the etching process is performed, damage to the lower mask layer 104 may be reduced.

The first preliminary mask pattern 134a may have an asymmetric shape with respect to a line extending in the first direction along a center of the second direction perpendicular to the first direction. Even after the first preliminary mask pattern 134a is formed, the upper mask pattern 132 may remain on each of the sacrificial layer patterns 130 .

Referring to FIG. 12 , a filling layer (not shown) is formed to fill a gap between the first preliminary mask patterns 134a.

The buried layer may be formed using the same material as the sacrificial layer pattern 130 . For example, the buried layer may include an ACL or a carbon-containing layer. In this case, the buried layer may be formed through a spin coating process.

As another example, the buried layer may be formed of a polysilicon layer. In this case, the buried layer may be formed through a chemical vapor deposition process.

The buried layer is etched back to expose the upper mask pattern 132 to form a buried layer pattern 136 in a gap between the first preliminary mask patterns 134a.

Referring to FIG. 13 , the upper mask pattern 132 is etched back so that the upper mask pattern 132 is completely removed. In addition, an upper portion of the first preliminary mask pattern 134a is etched back to form a second preliminary mask pattern 134b. In the etch-back process, the sacrificial layer pattern 130 and the buried layer pattern 136 may also be etched to a partial thickness.

The second preliminary mask pattern 134b may have a symmetrical shape with respect to a line extending in the first direction along the center of the second direction. The second preliminary mask patterns 134b may have substantially the same shape.

In addition, when the upper mask pattern 132 is removed through the etch-back process, the lower mask layer 104 is formed with the sacrificial layer pattern 130 , the buried layer pattern 136 , and the first preliminary mask pattern 134a. all covered by Accordingly, while the upper mask pattern 132 is removed, the surface of the lower mask layer 104 may not be damaged or etched at all.

Referring to FIG. 14 , the sacrificial layer patterns 130 and the buried layer pattern 136 are removed. Accordingly, second preliminary mask patterns 134b having the fourth width W4 may be formed on the lower mask layer 104 . A distance between the second preliminary mask patterns 134b may be equal to the second width W2 .

In an exemplary embodiment, when the sacrificial layer patterns 130 and the buried layer pattern 136 include an ACL or a carbon-containing layer, the sacrificial layer pattern 130 and the buried layer pattern 136 are performed through a plasma ashing process. can be removed.

In an exemplary embodiment, when the sacrificial layer pattern 130 and the buried layer pattern 136 include polysilicon, the polysilicon may be removed through an isotropic etching process.

Referring to FIG. 15 , an additional mask layer 138 is conformally formed on the surfaces of the second preliminary mask patterns 134b and the lower mask layer 104 .

The additional mask layer 138 may be formed so that the line width of the mask pattern has a target first width W1 . That is, the structure including the second preliminary mask pattern 134b and the additional mask layer 138 formed on both sidewalls of the second preliminary mask pattern 134b has the first width W1 in the second direction. can

The additional mask layer 138 may be formed of silicon oxide. The additional mask layer 138 may be formed through an atomic layer deposition process.

Referring to FIG. 16 , the additional mask layer 138 between the second preliminary mask patterns 134b is anisotropically etched. Accordingly, mask patterns 139 including the second preliminary mask patterns 134b and the additional mask 138a are formed.

Thereafter, the lower mask layer is etched using the mask patterns 139 as etch masks to form lower mask patterns 104a.

The target pattern 102a is formed by anisotropically etching the target layer 102 using the mask patterns 139 and the lower mask patterns 104a as etch masks. Some or all of the mask patterns 139 may be removed during the anisotropic etching process. The target patterns 102a may have a first width W1 and may be spaced apart from each other by the first distance D1 .

As described above, by using the mask patterns 139 , target patterns 102a in which a height difference and a line width distribution are reduced may be formed.

17 to 20 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, the structure shown in FIG. 3 is formed by performing the same process as described with reference to FIGS. 1 to 3 .

Referring to FIG. 17 , a buried layer is formed on the mask layer to fill a gap between the mask layers formed on sidewalls of the sacrificial layer patterns 106a.

In an exemplary embodiment, the buried layer may be formed using the same material as the sacrificial layer pattern 106a. For example, the buried layer may include an amorphous carbon layer (ACL) or a carbon-containing layer. In this case, the buried layer may be formed through a spin coating process. As another example, the buried layer may be formed of a polysilicon layer. In this case, the buried layer may be formed through a chemical vapor deposition process.

The buried layer is etched back to expose the top surface of the mask layer to form a buried layer pattern 150 in a gap between the mask layers formed on sidewalls of the sacrificial layer patterns 106a.

Referring to FIG. 18 , upper surfaces of the mask layer 112 , the buried layer pattern 150 , and the upper mask pattern 108a are planarized so that the top surfaces of the sacrificial layer patterns 106a are exposed. The planarization process may include an etch-back process and/or a chemical mechanical polishing process.

Accordingly, the mask layer 112 is a preliminary mask pattern 140 including the first and second lines 140a and 140b and the connecting portion 140c connecting the lower portions of the first and second lines 140a and 140b. ) can be formed. That is, the preliminary mask pattern 140 may have a shape that is extended while having a cup shape in cross section. Through the above process, the upper mask pattern 108a may be completely removed.

Since the lower mask layer 104 is not exposed when the upper mask pattern 108a is removed, the lower mask layer 104 may not be damaged in the removal process. Also, the preliminary mask pattern 140 may have a substantially flat top surface. The preliminary mask patterns 140 may have substantially the same shape.

Referring to FIG. 19 , the sacrificial layer patterns 106a and the buried layer pattern 150 are removed.

In an exemplary embodiment, when the sacrificial layer pattern 106a and the buried layer pattern 150 include an ACL or a carbon-containing layer, the sacrificial layer pattern 106a and the buried layer pattern 150 are formed through a plasma ashing process. can be removed

In an exemplary embodiment, when the sacrificial layer pattern 106a and the buried layer pattern 150 include polysilicon, the polysilicon may be removed through an isotropic etching process.

Referring to FIG. 20 , the preliminary mask pattern 140 is anisotropically etched to remove the connection portion of the preliminary mask pattern 140 . Accordingly, the mask pattern 142 having a line shape is formed.

The lower mask layer is etched using the mask patterns 142 as an etch mask to form lower mask patterns 104a.

The target layer 102 is anisotropically etched using the mask patterns 142 and the lower mask patterns 104a as etch masks to form a target pattern 102a. Some or all of the mask patterns 142 may be removed during the anisotropic etching process.

21 to 27 are perspective views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment.

A pattern including regularly arranged holes may be formed in the semiconductor device.

Referring to FIG. 21 , an etch target layer 202 is formed on the substrate 200 . On the etch target layer 202 , a first hard mask layer 204 , a first sacrificial layer 206 , a second hard mask layer 208 , a second sacrificial layer 210 , and a third hard mask layer ( 212) is formed. A photo process is performed on the third hard mask layer 212 to form first photoresist patterns 214 .

In an exemplary embodiment, the first photoresist patterns 214 may be formed in the same manner as described with reference to FIG. 1 . As another example, the first photoresist patterns 214 may be formed in the same manner as described with reference to FIG. 9 .

Referring to FIG. 22 , a first mask pattern 216 is formed on the second hard mask layer 208 .

In example embodiments, the first mask pattern 216 may be formed by performing the same processes described with reference to FIGS. 2 to 7 .

Specifically, the third hard mask layer 212 is anisotropically etched using the first photoresist patterns 214 as etch masks to form a third hard mask. The second sacrificial layer 210 is anisotropically etched using the third hard mask as an etch mask to form second sacrificial layer patterns, respectively. A mask layer is conformally formed along the surfaces of the second sacrificial layer patterns, the third hard mask, and the second hard mask layer 208 and anisotropically etched to form a preliminary first mask pattern (not shown). .

A first filling layer pattern (not shown) is formed between the preliminary first mask patterns. Through an etch-back process, the third hard mask is removed, and an upper portion of the first preliminary mask pattern is etched back to form a first mask pattern 216 . Thereafter, the first buried layer pattern and the second sacrificial layer pattern between the first mask patterns 216 are removed.

In example embodiments, the first mask pattern 216 may be formed by the same method as described with reference to FIGS. 9 to 15 or the same method as described with reference to FIGS. 17 to 19 .

Referring to FIG. 23 , the second hard mask layer 208 is etched using the first mask pattern 216 to form a second hard mask 208a. In this case, the first sacrificial layer 206 between the second hard mask 208a may also be partially over-etched. Accordingly, the first preliminary sacrificial layer pattern 206a including the first trench 217 extending in the first direction is formed.

The second hard masks 208a may have the first width and may be formed to be spaced apart from each other by the first distance. Also, the second hard masks 208a may have a shape extending in the first direction.

Referring to FIG. 24 , a third sacrificial layer is formed to completely fill the inside of the first trench 217 . A third sacrificial layer pattern 218 is formed in the first trench 217 by etching back the first mask pattern 216 and the third sacrificial layer so that the second hard masks 208a are exposed.

The first preliminary sacrificial layer pattern 206a and the third sacrificial layer pattern 218 may be provided as one lower sacrificial layer pattern 219 . A second hard mask 208a extending in the first direction may be formed on the lower sacrificial layer pattern 219 . In addition, the lower sacrificial layer pattern 219 and the second hard mask 208a may have flat top surfaces.

A fourth hard mask layer 220 , a fourth sacrificial layer 222 , and a fifth hard mask layer 224 are formed on the lower sacrificial layer pattern 219 and the second hard mask 208a . In addition, a second photoresist pattern 226 is formed on the fifth hard mask layer 224 .

The second photoresist patterns 226 may be formed to have a line shape extending in a second direction perpendicular to the first direction.

Referring to FIG. 25 , a second mask pattern is formed on the fourth hard mask layer. The fourth hard mask layer is etched using the second mask pattern to form a fourth hard mask on the second hard mask 208a and the lower sacrificial layer pattern 219 .

Specifically, the fifth hard mask layer 224 is anisotropically etched using the second photoresist patterns 226 as etch masks to form fifth hard masks (not shown). The fourth sacrificial layer 222 is anisotropically etched using the fifth hard mask as an etch mask to form fourth sacrificial layer patterns (not shown), respectively. A mask layer is conformally formed along the surfaces of the fourth sacrificial layer patterns, the fifth hard mask, and the fourth hard mask layer 220 , and anisotropically etched to form a second preliminary mask pattern (not shown). .

A second buried layer pattern (not shown) is formed between the second preliminary mask patterns. Through an etch-back process, the fifth hard mask is removed, and an upper portion of the second preliminary mask pattern is etched back to form a second mask pattern 228 . Thereafter, the second buried layer pattern and the fourth sacrificial layer pattern between the second mask patterns 228 are removed.

As such, the second mask pattern 228 may be formed by performing the same processes described with reference to FIGS. 2 to 7 .

Alternatively, the second mask pattern may be formed in the same manner as described with reference to FIGS. 9 to 15 or 17 to 19 .

Thereafter, the fourth hard mask layer 220 is etched using the second mask pattern 228 as an etch mask to form a fourth hard mask 220a.

The fourth hard mask 220a may have a line shape extending in a direction perpendicular to the second hard mask 208a.

Referring to FIG. 26 , the lower sacrificial layer pattern 219 exposed between the second and fourth hard masks 208a and 220a is etched to form holes.

Subsequently, the first hard mask layer 204 under the lower sacrificial layer pattern 219 is etched to form a first hard mask 204a. Holes are regularly formed in the first hard mask 204a. During the etching processes, some or all of the layers formed on the first hard mask 204a may be removed. Although not shown, the method may further include a process of removing layers on the first hard mask 204a.

Referring to FIG. 27 , the target layer 202 is anisotropically etched using the first hard mask 204a as an etch mask to form a pattern 202a including holes 230 .

By performing the above processes, it is possible to form a pattern including regularly arranged holes and in which the size distribution of the holes is reduced.

28 to 36 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Specifically, FIGS. 29 and 32 are plan views illustrating a method of manufacturing the semiconductor device, and FIGS. 28, 30, 31, and 32 to 36 are cross-sectional views illustrating a method of manufacturing the semiconductor device. Each of the cross-sectional views is a section taken along II' and II-II' in FIGS. 29 and 21 .

28 and 29 , the device isolation layer 302 is formed on the substrate 300 to form active patterns 305 .

In example embodiments, the device isolation layer 302 and the active pattern 305 may be formed through a shallow trench isolation (STI) process. For example, the device isolation trench may be formed by removing the upper portion of the substrate 300 through an anisotropic etching process. Thereafter, for example, an insulating layer including silicon oxide may be formed on the substrate 300 while filling the device isolation trench. Then, the isolation layer 302 may be formed by planarizing the insulating layer through, for example, a CMP process until the top surface of the active pattern 305 is exposed.

As the device isolation layer 302 is formed, a plurality of active patterns 305 defined by the device isolation layer 302 may be formed. As shown in FIG. 29 , each active pattern 305 may extend in an oblique direction inclined at a predetermined angle to the first direction.

A first hard mask 317 extending in the first direction is formed on the isolation layer 302 and the active patterns 305 .

The first hard mask 317 may be formed, for example, by performing substantially the same process as that of forming the lower mask with reference to FIGS. 1 to 8 . As another example, the first hard mask 317 may be formed by performing substantially the same process as that of forming the lower mask with reference to FIGS. 9 to 16 or 17 to 20 .

The device isolation layer 302 and the active patterns 305 may be etched using the first hard mask 317 to form a gate trench 309 extending in the first direction. In the gate trench 309 , dispersion of an inner width may be reduced.

Referring to FIG. 30 , a gate structure 328 extending while filling the gate trench 309 may be formed. Since dispersion of the inner width of the gate trench 309 is reduced, the gate structures 328 may have a uniform line width.

According to example embodiments, a thermal oxidation process is performed on the surface of the active pattern 305 exposed by the gate trench 309 , or a CVD process is performed on the surface of the active pattern 305 , for example. A gate insulating layer may be formed by depositing silicon oxide or metal oxide through the ?

A gate conductive layer may be formed on the gate insulating layer to fill the remaining portion of the gate trench 309 . Thereafter, the gate conductive layer is planarized through a CMP process until the top surface of the active pattern 305 is exposed, and the gate insulating layer and a portion of the gate conductive layer formed inside the gate trench 309 are removed through an etch-back process. can do. Accordingly, the gate insulating layer pattern 322 and the gate electrode 324 filling the lower portion of the gate trench 309 may be formed.

After forming a mask layer filling the remaining portion of the gate trench 309 on the gate insulating layer pattern 322 and the gate electrode 324 , an upper portion of the mask layer is planarized until the top surface of the active pattern 305 is exposed. Thus, a gate mask 326 may be formed.

Accordingly, a gate structure 328 including a gate insulating layer pattern 322 , a gate electrode 324 , and a gate mask 326 sequentially stacked in the gate trench 309 may be formed.

Impurity regions ( FIGS. 29 , 301 , and 303 ) may be formed by performing an ion implantation process on the active pattern 305 adjacent to the gate structures 328 .

An etch stop layer 330 is formed to cover the active pattern 305 , the device isolation layer 302 , and the gate structure 328 , and a first interlayer insulating layer 332 is formed on the etch stop layer 330 . A first conductive layer 334 is formed on the first interlayer insulating layer 332 .

The first conductive layer 334 , the first interlayer insulating layer 332 , and the etch stop layer 330 are partially etched to expose a portion of the active pattern 305 between the gate structures 328 . Holes 336 may be formed.

Referring to FIG. 31 , a second conductive layer 338 is formed on the first conductive layer 334 while filling the first holes 336 . The second conductive layer 338 may be formed of substantially the same material as the first conductive layer 334 . For example, the first and second conductive layers 334 and 338 may be formed using doped polysilicon.

Thereafter, a planarization process may be performed so that upper surfaces of the first and second conductive layers 334 and 338 are flat.

A third conductive layer 348 including a barrier metal layer 345 and a metal layer 347 is formed on the first and second conductive layers 334 and 338 .

A second hard mask 350 extending in a second direction perpendicular to the first direction is formed on the third conductive layer 348 .

The second hard mask 350 may be formed, for example, by performing substantially the same process as that of forming the lower mask with reference to FIGS. 1 to 8 . As another example, the second hard mask 350 may be formed by performing substantially the same process as forming the lower mask with reference to FIGS. 9 to 16 or forming the lower mask with reference to FIGS. 17 to 20 . may be

32 and 33 , the third conductive layer 348 , the second conductive layer 338 , and the first conductive layer 334 are sequentially etched using the second hard mask 350 as an etch mask. . Accordingly, the bit line structure 355 including the first conductive layer pattern 334a , the second conductive layer pattern 338a , the third conductive layer pattern 348a , and the second hard mask 350 may be formed. .

In example embodiments, the bit line structure 355 may have a smaller width than the first hole 336 . Accordingly, the sidewall of the bit line structure 355 may be spaced apart from the sidewall of the first hole 336 .

Since the bit line structure 355 is formed using the second hard mask 350 , the bit line structure 355 may have a fine line width while reducing the line width distribution.

Referring to FIG. 34 , a spacer 352 is formed on a sidewall of the bit line structure 355 .

A second interlayer insulating layer 360 covering the bit line structure 355 is formed on the first interlayer insulating layer 332 . A planarization process may be further performed so that an upper portion of the second interlayer insulating layer 360 is flat.

A portion of the second interlayer insulating layer 360 , the first interlayer insulating layer 332 , and the etch stop layer 330 may be etched to form contact holes exposing an upper portion of the active pattern 305 .

Contact plugs 375 electrically connected to the active pattern 305 may be formed while filling the inside of the contact holes. Specifically, after the conductive layer filling the contact holes is formed, an upper portion of the conductive layer may be planarized until the top surface of the second hard mask 350 is exposed.

Referring to FIG. 35 , an etch stop layer (not shown) and a mold layer are formed on the second hard mask 350 , the second interlayer insulating layer 360 , and the contact plugs 375 .

A third hard mask 381 including holes, respectively, is formed on the mold layer at a portion corresponding to the contact plug.

The third hard mask 381 may be formed by, for example, performing substantially the same process as that of forming the first hard mask with reference to FIGS. 21 to 27 .

The mold layer pattern 380 including capacitor openings 382 exposing upper surfaces of the contact plugs 375 by etching the mold layer and the etch stop layer using the third hard mask 381 as an etch mask, respectively. ) can be formed.

Referring to FIG. 36 , capacitors 390 electrically connected to the contact plugs 375 are formed. Accordingly, a dynamic random access memory (DRAM) device may be manufactured.

Specifically, a lower electrode layer may be formed along an inner wall of the capacitor opening 382 and an upper surface of the mold layer pattern 380 . After a sacrificial layer (not shown) is formed on the lower electrode layer, upper portions of the sacrificial layer and the lower electrode layer may be planarized to expose a top surface of the mold layer pattern 380 . Thereafter, the lower electrode 390a may be formed by removing the sacrificial layer and the mold layer.

A capacitor 390 may be formed by forming a dielectric layer 390b along the surfaces of the etch stop layer and the lower electrode 390a, and forming an upper electrode 390c on the dielectric layer 390b. The dielectric layer 390b may be formed using silicon oxide or a metal oxide having a high dielectric constant. The lower electrode 390a and the upper electrode 390c may be formed using a metal or a metal nitride such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, or ruthenium.

According to the above-described exemplary embodiments, it is possible to form semiconductor devices including lines or contact holes having a fine width and having patterns with reduced dispersion.

The present invention can be used in various ways to form a pattern having a fine line width in the manufacture of a semiconductor device. In particular, it can be used to form wirings or contacts of semiconductor devices that require high performance while being highly integrated.

100: substrate 102: etch target film
104: lower mask layer 106: sacrificial layer
108: upper mask layer 110: photoresist pattern
108a, 132: upper mask pattern 106a, 130: sacrificial layer pattern
112, 134: mask layer 112a: preliminary mask pattern
114, 136: buried film pattern 112b: mask pattern
104a: lower mask pattern
134a: first preliminary mask pattern 134b: second preliminary mask pattern
138: additional mask layer 138a: additional mask

Claims (20)

forming a sacrificial layer and an upper mask layer including a material having a selectivity to the sacrificial layer on the etch target layer;
patterning the sacrificial layer and the upper mask layer to form line-shaped sacrificial layer patterns extending in a first direction on the etch target layer and an upper mask pattern on each of the sacrificial layer patterns;
forming spacer-shaped preliminary mask patterns on both sidewalls of the stacked structure of the sacrificial layer pattern and the upper mask pattern;
forming a buried layer to fill a gap between the preliminary mask patterns;
A portion of upper surfaces of the preliminary mask patterns and all of the upper mask patterns are removed through an etch-back process to expose an upper surface of the sacrificial layer pattern, the preliminary mask patterns are converted into mask patterns, and the mask the pattern has a symmetrical shape with respect to a line extending in the first direction along a center of a second direction perpendicular to the first direction;
removing the sacrificial layer patterns and the buried layer; and
A method of manufacturing a semiconductor device for forming patterns by etching the etch target layer using the mask patterns. delete delete The method of claim 1 , wherein the sacrificial layer patterns and the buried layer are formed of the same material. The method of claim 4 , wherein the sacrificial layer patterns and the buried layer are formed of a carbon-containing layer or a polysilicon layer. The method of claim 1 , wherein forming the preliminary mask patterns comprises:
forming a mask layer conformally on the sacrificial layer patterns and the etch target layer; and
and anisotropically etching the mask layer. The sacrificial layer patterns of claim 1 , wherein the sacrificial layer patterns have a width equal to a first distance that is a target separation distance of the patterns, and a separation distance between the sacrificial layer patterns is twice a first line width that is a target line width of the patterns and the A method of manufacturing a semiconductor device formed to be equal to the sum of the first distances. The method of claim 7 , wherein the preliminary mask patterns are formed to have the first line width. The sacrificial layer patterns of claim 1 , wherein the sacrificial layer patterns have a width wider than a first distance that is a target separation distance of the patterns, and the spacing distance of the sacrificial layer patterns is twice a first line width that is a target line width of the patterns and the first A method of manufacturing a semiconductor device formed to have a distance smaller than the sum of the distances. The method of claim 9 , wherein the preliminary mask patterns are formed to have a width narrower than the first line width. The method of claim 10 , wherein a distance between the preliminary mask patterns is greater than the first distance. The method of claim 9 , further comprising forming additional mask patterns on both sidewalls of the mask pattern after removing the sacrificial layer patterns and the buried layer. The method of claim 12 , wherein the additional mask pattern is formed such that a line width of the mask structure including the mask pattern and additional mask patterns formed on both sidewalls of the mask pattern is the same as the first line width. The method according to claim 12, wherein forming the additional mask pattern comprises:
forming an additional mask layer conformally on the mask pattern and the etch target layer; and
and anisotropically etching the additional mask layer. The method of claim 14 , wherein the additional mask layer is formed by an atomic layer stacking method. The method of claim 1 , further comprising forming a lower mask layer on the etch target layer. forming a sacrificial layer and an upper mask layer including a material having a selectivity to the sacrificial layer on the etch target layer;
patterning the sacrificial layer and the upper mask layer to form line-shaped sacrificial layer patterns extending in a first direction on the etch target layer and an upper mask pattern on each of the sacrificial layer patterns;
conformally forming a mask layer on the layered structure of the sacrificial layer pattern and the upper mask pattern and on the etch target layer;
forming a buried layer to fill a gap between the mask layers;
The mask patterns are etched back so that a portion of the upper surface of the mask layer is removed so that the upper surface of the sacrificial layer pattern is exposed, and mask patterns including a first line, a second line, and a connection part connecting lower portions of the first and second lines forming and removing all of the upper mask pattern in the etch-back process;
removing the sacrificial layer patterns and the buried layer; and
A method of manufacturing a semiconductor device, comprising: anisotropically etching a connection portion of the mask pattern; and etching an etch target layer thereunder to form patterns. delete delete The method of claim 17 , further comprising forming a lower mask layer on the etch target layer.

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