KR102338947B1 - Substrate including thin film transistor - Google Patents

Abstract

The present invention relates to a substrate including a thin film transistor capable of preventing spot defects, wherein the substrate including the thin film transistor according to the present invention has a drain electrode overlapping a pixel buried electrode filling a pixel contact hole exposing a drain electrode A pixel auxiliary layer is disposed above or below the pixel auxiliary layer, and the top surface of the pixel auxiliary layer or the top surface of the drain electrode is located closer to the top surface of the planarization layer than the top surface of the data line.

Description

A substrate including a thin film transistor {SUBSTRATE INCLUDING THIN FILM TRANSISTOR}

The present invention relates to a substrate including a thin film transistor and a method for manufacturing the same, and more particularly, to a substrate including a thin film transistor capable of preventing stain defects.

In a liquid crystal display (LCD), an electric field is applied to a liquid crystal layer having an anisotropic dielectric constant injected between a thin film transistor (TFT) substrate and a color filter substrate, and the intensity of the electric field is adjusted to reduce the amount of light transmitted through the substrate. It is a display device that obtains a desired image signal by adjusting the amount.

Such a conventional liquid crystal display device includes an upper alignment layer and a lower alignment layer facing each other with the liquid crystal layer interposed therebetween in order to control the alignment of the liquid crystal layer.

Here, the upper alignment layer and the lower alignment layer are formed by rubbing after printing an alignment solution through a printing roller on a substrate. However, when the aligning agent 18 is printed, the aligning agent 18 flows into the contact hole 16 penetrating the protective film 14 formed on the substrate as shown in FIG. 1 , so that around the contact hole 16 . In the region, the aligning agent 18 is not formed or the aligning agent 18 is applied thinly. Accordingly, there is a problem in that the area around the contact hole 16 has a difference in luminance from that of other areas, resulting in a defective spot. In order to solve this problem, if the black matrix is formed to be long so as to overlap the area around the contact hole 16 , there is a problem in that the aperture ratio is decreased.

The present invention is to solve the above problems, and the present invention is to provide a substrate including a thin film transistor capable of preventing spot defects without reducing the aperture ratio.

In order to achieve the above object, in the substrate including the thin film transistor according to the present invention, a pixel auxiliary layer is positioned above or below the drain electrode to overlap the pixel buried electrode filling the pixel contact hole exposing the drain electrode, and the The upper surface of the pixel auxiliary layer or the upper surface of the drain electrode thereof is located closer to the upper surface of the planarization layer than the upper surface of the data line.

According to the present invention, the step difference between the upper surface of the pixel buried electrode and the upper surface of the planarization layer is reduced by the pixel buried electrode and the pixel auxiliary layer. Accordingly, when the alignment layer is formed, it is possible to minimize the flow of the alignment solution into the pixel contact hole, so that the alignment layer is uniformly formed, thereby preventing a luminance difference. In addition, since the depth of the pixel contact hole of the present invention is reduced, the risk of disconnection of the pixel electrode is lowered, so that a point defect can be prevented.

1 is a view for explaining an aligning agent flowing into a conventional contact hole.
2 is a cross-sectional view showing a substrate including a thin film transistor according to a first embodiment of the present invention.
FIG. 3 is a view showing an alignment layer of a substrate including the thin film transistor shown in FIG. 2 .
4A to 4G are cross-sectional views for explaining a method of manufacturing a substrate including the thin film transistor shown in FIG. 2 .
5 is a cross-sectional view illustrating a substrate including a thin film transistor according to a second embodiment of the present invention.
6A to 6E are cross-sectional views illustrating a method of manufacturing a substrate including the thin film transistor shown in FIG. 5 .
7 is a cross-sectional view illustrating a substrate including a thin film transistor according to a third embodiment of the present invention.
8A to 8D are cross-sectional views illustrating a method of manufacturing a substrate including the thin film transistor shown in FIG. 7 .
9 is a cross-sectional view illustrating a substrate including a thin film transistor according to a fourth embodiment of the present invention.
10A and 10B are cross-sectional views for explaining a method of manufacturing a substrate including the thin film transistor shown in FIG. 9 .
11 is a cross-sectional view illustrating a substrate including a thin film transistor according to a fourth embodiment of the present invention.
12A and 12B are cross-sectional views illustrating another arrangement of a pixel electrode and a common electrode of a substrate including a thin film transistor according to first to fourth embodiments of the present invention.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view showing a thin film transistor substrate according to a first embodiment of the present invention.

The thin film transistor substrate shown in FIG. 2 includes a thin film transistor, a pixel electrode 122 connected to the thin film transistor, and a common electrode 126 formed to form a fringe field with the pixel electrode 122 in the pixel region.

A thin film transistor is formed at the intersection of the gate line and the data line 104 . The thin film transistor causes the video signal on the data line 104 to be charged and maintained in the pixel electrode 122 in response to the scan signal of the gate line. To this end, the thin film transistor includes a gate electrode 106 , a source electrode 108 , a drain electrode 110 , an active layer 114 , and an ohmic contact layer 116 .

The gate electrode 106 overlaps the channel of the active layer 114 with the gate insulating layer 112 interposed therebetween. The gate electrode 106 is formed on the substrate 101 by molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper ( Cu) may be a single layer or a multilayer made of any one or an alloy thereof, but is not limited thereto. For example, the gate electrode 106 is formed in a structure in which a first gate metal layer 102a made of MoTi and a second gate metal layer 102b made of Cu are stacked. A gate signal is supplied to the gate electrode 106 through the gate pad 150 connected to the gate line.

The gate pad 150 includes a gate lower electrode 152 and a gate upper electrode 156 . The gate lower electrode 152 is formed on the substrate 101 with first and second gate metal layers 102a and 102b in the same manner as the gate electrode 106 . The gate upper electrode 156 is electrically connected to the gate lower electrode 152 exposed through the gate contact hole 158 penetrating the gate insulating layer 112 and the second passivation layer 138 . The gate upper electrode 156 is formed of the same material as the pixel electrode 122 , such as ITO, IZO, and ITZO, which have strong corrosion resistance and acid resistance.

The active layer 114 is formed on the gate insulating layer 112 to overlap the gate electrode 106 to form a channel between the source and drain electrodes 108 and 110 . The ohmic contact layer 116 is formed on the active layer 114 except for the channel for ohmic contact between each of the source and drain electrodes 108 and 110 and the active layer 114 . The active layer 114 and the ohmic contact layer 116 are formed to overlap not only the source and drain electrodes 108 and 110 , but also the data line 104 and the data lower electrode 142 .

The source electrode 108 is formed on the ohmic contact layer 116 with molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper. (Cu) may be a single layer or multiple layers made of any one or an alloy thereof, but is not limited thereto. A video signal is supplied to the source electrode 108 through the data pad 140 connected to the data line DL.

The data pad 140 includes a data lower electrode 142 , a data embedding electrode 144 , and a data upper electrode 146 . The data lower electrode 142 is formed on the ohmic contact layer 116 with the same material as the source and drain electrodes 108 and 110 . A data auxiliary layer 132 , a gate insulating layer 112 , an active layer 114 , and an ohmic contact layer 116 are formed between the data lower electrode 142 and the lower substrate 101 . The data buried electrode 144 is formed in the first data contact hole 148a to fill the first data contact hole 148a passing through the first passivation layer 118 and the planarization layer 128 . The data upper electrode 146 is electrically connected to the data embedding electrode 144 exposed through the second data contact hole 148b penetrating the second passivation layer 138 . The data upper electrode 146 is formed of the same material as the pixel electrode 122 , such as ITO, IZO, and ITZO with strong corrosion resistance and acid resistance.

The drain electrode 110 faces the source electrode 108 with the channel interposed therebetween, and is formed of the same material as the source electrode 108 . The drain electrode 110 is exposed through the first pixel contact hole 120a penetrating the first passivation layer 118 and the planarization layer 128 to be electrically connected to the pixel buried electrode 124 . Since the pixel buried electrode 124 is formed in the first pixel contact hole 120a to fill the first pixel contact hole 120a, the pixel buried electrode 124 is the first pixel buried electrode 124 exposed by the first pixel contact hole 120a. 1 The passivation layer 118 and the planarization layer 128 are in contact with respective side surfaces.

The pixel electrode 122 is formed to have a plurality of slits 122S on the second passivation layer 138 . The pixel electrode 122 is connected to the pixel buried electrode 124 exposed through the second pixel contact hole 120b and the drain electrode 110 connected to the pixel buried electrode 124 . In addition, the pixel electrode 122 overlaps the common electrode 126 with the second passivation layer 138 interposed therebetween to form a fringe field.

The common electrode 126 is formed in each pixel area and a common voltage is supplied through a common line. Accordingly, the common electrode 126 to which the common voltage is supplied forms a fringe field with the pixel electrode 122 to which the video signal is supplied through the thin film transistor, and liquid crystal molecules arranged in a horizontal direction between the thin film transistor substrate and the color filter substrate. They are rotated by dielectric anisotropy. In addition, the light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

As described above, in the first embodiment of the present invention, the pixel buried electrode 124 and the pixel auxiliary layer 130 overlapping the first pixel contact hole 120a and the data buried electrode 124 overlapping the first data contact hole 148a An electrode 144 and a data auxiliary layer 132 are provided.

Each of the pixel buried electrode 124 and the data buried electrode 144 is formed by using an electrolytic plating method or an electroless plating method to form low-resistance metals silver (Ag), gold (Au), copper (Cu), nickel (Ni), tin ( Sn), zinc (Zn) is formed of a plated metal. That is, the pixel buried electrode 124 is formed by plating a plating metal on the seed metal that is the drain electrode 110 exposed by the first pixel contact hole 120a, and the data buried electrode 144 is the first data contact. It is formed by plating a plating metal on the seed metal, which is the data lower electrode 142 exposed by the hole 148a. In this case, the thickness of each of the pixel buried electrode 124 and the data buried electrode 144 is equal to or greater than the depth of the corresponding contact hole (the first pixel contact hole 120a or the first data contact hole 148a). formed, and may be appropriately selected according to need. Here, when the thickness of each of the pixel buried electrode 124 and the data buried electrode 144 is formed to be greater than the depth of the corresponding contact hole (the first pixel contact hole 120a or the first data contact hole 148a), the pixel A top surface of each of the buried electrode 124 and the data buried electrode 144 is located on the same horizontal plane as an upper surface of the second passivation layer 138 , or an upper surface of the planarization layer 128 and an upper surface of the second passivation layer 138 . located between the sides.

Each of the pixel auxiliary layer 130 and the data auxiliary layer 132 is formed on the substrate 101 to have the same thickness as the gate electrode 106 or to be thicker than the gate electrode 106 . For example, the gate electrode 106 is formed of first and second gate metal layers 102a and 102b, and the pixel auxiliary layer 130 and the data auxiliary layer 132 are formed of the first and second gate metal layers 102a and 102b. 102b), or the first to third gate metal layers 102a, 102b, and 102c.

Since the drain electrode 110 protrudes upward from the data line 104 by the thickness of the pixel auxiliary layer 130 , the upper surface of the drain electrode 110 overlapping the first pixel contact hole 120a and the planarization layer ( 128), the distance between the upper surfaces becomes closer. Also, since the data lower electrode 142 protrudes from the data line 104 by the thickness of the data auxiliary layer 132 , the upper surface of the data lower electrode 142 overlapping the first data contact hole 148a and the planarization layer The distance between the top surfaces of (128) gets closer.

Accordingly, the depth of each of the first pixel contact hole 120a and the first data contact hole 148 passing through the first passivation layer 118 and the planarization layer 128 is reduced. The volume of the pixel buried electrode 124 positioned in the first pixel contact hole 120a and the data buried electrode 144 positioned in the first data contact hole 148a can be reduced, so that the pixel buried electrode 124 has a reduced depth. ) and the data embedding electrode 144 may be reduced in cost and process time.

In addition, the pixel buried electrode 124 and the data buried electrode 144, and the pixel auxiliary layer 130 and the data auxiliary layer 132, respectively, to the top surface of each of the pixel buried electrode 124 and the data buried electrode 144 and The step difference between the upper surfaces of the planarization layer 128 is reduced. Accordingly, as shown in FIG. 3 , when the alignment layer 160 is formed, it is possible to minimize the flow of the alignment solution into the pixel contact holes 102a and 120b, so that the alignment layer 160 is uniformly formed to prevent a luminance difference. can

4A to 4G are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention shown in FIG. 2 .

Referring to FIG. 4A , in a first mask process, a first pixel auxiliary layer 130 , a data auxiliary layer 132 , a gate electrode 106 , and a gate lower electrode 152 are included on the lower substrate 101 . A conductive pattern is formed. Specifically, a multi-layered gate metal layer is stacked on the lower substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used in a multi-layered structure. Then, the pixel auxiliary layer 130 , the data auxiliary layer 132 , the gate electrode 106 , and the gate are patterned by patterning the gate metal layer using the photoresist pattern formed through the exposure process and the development process using a photomask as a mask. A first conductive pattern including a lower electrode 152 is formed. Meanwhile, the pixel auxiliary layer 130 and the data auxiliary layer 132, which are higher than the gate electrode 106 and the gate lower electrode 152, are formed using a halftone mask or a slit mask, and the gate electrode 106 and the gate lower portion are formed. It may be formed simultaneously with the electrode 152 .

4B, the gate insulating layer 112 is formed on the lower substrate 101 on which the first conductive pattern is formed, and the active layer 114 and the ohmic contact layer ( A semiconductor pattern including the 116 and a second conductive pattern including the data line 104 , the source electrode 108 , the drain electrode 110 , and the data lower electrode 142 are formed.

Specifically, a gate insulating film 112, an amorphous silicon layer, and an amorphous silicon layer doped with impurities (n+ or p+) are sequentially formed on the lower substrate 101 on which the first conductive pattern is formed by a deposition method such as PECVD, A source/drain metal layer is formed thereon by a deposition method such as sputtering. An inorganic insulating material such as SiOx or SiNx is used as the gate insulating layer 112 . As the source/drain metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or is used in a multi-layer structure using these. Then, the gate insulating film ( On the 112, an active layer 114 and an ohmic contact layer 116 are formed with a semiconductor pattern, a data line 104, an integrated source electrode 108 and a drain electrode 110, and a data lower electrode 142. 2 A conductive pattern is formed. Here, the second conductive pattern is formed on the semiconductor pattern in the same pattern as the semiconductor pattern.

Referring to FIG. 4C , the first passivation layer 118 and the planarization layer 128 having the first pixel contact hole 120a and the first data contact hole 148a on the gate insulating layer 112 on which the second conductive pattern is formed. this is formed Specifically, the first passivation layer 118 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the gate insulating layer 112 on which the second conductive pattern is formed. Then, an organic insulating material such as photoacrylic is applied over the entire surface of the first passivation layer 118 , and then the organic insulating material is patterned by a photolithography process to form the planarization layer 128 . Here, the organic insulating material in which the thickness of the organic insulating material corresponding to the first pixel contact hole 120a and the first data contact hole 148a corresponds to a region different from that of the pixel auxiliary layer 130 and the data auxiliary layer 132 . It is applied thinner than the material. Accordingly, the exposure time of the organic insulating material corresponding to the first pixel contact hole 120a and the first data contact hole 148a is reduced, and process efficiency is improved. A first pixel contact hole 120a and a first data contact hole 148a are formed by etching the first passivation layer 118 using the planarization layer 128 as a mask. The first pixel contact hole 120a is formed to penetrate the first passivation layer 118 and the planarization layer 128 to expose the drain electrode 110 , and the first data contact hole 148a has the first passivation layer 118 . ) and the planarization layer 128 to expose the data lower electrode 142 .

Referring to FIG. 4D , a pixel embedding electrode 124 and a data embedding electrode 144 are formed on the substrate 101 on which the planarization layer 128 is formed. Specifically, the substrate on which the first data contact hole 148a and the first pixel contact hole 120a are formed is exposed to a solution containing metal ions. Accordingly, metal ions are adsorbed to the data lower electrode 142 exposed by the first data contact hole 148a and the drain electrode 110 exposed by the first pixel contact hole 120a to grow into plated metal. do. The plated metal is grown in the first data contact hole 148a and the first pixel contact hole 120a to form the pixel buried electrode 124 and the data buried electrode 144 .

Referring to FIG. 4E , a common electrode 126 is formed on the substrate 101 on which the pixel buried electrode 124 and the data buried electrode 144 are formed. Specifically, a transparent conductive layer is formed on the substrate 101 on which the pixel buried electrode 124 and the data buried electrode 144 are formed by a deposition method such as sputtering. ITO, TO, IZO, ITZO, etc. are used as a transparent conductive layer. Next, the common electrode 126 is formed by etching the transparent conductive layer using the photoresist pattern formed through the exposure process using a photomask and the developing process as a mask.

Referring to FIG. 4F , a second passivation layer 138 having a gate contact hole 158 , a second data contact hole 148b , and a second pixel contact hole 120b on the substrate 101 on which the common electrode 126 is formed. ) is formed. Specifically, the second passivation layer 138 is formed by stacking an inorganic insulating material such as SiOx or SiNx on the substrate 101 on which the common electrode 126 is formed. Then, the gate contact hole 158, the second data contact hole 148b, and the second passivation layer 138 are etched by etching the second passivation layer 138 using the photoresist pattern formed through the exposure process and the development process using a photomask as a mask. A pixel contact hole 120b is formed.

Referring to FIG. 4G , the pixel electrode 122 is formed on the substrate 101 on which the second passivation layer 138 having the gate contact hole 158 , the second data contact hole 148b and the second pixel contact hole 120b is formed. ), a gate upper electrode 156 and a data upper electrode 146 are formed. Specifically, a transparent conductive layer is formed on the second passivation layer 138 having the gate contact hole 158 , the second data contact hole 148b and the second pixel contact hole 120b by a deposition method such as sputtering. ITO, TO, IZO, ITZO, etc. are used as a transparent conductive layer. Then, the transparent conductive layer is etched using the photoresist pattern formed through the exposure process using a photomask and the developing process as a mask to form the pixel electrode 122 , the gate upper electrode 156 , and the data upper electrode 146 . do.

Then, an alignment layer is formed on the substrate 101 on which the pixel electrode 122 , the gate upper electrode 156 , and the data upper electrode 146 are formed.

5 is a cross-sectional view showing a thin film transistor substrate according to a second embodiment of the present invention.

The thin film transistor substrate shown in FIG. 5 further includes a gate buried electrode 154 in comparison with the thin film transistor substrate shown in FIG. 2 , and includes a pixel buried electrode 124 , a data buried electrode 144 , and a gate buried electrode 154 . ) has the same components except for the contact with the side surface of the second passivation layer 138 , so a detailed description of the same components will be omitted.

Specifically, in the second embodiment of the present invention, the pixel embedding electrode 124 filling the second pixel contact hole 120b, the data embedding electrode 144 filling the second data contact hole 148b, and the gate A gate buried electrode 154 filling the contact hole 154 is provided.

The pixel buried electrode 124 is electrically connected to the drain electrode 110 exposed by the second pixel contact hole 120b passing through the first and second passivation layers 118 and 138 , and is directly connected to the pixel electrode 122 . connected Also, the pixel buried electrode 124 contacts the side surfaces of the first and second passivation layers 118 and 138 exposed by the second pixel contact hole 120b positioned in the first pixel contact hole 120a, respectively.

The data embedding electrode 144 is electrically connected to the data lower electrode 142 exposed by the second data contact hole 120b penetrating the first and second passivation layers 118 and 138 , and the data upper electrode 146 . is directly connected to Also, the data embedding electrode 144 contacts the side surfaces of the first and second passivation layers 118 and 138 exposed by the second data contact hole 148b positioned in the first data contact hole 148a.

The gate buried electrode 154 is electrically connected to the gate lower electrode 152 exposed by the gate contact hole 158 penetrating the gate insulating layer 112 and the first and second passivation layers 118 and 138 , and the upper gate portion It is directly connected to the electrode 156 . The gate buried electrode 154 contacts side surfaces of the gate insulating layer 112 and the first and second passivation layers 118 and 138 exposed by the gate contact hole 158 , respectively.

Each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is formed of silver (Ag), gold (Au), and copper (Cu), which are low-resistance metals, by using an electrolytic plating method or an electroless plating method. , nickel (Ni), tin (Sn), is formed of a plated metal such as zinc (Zn). In this case, the thickness of each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is the corresponding contact hole (the second pixel contact hole 120b , the second data contact hole 148b , and the gate). It is formed to be equal to or larger than the depth of the contact hole 158 and may be appropriately selected according to need, where the thickness of each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is thick. is formed to be greater than the depth of the corresponding contact hole, the upper surface of each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is positioned above the upper surface of the second passivation layer 138 .

Each of the pixel auxiliary layer 130 and the data auxiliary layer 132 is formed on the substrate 101 to have the same thickness as the gate electrode 106 or to be thicker than the gate electrode 106 . For example, the gate electrode 106 is formed of first and second gate metal layers 102a and 102b, and the pixel auxiliary layer 130 is formed of the first and second gate metal layers 120a and 120b or first to second gate metal layers 120a and 120b. It is formed of three gate metal layers 102a, 102b, and 102c.

The drain electrode 110 protrudes from the data line 104 by the thickness of the pixel auxiliary layer 130 , and the data lower electrode 142 protrudes from the data line 104 by the thickness of the data auxiliary layer 132 .

Accordingly, the volume of the pixel electrode 122 filling the second pixel contact hole 120b positioned in the first pixel contact hole 120a can be reduced, and the second pixel contact hole 120b positioned in the first data contact hole 148a can be reduced in volume. The volume of the data embedding electrode 144 filling the data contact hole 148b may be reduced. When the pixel buried electrode 124 and the data buried electrode 144 are formed, cost and process time may be reduced.

In addition, the pixel buried electrode 124 and the data buried electrode 144, and the pixel auxiliary layer 130 and the data auxiliary layer 132, respectively, to the top surface of each of the pixel buried electrode 124 and the data buried electrode 144 and The step difference between the upper surfaces of the planarization layer 128 is reduced. Accordingly, when the alignment layer is formed on the substrate on which the pixel filling electrode 124 and the data filling electrode 144 are formed, it is possible to minimize the flow of the alignment solution into the pixel contact holes 102a and 120b, so that the alignment layer 160 is uniformly formed. formed to prevent a luminance difference from occurring.

In addition, since the gate pad 150 includes the gate buried electrode 154 connected thereto between the gate lower electrode 152 and the gate upper electrode 156 , the resistance of the gate pad 150 can be reduced, so that the gate signal delay can be avoided. In addition, since the data pad 140 includes the data embedding electrode 144 between the data lower electrode 142 and the data upper electrode 146 connected thereto, the resistance of the data pad 140 can be reduced, thereby delaying the data signal. can prevent

6A to 6E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to the first embodiment of the present invention shown in FIG. 5 .

Referring to FIG. 6A , a thin film transistor, a gate lower electrode 152 , a data lower electrode 142 , a data line 104 , a pixel auxiliary layer 130 , and a data auxiliary layer 132 are formed on a substrate 101 . do. Since the manufacturing method thereof is the same as that of FIGS. 4A and 4B described above, a detailed description thereof will be omitted.

Then, inorganic insulation such as SiNx or SiOx is formed on the gate insulating film 112 on which the second conductive pattern including the source and drain electrodes 108 and 110 of the thin film transistor, the data lower electrode 142 and the data line 104 is formed. A first passivation layer 118 is formed by depositing a material over the entire surface. Then, an organic insulating material such as photoacrylic is applied over the entire surface of the first passivation layer 118 , and then the organic insulating material is patterned by a photolithography process to form the planarization layer 128 . A first pixel contact hole 120a and a first data contact hole 148a are formed by etching the first passivation layer 118 using the planarization layer 128 as a mask. Each of the first pixel contact hole 120a and the first data contact hole 148a is formed to penetrate the planarization layer 128 to expose the first passivation layer 118 .

Referring to FIG. 6B , the common electrode 126 is formed on the substrate 101 on which the planarization layer 128 is formed. Specifically, a transparent conductive layer is formed on the substrate 101 on which the planarization layer 128 is formed by a deposition method such as sputtering. ITO, TO, IZO, ITZO, etc. are used as a transparent conductive layer. Next, the common electrode 126 is formed by etching the transparent conductive layer using the photoresist pattern formed through the exposure process using a photomask and the developing process as a mask.

Referring to FIG. 6C , a second passivation layer including a gate contact hole 158 , a second data contact hole 148b , and a second pixel contact hole 120b is formed on the substrate 101 on which the common electrode 126 is formed. 138) is formed. Specifically, the second passivation layer 138 is formed by stacking an inorganic insulating material such as SiOx or SiNx on the substrate 101 on which the common electrode 126 is formed. Then, the first and second passivation layers 118 and 138 are etched using the photoresist pattern formed through the exposure process and the development process using a photomask as a mask to form the gate contact hole 158 and the second data contact hole ( 148b) and a second pixel contact hole 120b are formed.

Referring to FIG. 6D , on the substrate 101 on which the second passivation layer 138 having the gate contact hole 158 , the second data contact hole 148b , and the second pixel contact hole 120b is formed, a pixel buried electrode ( 124 , a gate buried electrode 154 , and a data buried electrode 144 are formed. Specifically, the substrate 101 on which the gate contact hole 158 , the second data contact hole 148b , and the second pixel contact hole 120b are formed is exposed to a solution containing metal ions. Accordingly, the data lower electrode 142 exposed through the second data contact hole 148b, the drain electrode 110 exposed through the second pixel contact hole 120b, and the gate contact hole 158 Metal ions are adsorbed to the exposed gate lower electrode 152 to grow into plated metal. The plated metal is grown in the second data contact hole 148b, the gate contact hole 158, and the second pixel contact hole 120b, so that the data buried electrode 144, the gate buried electrode 154, and the pixel buried electrode ( 124) is formed.

Referring to FIG. 6E , the pixel electrode 122 , the gate upper electrode 156 , and the data upper electrode are formed on the substrate 101 on which the data buried electrode 144 , the gate buried electrode 154 and the pixel buried electrode 124 are formed. (146) is formed. Specifically, a transparent conductive layer is formed on the second passivation layer 138 on which the data buried electrode 144 , the gate buried electrode 154 , and the pixel buried electrode 124 are formed by a deposition method such as sputtering. ITO, TO, IZO, ITZO, etc. are used as a transparent conductive layer. Then, the transparent conductive layer is etched using the photoresist pattern formed through the exposure process using a photomask and the developing process as a mask to form the pixel electrode 122 , the gate upper electrode 156 , and the data upper electrode 146 . do.

7 is a cross-sectional view showing a thin film transistor substrate according to a third embodiment of the present invention.

In the thin film transistor substrate shown in FIG. 7 , in contrast to the thin film transistor substrate shown in FIG. 2 , the pixel auxiliary layer 130 is formed on the drain electrode 110 , and the data auxiliary layer 132 is the data lower electrode 132 . It has the same components except that it is formed on the top. Accordingly, detailed descriptions of the same components will be omitted.

The pixel auxiliary layer 130 is formed on the drain electrode 110 to be electrically connected to the drain electrode 110 . Accordingly, since the distance between the upper surface of the pixel auxiliary layer 130 overlapping the first pixel contact hole 120a and the upper surface of the planarization layer 128 becomes close, the first passivation layer 118 and the planarization layer 128 ), the depth of the first pixel contact hole 120a passing through is reduced. Also, the data auxiliary layer 132 is formed on the data lower electrode 142 to be electrically connected to the data lower electrode 142 . Accordingly, since the distance between the upper surface of the data auxiliary layer 132 overlapping the first data contact hole 148a and the upper surface of the planarization layer 128 becomes close, the first passivation layer 118 and the planarization layer 128 . ), the depth of the first data contact hole 148a passing through is reduced.

Accordingly, the volume of the pixel buried electrode 124 positioned in the first pixel contact hole 120a and the data buried electrode 144 positioned in the first data contact hole 148a can be reduced, so that the pixel buried electrode 124 is reduced. ) and the data embedding electrode 144 may be reduced in cost and process time.

In addition, the pixel buried electrode 124 and the data buried electrode 144, and the pixel auxiliary layer 130 and the data auxiliary layer 132, respectively, to the top surface of each of the pixel buried electrode 124 and the data buried electrode 144 and The step difference between the upper surfaces of the planarization layer 128 is reduced. Accordingly, as shown in FIG. 3 , when the alignment layer 160 is formed, since the alignment solution does not flow into the contact hole, the alignment layer 160 is uniformly formed, thereby preventing a luminance difference.

8A to 8D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a third exemplary embodiment of the present invention shown in FIG. 7 .

Referring to FIG. 8A , a first conductive pattern including a gate electrode 106 and a gate lower electrode 152 is formed on a lower substrate 101 . Specifically, a multi-layered gate metal layer is stacked on the lower substrate 101 through a deposition method such as a sputtering method. As the gate metal layer, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used in a multi-layered structure. Then, the first conductive pattern including the gate electrode 106 and the gate lower electrode 152 by patterning the gate metal layer using the photoresist pattern formed through the exposure process and the development process using the first photomask as a mask. this is formed

Referring to FIG. 8B , a gate insulating layer 112 is formed on the substrate on which the first conductive pattern is formed, and an active layer 114 and an ohmic contact layer 116 are formed on the gate insulating layer 112 . Specifically, the gate insulating layer 112 is formed by depositing an inorganic insulating material such as SiOx or SiNx on the lower substrate 101 on which the first conductive pattern is formed by a deposition method such as PECVD. Then, an amorphous silicon layer and an amorphous silicon layer doped with impurities (n+ or p+) are sequentially formed on the gate insulating layer 112 , and then the amorphous silicon layer and impurities (n+ or p+) are formed by a photolithography process and an etching process. An active layer 114 and an ohmic contact layer 116 are formed by patterning the doped amorphous silicon layer.

Referring to FIG. 8C , the pixel auxiliary layer 130 , the data auxiliary layer 132 , the data lower electrode 142 , and the source and drain electrodes are on the substrate 101 on which the active layer 114 and the ohmic contact layer 116 are formed. (108,110) is formed. Specifically, first and second data metal layers are sequentially deposited on the substrate 101 on which the active layer 114 and the ohmic contact layer 116 are formed. As each of the first and second data metal layers, a metal material such as Mo, Ti, Cu, AlNd, Al, Cr, or an alloy thereof is used as a single layer, or a multilayer structure is used using them. Then, the pixel auxiliary layer 130 , the data auxiliary layer 132 , the data lower electrode 142 , and the source and drain electrodes 108 and 110 are formed by patterning the first and second data metal layers using a photolithography process and an etching process. formed at the same time In this case, the data lower electrode 142 and the source and drain electrodes 108 and 110 are formed of the first source/drain metal layer, and the pixel auxiliary layer 130 and the data auxiliary layer 132 are the data lower electrode 142 and the source. and a second source/drain metal layer on the drain electrodes 108 and 110 . In addition, the pixel auxiliary layer 130 and the data auxiliary layer 132 are formed on the drain electrode 110 and the data lower electrode 142 by using a halftone mask or a slit mask, the drain electrode 110 and the data lower electrode ( 142) and formed at the same time. Then, the channel region of the active layer 114 is exposed by etching the ohmic contact layer 116 exposed between the source and drain electrodes 108 and 110 using the source and drain electrodes 108 and 110 as a mask.

Referring to FIG. 8D , a first passivation layer 118 having a first pixel contact hole 120a and a first data contact hole 148a and a planarization layer are formed on the gate insulating layer 112 on which the second conductive pattern is formed. . Then, a pixel embedding electrode and a data embedding electrode are formed on the substrate on which the planarization layer is formed. Then, a common electrode 126 is formed on the substrate 101 on which the pixel buried electrode 124 and the data buried electrode 144 are formed. A second passivation layer 138 having a gate contact hole 158 , a second data contact hole 148b , and a second pixel contact hole 120b is formed on the substrate 101 on which the common electrode 126 is formed. A pixel electrode 122 and a gate upper electrode ( 156 and a data upper electrode 146 are formed. Meanwhile, since the manufacturing process after the second conductive pattern is the same as that of FIGS. 4C to 4G , a detailed description thereof will be omitted.

9 is a cross-sectional view showing a thin film transistor substrate according to a fourth embodiment of the present invention.

The thin film transistor substrate shown in FIG. 9 further includes a gate buried electrode 154 compared to the thin film transistor substrate shown in FIG. 7 , and a pixel buried electrode 124 , a data buried electrode 144 , and a gate buried electrode 154 . ) has the same components except for the contact with the side surface of the second passivation layer 138 , so a detailed description of the same components will be omitted.

Specifically, in the fourth embodiment of the present invention, the pixel embedding electrode 124 filling the second pixel contact hole 120b, the data embedding electrode 144 filling the second data contact hole 148b, and the gate A gate buried electrode 154 filling the contact hole 154 is provided.

The pixel buried electrode 124 is electrically connected to the drain electrode 110 exposed through the second pixel contact hole 120b penetrating the first and second passivation layers 118 and 138 . The data embedding electrode 144 is electrically connected to the data lower electrode 142 exposed through the second data contact hole 120b passing through the first and second passivation layers 118 and 138 . The gate buried electrode 154 is electrically connected to the gate lower electrode 152 exposed by the gate contact hole 158 penetrating the gate insulating layer 112 and the first and second passivation layers 118 and 138 .

Each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is formed of silver (Ag), gold (Au), and copper (Cu), which are low-resistance metals, by using an electrolytic plating method or an electroless plating method. , nickel (Ni), tin (Sn), is formed of a plated metal such as zinc (Zn). In this case, the thickness of each of the pixel buried electrode 124 , the data buried electrode 144 , and the gate buried electrode 154 is the corresponding contact hole (the second pixel contact hole 120b , the second data contact hole 148b , and the gate). It is formed to be equal to or larger than the depth of the contact hole 158, and may be appropriately selected according to need.

The pixel auxiliary layer 130 is formed on the drain electrode 110 to be electrically connected to the drain electrode 110 . Accordingly, since the distance between the upper surface of the pixel auxiliary layer 130 overlapping the first pixel contact hole 120a and the upper surface of the planarization layer 128 becomes close, the first pixel passing through the planarization layer 128 . The depth of the contact hole 120a is reduced. Also, the data auxiliary layer 132 is formed on the data lower electrode 142 to be electrically connected to the data lower electrode 142 . Accordingly, since the distance between the upper surface of the data auxiliary layer 132 overlapping the first data contact hole 148a and the upper surface of the planarization layer 128 becomes close, the first data passing through the planarization layer 128 . The depth of the contact hole 148a is reduced.

Accordingly, the volume of the pixel embedding electrode 124 filling the second pixel contact hole 120b and the data embedding electrode 144 filling the second data contact hole 148b can be reduced, so that the pixel embedding electrode 124 is reduced. ) and the data embedding electrode 144 may be reduced in cost and process time.

In addition, the pixel buried electrode 124 and the data buried electrode 144, and the pixel auxiliary layer 130 and the data auxiliary layer 132, respectively, to the top surface of each of the pixel buried electrode 124 and the data buried electrode 144 and The step difference between the upper surfaces of the planarization layer 128 is reduced. Accordingly, as shown in FIG. 3 , when the alignment layer 160 is formed, since the alignment solution does not flow into the contact hole, the alignment layer 160 is uniformly formed, thereby preventing a luminance difference.

In addition, since the gate pad 150 includes the gate buried electrode 154 connected thereto between the gate lower electrode 152 and the gate upper electrode 156 , the resistance of the gate pad 150 can be reduced, so that the gate signal delay can be avoided. In addition, since the data pad 140 includes the data embedding electrode 144 between the data lower electrode 142 and the data upper electrode 146 connected thereto, the resistance of the data pad 140 can be reduced, thereby delaying the data signal. can prevent

10A to 10B are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a fourth embodiment of the present invention shown in FIG. 9 .

Referring to FIG. 10A , a thin film transistor, a gate lower electrode, a data lower electrode, a data line and a pixel auxiliary layer 130 , and a data auxiliary layer 132 are formed on a substrate 101 . Since the manufacturing method thereof is the same as that of FIGS. 8A and 8C described above, a detailed description thereof will be omitted.

Referring to FIG. 10B , a first passivation layer 118 is formed by depositing an inorganic insulating material such as SiNx or SiOx on the gate insulating layer 112 on which the second conductive pattern is formed, and then on the first passivation layer 118 . A planarization layer 128 having one pixel contact hole 120a and a first data contact hole 148a is formed. A common electrode 126 is formed on the substrate 101 on which the planarization layer 128 is formed. A second passivation layer 138 including a gate contact hole 158 , a second data contact hole 148b , and a second pixel contact hole 120b is formed on the substrate 101 on which the common electrode is formed. The pixel buried electrode 124 and the gate buried electrode are formed on the substrate 101 on which the second passivation layer 138 having the gate contact hole 158 , the second data contact hole 148b and the second pixel contact hole 120b is formed. 154 and a data embedding electrode 144 are formed. A pixel electrode 122 , a gate upper electrode 156 , and a data upper electrode 146 are formed on the substrate 101 on which the data buried electrode 144 , the gate buried electrode 154 , and the pixel buried electrode 124 are formed. . Since this manufacturing method is the same as that of FIGS. 6A to 6E described above, a detailed description thereof will be omitted.

Meanwhile, in the first and second embodiments of the present invention, the pixel auxiliary layer 130 and the data auxiliary layer 132 made of a gate metal layer are provided on the same plane as the gate electrode 106 , and the third and In the fourth embodiment, the pixel auxiliary layer 130 and the data auxiliary layer 132 formed of the source/drain metal layer are provided on the same plane as the data line 104 as an example. Similarly, on the same plane as the gate electrode 106 , the first pixel auxiliary layer 130a and the first data auxiliary layer 132a are formed of a gate metal layer, and the source/drain metal layer is formed on the same plane as the data line 104 . A second auxiliary pixel layer 130b and a second auxiliary data layer 132b may be provided.

Also, in the first to fourth embodiments of the present invention, the structure in which the pixel electrode 122 having the slit 122S is formed on the second passivation layer 138 covering the common electrode 126 has been described as an example. 12A and 12B , a common electrode 126 having a slit 126S may be formed on the second passivation layer covering the pixel electrode 122 .

In the present invention, although the gate upper electrode 156 and the data upper electrode 146 are separated, when the same signal is supplied to the gate pad and the data pad, the gate upper electrode 156 and the data upper electrode 146 are separated. It can also be electrically connected.

In addition, although the fringe electric field structure has been described as an example in the present invention, it is applicable to all liquid crystal display panel structures such as a horizontal electric field type or a vertical electric field type.

The above description is merely illustrative of the present invention, and various modifications may be made by those of ordinary skill in the art to which the present invention pertains without departing from the technical spirit of the present invention. Therefore, the embodiments disclosed in the specification of the present invention do not limit the present invention. The scope of the present invention should be construed by the following claims, and all technologies within the scope equivalent thereto should be construed as being included in the scope of the present invention.

122: pixel electrode 124: pixel buried electrode
130: pixel auxiliary layer 132: data auxiliary layer
136: common electrode 144: data buried electrode
154: gate buried electrode

Claims (12)

a thin film transistor connected to the gate line and the data line;
a planarization layer having a pixel contact hole exposing a drain electrode of the thin film transistor;
a first pixel auxiliary layer overlapping the pixel contact hole and positioned under the drain electrode;
a pixel buried electrode filling the pixel contact hole and connected to the drain electrode;
the first pixel auxiliary layer is positioned on the same plane as the gate line and is made of a metal thicker than each of the gate line and the gate electrode of the thin film transistor;
an upper surface of the drain electrode is closer to an upper surface of the planarization layer than an upper surface of the data line;
and the pixel buried electrode includes a thin film transistor having an upper surface higher than an upper surface of the planarization layer.
delete The method of claim 1,
The pixel auxiliary layer includes a thin film transistor including a first metal layer constituting the gate electrode of the thin film transistor, and a second metal layer on the first metal layer. The method of claim 1,
a second pixel auxiliary layer on the drain electrode and in direct contact with the drain electrode;
and a thin film transistor having a shorter distance between the upper surface of the second pixel auxiliary layer and the upper surface of the planarization layer than the distance between the upper surface of the data line and the upper surface of the planarization layer. 5. The method of claim 4,
The second pixel auxiliary layer overlaps the pixel contact hole and has a width smaller than that of the drain electrode,
A substrate comprising a thin film transistor made of the same metal as the drain electrode or a different metal. 5. The method of any one of claims 1, 3 and 4,
The planarization layer is made of an organic insulating material,
Further comprising a first protective film and a second protective film of an inorganic insulating material on the lower and upper portions of the planarization layer, respectively,
The pixel contact hole is
a first pixel contact hole passing through the first passivation layer covering the thin film transistor and the planarization layer;
a second pixel contact hole penetrating the second passivation layer covering the pixel buried electrode;
and the pixel buried electrode includes a thin film transistor in contact with side surfaces of the first passivation layer and the planarization layer exposed by the first pixel contact hole. a thin film transistor connected to the gate line and the data line;
a first passivation layer of an inorganic insulating material and a planarization layer of an organic insulating material, which are sequentially provided to cover the thin film transistor;
a first pixel auxiliary layer disposed under the drain electrode of the thin film transistor and formed of a metal thicker than the gate electrode on the same plane as the gate electrode of the thin film transistor;
a first pixel contact hole corresponding to the drain electrode and provided through the planarization layer and overlapping the first pixel auxiliary layer;
a common electrode overlapping the entire width of the data line on the planarization layer;
a second passivation layer of an inorganic insulating material provided to cover an upper portion of the common electrode;
a second pixel contact hole provided in the second passivation layer and the first passivation layer to expose the drain electrode inside the first pixel contact hole;
a pixel buried electrode filling the second pixel contact hole and connected to the drain electrode;
a pixel electrode connected to the pixel connection pattern and the pixel connection pattern integrally connected to the pixel buried electrode, the pixel electrode overlapping the common electrode on the second passivation layer, and branched with a slit therebetween;
an alignment layer provided on the second passivation layer including the pixel connection pattern and the pixel electrode;
The pixel buried electrode includes a thin film transistor including an upper surface equal to the upper surface of the second passivation layer, and a side surface in contact with side surfaces of the first and second passivation layers exposed by the second pixel contact hole. a thin film transistor connected to the gate line and the data line;
a gate pad electrode and a data pad electrode respectively provided at an end of the gate line and an end of the data line;
a planarization layer having a pixel contact hole exposing the drain electrode of the thin film transistor and a data contact hole exposing the data pad electrode;
a first pixel auxiliary layer overlapping the pixel contact hole and located under the drain electrode, and a data auxiliary layer overlapping the data contact hole and located under the data pad electrode;
a pixel buried electrode filling the pixel contact hole and connected to the drain electrode, and a data embedding electrode filling the data contact hole and connected to the data pad electrode;
a pixel electrode connected to the pixel buried electrode and a data upper electrode connected to the data buried electrode on the planarization layer;
The first pixel auxiliary layer and the data auxiliary layer are positioned on the same plane as the gate line and are made of a metal thicker than each of the gate line and the gate electrode of the thin film transistor;
an upper surface of the drain electrode is closer to an upper surface of the planarization layer than an upper surface of the data line;
and a thin film transistor including upper surfaces of the pixel buried electrode and the data buried electrode that are higher than or equal to upper surfaces of the planarization layer. 9. The method of claim 8,
and a thin film transistor further including a second pixel auxiliary layer between the pixel buried electrode and the drain electrode. 9. The method of claim 8,
Further comprising a common electrode on the planarization layer,
and the pixel electrode includes a thin film transistor overlapping the common electrode with a passivation layer interposed therebetween. 11. The method of claim 10,
and a thin film transistor in which the pixel electrode or the common electrode located on the passivation layer is branched into a plurality. 11. The method of claim 10,
and the passivation layer includes a thin film transistor further including a contact hole at a connection portion between the data buried electrode and the data upper electrode.

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