KR102332423B1 - Shift Resistor and Display Device having the Same - Google Patents

Abstract

A display device according to the present invention includes a display panel in which pixels are disposed on each of first to nth pixel lines, and a shift register that supplies scan signals to first and second scan lines connected to each of the pixels. The shift register includes first to n-th (n is a natural number) scan drivers that are cascadedly connected to each other. The i-th scan driver (i is a natural number less than or equal to “n-2”) includes a first scan signal supplied to a first scan line connected to the pixels of the i-th pixel line and a first scan signal connected to the pixels of the i-th pixel line. A second scan signal supplied to the second scan line is generated.

Description

Shift Resistor and Display Device having the Same

The present invention relates to a shift register and a display device including the same.

Flat panel displays (FPDs) are widely used in portable computers such as notebook computers and tablets, mobile phone terminals, etc. as well as monitors of desktop computers due to their advantages in miniaturization and weight reduction. Such a flat panel display device is a liquid crystal display device; LCD), Plasma Display Panel (PDP), Field Emission Display; FED) and organic light emitting diode display (OLED).

Among them, the organic light emitting diode display has advantages of fast response speed, high luminance efficiency, and a large viewing angle. In general, an organic light emitting diode display applies a data voltage to a gate electrode of a driving transistor using a transistor turned on by a scan signal, and charges the data voltage supplied to the driving transistor to a storage capacitor. Then, the organic light emitting diode emits light by outputting the data voltage charged in the storage capacitor using the light emission control signal.

Although the driving transistors disposed in all pixels should have the same electrical characteristics, they become non-uniform due to process conditions or driving environments. For this reason, the driving current according to the same data voltage varies for each pixel, and as a result, a luminance deviation occurs between the pixels. In order to solve this problem, a picture quality compensation technique for reducing luminance non-uniformity by sensing characteristic parameters (threshold voltage, mobility) of a driving transistor from each pixel and correcting input data according to the sensing result is known.

Among the image quality compensation technologies, the internal compensation method controls the pixel structure and driving timing to exclude the electrical characteristics of the driving transistor while the organic light emitting diode emits light. The internal compensation method basically raises the gate voltage of the driving transistor in the source-follower method to perform a sampling operation to saturate it to a certain level.

The internal compensation method has a pixel structure composed of a plurality of transistors, and each pixel is operated by gate signals. Depending on the pixel structure, the gate signals may include two or more signals. In general, the gate signals include a transistor that initializes a main node of a pixel, a scan signal applied to the transistors that control an operation of charging a data voltage in the pixel, and an emission signal that controls an emission period of the pixel.

The gate driver for applying the gate signals is sometimes implemented in the form of a gate-in-panel (GIP) in the bezel area of the display panel. The GIP type gate driver includes a shift register composed of stages that are connected to each other subordinately to generate one gate signal. Accordingly, shift registers are required as many as the number of gate signals. Depending on the pixel structure, a shift register is required, which increases the bezel area.

An object of the present invention is to provide a shift register capable of reducing a bezel area of a display panel and a display device including the same.

In order to achieve the above object, a display device according to the present invention provides a shift supplying scan signal to a display panel in which pixels are disposed on each of the first to nth pixel lines, and to first and second scan lines connected to each of the pixels. Includes registers. The shift register includes first to n-th (n is a natural number) scan drivers that are cascadedly connected to each other. The i-th scan driver (i is a natural number less than or equal to “n-2”) includes a first scan signal supplied to a first scan line connected to the pixels of the i-th pixel line and a first scan signal connected to the pixels of the i-th pixel line. A second scan signal supplied to the second scan line is generated.

The display device according to the present invention generates first and second scan signals having different output timings from scan drivers that are dependently connected to each other. That is, since the shift registers for generating the first and second scan signals are not separately provided, the number of shift registers can be reduced, and as a result, the bezel area of the display panel in which the shift registers are disposed can be reduced.

1 is a view showing the configuration of an organic light emitting diode display according to the present invention.
Fig. 2 is a diagram showing the configuration of a shift register according to the present invention;
3 is a diagram illustrating a pixel structure according to a first embodiment of the present invention;
FIG. 4 is a diagram illustrating timing of gate signals for driving the pixel shown in FIG. 3;
5 is a diagram showing a scan driver according to the present invention;
6 is a diagram illustrating scan clock timing according to the first embodiment;
FIG. 7 is a diagram illustrating voltage changes of BST1 and BST2 according to the scan clock timing shown in FIG. 6;
8 is a diagram illustrating a pixel structure according to a second embodiment;
FIG. 9 is a diagram illustrating timing of gate signals for driving the pixel shown in FIG. 8;
10 is a diagram illustrating scan clock timing according to the second embodiment;

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals refer to substantially identical elements throughout. In the following description, if it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, component names used in the following description may be selected in consideration of the ease of writing the specification, and may be different from the component names of the actual product. In describing various embodiments, substantially the same components are representatively described in the introduction and may be omitted in other embodiments.

Terms including an ordinal number, such as first, second, etc., may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the gate driver of the present invention, the switch elements may be implemented as transistors of an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. It should be noted that although the p-type transistor is exemplified in the following embodiments, the present invention is not limited thereto. A transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In the transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type MOSFET, the direction of current flows from drain to source because electrons flow from source to drain. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET may be changed according to an applied voltage. The invention should not be limited by the source and drain of the transistor in the following embodiments.

1 is a diagram showing the configuration of a display device according to the present invention.

Referring to FIG. 1 , an organic light emitting diode display according to the present invention includes a display panel 100 in which pixels P are arranged in a matrix form, a data driver 120 , gate drivers 130 and 140 , and a timing controller 110 . to provide

The display panel 100 includes a display unit 100A in which pixels P are arranged to display an image, and a non-display unit 100B in which a shift register 140 is arranged and does not display an image.

The display unit 100A includes a plurality of pixels P, and displays an image based on a gray level displayed by each pixel P. The pixels P are arranged along the first to nth pixel lines HL1 to HL[n]. Each pixel P is connected to a data line DL arranged along a column line and connected to a gate line GL arranged along a pixel line HL. That is, pixels disposed on the same pixel line share the same gate line GL and are simultaneously driven. In addition, when pixels disposed on the first pixel line HL1 are defined as first pixels P1 and pixels disposed on the nth pixel line HLn are defined as nth pixels Pn, the first pixel From (P1) to n-th pixels (Pn) are sequentially driven. In addition, a sampling period in which data is written in one scan line may be defined as one horizontal period (1H).

The gate line GL may include an emission line and a plurality of scan lines according to a pixel structure. As shown in FIG. 2 , the gate line GL according to an embodiment of the present invention includes a first scan line SL1 , a second scan line SL2 , and an emission line EML.

The timing controller 110 controls driving timings of the data driver 120 and the gate drivers 130 and 140 . To this end, the timing controller 110 rearranges digital video data RGB input from the outside to match the resolution of the display panel 100 and supplies it to the data driver 120 . In addition, the timing controller 110 controls the data driver 120 based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The data control signal DDC for controlling the operation timing and the gate control signal GDC for controlling the operation timing of the gate drivers 130 and 140 are generated.

The data driving unit 120 is for driving the data line unit DL. To this end, the data driver 120 converts the digital video data RGB input from the timing controller 110 into an analog data voltage based on the data control signal DDC and supplies it to the data lines DL.

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140 . The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC, and the shift register 140 is a gate formed in the non-display area 100B of the display panel 100 . - It is formed in a gate-in-panel (GIP) method.

The level shifter 130 level-shifts the clocks and the start signal VST under the control of the timing controller 110 , and then supplies them to the shift register 140 . The shift register 140 is formed by a combination of a plurality of thin film transistors (hereinafter referred to as transistors) in the non-display area 100B of the display panel 100 by the GIP method.

2 is a diagram showing a shift register according to the present invention.

Referring to FIG. 2 , the shift register according to the present invention includes an emission signal generator 141 and a scan signal generator 143 .

The emission signal generator 141 includes first to n-th emission drivers EMD1 to EMDn. The first emission driver EMD1 generates the emission signal EM1 and applies it to the emission line EML( 1 ) of the first pixel line HL1 . The second emission driver EMD2 generates the emission signal EM2 and applies it to the emission line EML( 2 ) of the second pixel line HL2 . The n-th emission driver EMDn generates the emission signal EMn and applies it to the emission line EML(n) of the n-th pixel line HLn.

The scan signal generator 143 includes first to nth scan drivers SD1 to SDn. The first scan driver SD1 generates a first scan signal SCAN1(1) and applies it to the first scan line SL1(1) of the first pixel line HL1, and the second scan signal SCAN2( 1)) is generated and applied to the second scan line SL2(1) of the first pixel line HL1. The second scan driver SD2 generates a first scan signal SCAN1(2) and applies it to the first scan line SL1(2) of the second pixel line HL2, and the second scan signal SCAN2( 2)) is generated and applied to the second scan line SL2(2) of the second pixel line HL2. The n-th scan driver SDn generates a first scan signal SCAN1(1) and applies it to the first scan line SL1(n) of the n-th pixel line HLn, and the second scan signal SCAN2( 1)) is generated and applied to the second scan line SL2(n) of the nth pixel line HLn.

The first to n-th emission drivers EMD1 to EMDn of the emission signal generating unit 141 are dependently connected to each other, and similarly, the first to n-th scan drivers SD1 to SDn of the scan signal generating unit 143 . are dependently connected to each other. In particular, as shown in the drawing, each of the scan drivers SD1 to SDn generates first and second scan signals SCAN1 and SCAN2. As described above, since each of the scan drivers SD1 to SDn outputs the first and second scan signals SCAN1 and SCAN2 , the overall size of the scan signal generator 143 may be reduced. Accordingly, the bezel on which the scan drivers SD1 to SDn are disposed can be reduced.

Hereinafter, an embodiment of the organic light emitting diode display to which the scan signal generator of the present invention is applied will be described.

3 is a diagram illustrating a pixel according to the first embodiment. The pixel illustrated in FIG. 3 illustrates pixels disposed on the first pixel line HL1. Pixels disposed on other pixel lines may also have the same structure as shown in FIG. 3 .

Referring to FIG. 3 , the pixel according to the embodiment includes a driving transistor DT, first to sixth transistors T1 to T6 , and a storage capacitor Cst.

The driving transistor DT controls a driving current applied to the organic light emitting diode OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the first node N1 , the source electrode is connected to the third node N3 , and the drain electrode is connected to the second node N2 . The first transistor T1 connects the first node N1 and the second node N2 in response to the second scan signal SCAN2( 1 ). The second transistor T2 connects the data line DL and the third node N3 in response to the second scan signal SCAN2( 1 ). The third transistor T3 connects the third node N3 to the input terminal of the high potential driving voltage VDD in response to the emission signal EM( 1 ). The fourth transistor T4 connects the second node N2 and the fourth node N4 in response to the emission signal EM( 1 ). The fifth transistor T5 connects the first node N1 to the input terminal of the initialization voltage Vini in response to the first scan signal SCAN1(1). The sixth transistor T6 connects the input terminal of the initialization voltage Vini and the fourth node N4 in response to the second scan signal SCAN2( 1 ). In addition, the storage capacitor Cst is connected between the first node N1 and the input terminal of the initialization voltage Vini.

FIG. 4 is a diagram illustrating timing of gate signals for driving the pixel shown in FIG. 3 . In particular, the operation of the pixels of the first pixel line HL1 will be examined based on the first scan signal SCAN1( 1 ) and the second scan signal SCAN2( 1 ) output by the first scan driver SD1 . do it with

Referring to FIGS. 3 and 4 , driving of the pixel is as follows.

In the initial period Ti, the fifth transistor T5 connects the first node N1 to the input terminal of the initialization voltage Vini in response to the first scan signal SCAN1(1). As a result, the first node N1 is initialized to the initialization voltage Vini. The initialization voltage Vini is selected within a voltage range sufficiently lower than the operating voltage of the organic light emitting diode OLED, and may be set equal to or lower than the low potential driving voltage VSS.

In the sampling period Ts, in response to the second scan signal SCAN2( 1 ), the first transistor T1 , the second transistor T2 , and the sixth transistor T6 are turned on. As a result, the first transistor T1 diode-connects the first node N1 and the second node N2. The second transistor T2 charges the data voltage Vdata supplied from the data line DL to the third node N3. The sixth transistor T6 charges the initialization voltage Vini to the fourth node N4.

In the sampling period Ts, a current Ids flows between the source and the drain of the driving transistor DT, and accordingly, the voltage of the third node N3 is changed from the data voltage Vdata to the threshold voltage of the driving transistor DT. It becomes a value (Vdata(n)-|Vth|) obtained by subtracting the absolute value of (Vth). The first node N1 has the same voltage as the second node N2.

In the emission period Te, the third transistor T3 supplies the high potential driving voltage VDD to the third node N3 in response to the emission signal EM( 1 ). Then, the fourth transistor T4 is turned on, so that the second node N2 and the fourth node N4 are connected. In the emission period Te, a current passing through the second node N2 from the third node N3 is generated according to the voltage set between the gate and the source of the driving transistor DT.

The relational expression for the driving current Ioled flowing through the organic light emitting diode OLED in the emission period Te is expressed as Equation 1 below.

[Equation 1]

I _OLED =k/2(Vsg-|Vth|) ² = k/2(Vs-Vg-Vth) ² = k/2{VDD-(Vdata-|Vth|) -Vth)}

[Equation 1] is eventually summarized as "k/2(VDD-Vdata) ^{2 ".}

In Equation 1, k/2 represents a proportional constant determined by electron mobility, parasitic capacitance, and channel capacity of the driving transistor DT. Consequently, during the light emission period Te, the driving current flowing through the organic light emitting diode OLED is not affected by the threshold voltage Vth of the driving transistor DT.

FIG. 5 is a diagram illustrating the configuration of the first scan driver shown in FIG. 2 .

Referring to FIG. 5 , the first scan driver SD1 includes first and second pull-up transistors Tpu1 and Tpu2, first and second pull-down transistors Tpd1 and Tpd2, and first to fifth transistors T1 to T5. ), and first and second node control transistors Ta and Tb.

The first pull-up transistor Tpu1 includes a gate electrode connected to the node BST1 , a drain electrode connected to the first output terminal Nout1 , and a source electrode connected to the first clock input terminal CLKP1 . The first pull-up transistor Tpu1 outputs a first scan signal SCAN1( 1 ) according to the scan clock applied to the first clock input terminal CLKP1 in response to the BST1 node voltage.

The second pull-up transistor Tpu2 includes a gate electrode connected to the node BST2 , a drain electrode connected to the second output terminal Nout2 , and a source electrode connected to the first clock input terminal CLKP1 . The second pull-up transistor Tpu2 outputs the second scan signal SCAN2( 1 ) according to the scan clock applied to the second clock input terminal CLKP2 in response to the BST2 node voltage.

The first pull-down transistor Tpd1 includes a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the high potential voltage VGH, and a source electrode connected to the first output terminal Nout1 . The first pull-down transistor Tpd1 charges the first output terminal Nout1 to a turn-off voltage in response to the QB node voltage.

The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a drain electrode connected to the input terminal of the high potential voltage VGH, and a source electrode connected to the second output terminal Nout2 . The second pull-down transistor Tpd2 charges the second output terminal Nout2 to a turn-off voltage in response to the QB node voltage.

The first transistor T1 includes a gate electrode connected to the start signal input terminal VP, a drain electrode connected to the Q node, and a source electrode connected to the input terminal of the low potential voltage VGL. The start signal input terminal VP receives a start pulse VST or a carry signal. As the carry signal, the n−1 th first scan signal SCAN1(n−1) may be used. The first transistor T1 precharges the Q node in response to the voltage of the start signal input terminal VP.

The second transistor T2 includes a gate electrode connected to the reset clock input terminal RP, a drain electrode connected to the QB node, and a source electrode connected to the input terminal of the low potential voltage VGL. The second transistor T2 discharges the QB node to the low potential voltage VSS in response to the reset clock RCLK.

The third transistor T3 includes a gate electrode connected to the QB node, a source electrode connected to the Q node, and a drain electrode connected to the input terminal of the high potential voltage VGH. The third transistor T3 charges the Q node to the high potential voltage VGH in response to the QB node voltage.

The fourth transistor T4 is a gate electrode connected to the start signal input terminal VP. It includes a source electrode connected to the QB node and a drain electrode connected to an input terminal of the high potential voltage VGH. The fifth transistor T5 charges the QB node to the high potential voltage VGH in response to the start signal.

The fifth transistor T5 is a gate electrode connected to the Q node. It includes a source electrode connected to the QB node and a drain electrode connected to an input terminal of the high potential voltage VGH. The sixth transistor T6 charges the QB node to the high potential voltage VGH in response to the Q node voltage.

The first node control transistor Ta includes a gate electrode connected to the input terminal of the low potential voltage VGL, a drain electrode connected to the Q node, and a source electrode connected to the BST1 node.

The second node control transistor Tb includes a gate electrode connected to the input terminal of the low potential voltage VGL, a drain electrode connected to the Q node, and a source electrode connected to the BST2 node.

FIG. 6 is a diagram illustrating timings of clocks applied to the scan driver shown in FIG. 5, changes in main node voltage of the scan driver, and output of the scan driver according to the timing of the clocks shown in FIG. FIG. 7 is a diagram illustrating voltage changes of the BST1 node and the BST2 node shown in FIG. 5 . In FIG. 6 , the initial period Ti, the sampling period Ts, and the light emission period Te indicate the operation timing of the first scan driver SD1 for driving the first pixel line HL1 . Also, in FIG. 6 , the high potential voltage of the first to fourth scan clocks SCLK1 to SCLK4 may be the gate high voltage VGH, and the low potential voltage may be the gate low voltage VGL. FIGS. 5 to FIG. Referring to 7, the operation of the scan driver according to the present invention is as follows. In particular, an embodiment will be described focusing on the operation of the first scan driver SD1 that generates the first and second scan signals SCAN1 ( 1 ) and SCAN2 ( 1 ).

Before the initial period Ti, the start signal input terminal VP receives the start signal VST. The first transistor T1 precharges the Q node to the first voltage level VL1 that is the low potential voltage VGL in response to the start signal VST. And the first node control transistor Ta precharges the BST1 node to the Q node voltage. While the Q node is the turn-on voltage, the fifth transistor T5 supplies the high potential voltage VGH to the QB node so that the first and second pull-down transistors Tpd1 and Tpd2 are stably turned off. keep

While the start signal VST is applied, the fourth transistor T4 is turned on, and thus the QB node maintains the turn-off voltage of the high potential voltage VGH. As a result, the first and second pull-down transistors Tpd1 and Tpd2 stably maintain a turn-off state. Like the fifth transistor T5 , the fourth transistor T4 suppresses the operations of the first and second pull-down transistors Tpd1 and Tpd2 so that the first and second pull-up transistors Tpu1 and Tpu2 are turned on. - While being turned on, the first and second output terminals Nout1 and Nout2 can stably output scan signals.

In the initial period Ti, the start signal input terminal VP becomes a high level voltage so that the first transistor T1 is turned off, and as a result, the Q node and the BST1 node are in a floating state.

During the initial period Ti, the first scan clock SCLK1 of the low potential voltage VGL is input to the first clock input terminal CLKP1. That is, the voltage level of the source electrode of the first pull-up transistor Tpu1 is lowered from the high potential voltage VGH to the low potential voltage VGL. In the floating state of the BST1 node, the voltage of the BST1 node is bootstrapped from the first voltage level VL1 to the second voltage level VL2 according to the voltage change of the source electrode of the first pull-up transistor Tpu1. The first output terminal Nout1 outputs the first scan signal SCAN1(1) having a turn-on voltage level. The second voltage level VL2 at which the BST1 node is bootstrapped is “VGL-(VGH-VGL)” because the voltage change amount of the source electrode of the first pull-up transistor Tpu1 is reflected.

Since the first node control transistor Ta maintains the turned-off state while the first scan signal SCAN1(1) is output, the BST1 node and the Q node are not electrically connected. As a result, even if the BST1 node is bootstrapped while the first scan signal SCAN1(1) is output, the voltage of the Q node is prevented from being bootstrapped according to the BST1 node. If the voltage of the Q node is bootstrapped and lowered while the first scan signal SCAN1( 1 ) is output, the voltage of the BST2 node may be lowered through the second node control transistor Tb. As a result, the second pull-up transistor Tpu2 is turned on so that the second scan signal SCAN2( 1 ) may be output at an undesired timing through the second output terminal Nout2 .

When the sampling period Ts starts, the first scan clock SCLK1 becomes the high potential voltage VGH, and as a result, the voltage of the first output terminal Nout1 also becomes the high potential voltage VGH.

During the sampling period Ts, the second scan clock SCLK2 is input to the second clock input terminal CLKP2. Similarly to the principle in which the BST1 node is bootstrapped, the BST2 node is bootstrapped while the second pull-up transistor Tpu2 maintains a turn-on voltage. As a result, the second output terminal Nout2 outputs the second scan signal SCAN2(1) having the turn-on voltage level. The BST2 node is bootstrapped to a level similar to the second voltage level VL2 to which the BST1 node is bootstrapped. Meanwhile, the second node control transistor Tb maintains a turned-off state, and as a result, the Q node is prevented from being bootstrapped.

When the light emission period Te starts, the second scan clock SCLK2 becomes the high potential voltage VGH, and as a result, the voltage of the second output terminal Nout2 also becomes the high potential voltage VGH. As a result, during the light emission period Te, the second output terminal Nout2 also becomes the high potential voltage VGH together with the first output terminal Nout1 which becomes the high potential voltage VGH when the sampling period Ts starts.

And when the light emission period Te starts, the third scan clock SCLK3 is applied to the reset clock input terminal RP. In response to the third scan clock SCLK3 , the second transistor T2 supplies the low potential voltage VGL to the QB node. As a result, the third transistor T3 is turned on to charge the Q node to the high potential voltage VGH. In addition, the first and second pull-down transistors Tpd1 and Tpd2 are turned on, and the first and second output terminals Nout1 and Nout2 stably maintain the high potential voltage VGH. That is, the turn-off voltages of the first and second output terminals Nout1 and Nout2 may be stably maintained by the third scan clock SCLK3 applied to the reset clock input terminal RCLK.

As described above, the first scan driver SD1 according to the present invention generates a first scan signal SCAN1(1) and a second scan signal SCAN2(1).

The first scan signal SCAN1(1) is determined by the clock applied to the first clock input terminal CLKP1, and the second scan signal SCAN2(1) is determined by the clock applied to the second clock input terminal CLKP2. is determined by The first scan signal SCAN1 ( 1 ) and the second scan signal SCAN2 ( 1 ) have the same pulse width for one horizontal period ( 1H ), respectively, and differ only in phase. Similarly, the first scan signals SCAN1(i) to the second scan signals SCAN2(i) output by the second scan drivers SD2 to the nth scan drivers SDn each have a pulse width of one horizontal period. (1H) is the same and has a phase difference.

Accordingly, each of the scan drivers SD1 to SDn uses the same scan clocks, but varies the connection relationship between the clocks applied to the first clock input terminal CLKP1 and the second clock input terminal CLKP2 to make the first scan signal SCAN1 (1)) and the second scan signal SCAN2(1) may be output. [Table 1] below is a diagram showing clocks connected to the start signal input terminal VP, the first clock input terminal CLKP1, the second clock input terminal CLKP2, and the reset clock input terminal RP of each scan driver.

VP CLKP1 CLKP2 RCLK SD1 VST SCLK1 SCLK2 SCLK3 SD2 SCAN1(1) SCLK2 SCLK3 SCLK4 SD3 SCAN1(2) SCLK3 SCLK4 SCLK1 SD4 SCAN1(3) SCLK4 SCLK1 SCLK2 SD5 SCAN1(4) SCLK1 SCLK2 SCLK3 SD6 SCAN1(5) SCLK2 SCLK3 SCLK4

6 and [Table 1], clocks applied to each of the scan drivers SD1 to SDn include first scan clocks SCLK1 to fourth scan clocks SCLK4. As shown in [Table 1], the scan clock connected to the first clock input terminal CLKP1 and the scan clock connected to the second clock input terminal CLKP2 of each scan driver have a phase difference of one horizontal period from each other. That is, the scan clocks connected to the first clock input terminal CLKP1 of each of the scan drivers and the scan clocks connected to the second clock input terminal CLKP2 have a phase difference of one horizontal period.

And the reset clock applied to the i-th scan driver SDi (i is a natural number less than “n-2”) is the first clock input terminal CLKP1 of the (i+2)-th scan driver SD(i+2). ) is the same as the scan clock applied to

8 is a diagram illustrating a pixel structure according to the second embodiment, and shows a pixel disposed on an n-th pixel line. FIG. 9 is a diagram illustrating timings of gate signals driving the pixel shown in FIG. 8 .

Referring to FIG. 8 , the pixel according to the second exemplary embodiment includes an organic light emitting diode (OLED), a driving transistor (DT), first to fifth transistors (T1 to T5), and a storage capacitor (Cst).

The organic light emitting diode OLED emits light by a driving current supplied from the driving transistor DT. The anode electrode of the organic light emitting diode OLED is connected to the fifth node N5 , and the cathode electrode is connected to the input terminal of the low potential driving voltage VSS.

The driving transistor DT controls a driving current applied to the organic light emitting diode OLED according to its source-gate voltage Vsg. The gate electrode of the driving transistor DT is connected to the first node N1 , the source electrode is connected to the third node N3 , and the drain electrode is connected to the second node N2 .

The first transistor T1 is connected between the data line DL and the fourth node N4 , and is turned on/off according to the first scan signal SCAN1( 1 ). The gate electrode of the first transistor T1 is connected to the first scan line SL1(1) to which the first scan signal SCAN1(1) is applied, and its source electrode is connected to the data line DL, Its drain electrode is connected to the fourth node N4.

The second transistor T2 is connected between the first node N1 and the second node N2 , and is turned on/off according to the second scan signal SCAN2( 1 ). The gate electrode of the second transistor T2 is connected to the second scan line SL2( 1 ) to which the second scan signal SCAN2( 1 ) is applied, and its source electrode is connected to the second node N2 , and , its drain electrode is connected to the first node N1.

The third transistor T3 is connected between the fourth node N4 and the input terminal of the initial voltage Vinit, and is turned on/off according to the emission signal EM( 1 ). The gate electrode of the third transistor T3 is connected to the emission line EML( 1 ) to which the emission signal EM( 1 ) is applied, and its source electrode is connected to the fourth node N4 , and its The drain electrode is connected to the input terminal of the initial voltage Vinit.

The fourth transistor T4 is connected between the second node N2 and the fifth node N5 , and is turned on/off according to the emission signal EM( 1 ). The gate electrode of the fourth transistor T4 is connected to the emission line EML( 1 ) to which the emission signal EM( 1 ) is applied, and its source electrode is connected to the second node N2 , and its The drain electrode is connected to the fifth node N5.

The fifth transistor T5 is connected between the fifth node N5 and the input terminal of the initial voltage Vinit, and is turned on/off according to the second scan signal SCAN2( 1 ). The gate electrode of the fifth transistor T5 is connected to the second scan line SL2( 1 ) to which the second scan signal SCAN2( 1 ) is applied, and its source electrode is connected to the fifth node N5 , and , its drain electrode is connected to the input terminal of the initial voltage Vinit.

The storage capacitor Cst is connected between the first node N1 and the fourth node N4 . The auxiliary capacitor Cgv is connected between the first node N1 and the third node N3. The third node N3 of the auxiliary capacitor Cgv is connected to the input terminal of the high potential driving voltage VDD, which is a constant voltage source, to prevent the voltage of the gate electrode of the driving transistor DT from being changed due to an unwanted coupling phenomenon. do.

Referring to FIGS. 8 and 9 , driving of a pixel according to the second embodiment is as follows. In particular, the operation of the pixels of the first pixel line HL1 will be examined based on the first scan signal SCAN1( 1 ) and the second scan signal SCAN2( 1 ) output by the first scan driver SD1 . do it with

In the initial period Ti, the second scan signal SCAN2(1) and the emission signal EM(1) are applied at an on level, and the first scan signal SCAN2(1) is applied at an off level. . As a result, the third transistor T3 charges the initialization voltage to the fourth node N4 in response to the emission signal EM( 1 ). The fourth transistor T4 connects the second node N2 and the fifth node N5 in response to the emission signal EM( 1 ). The fifth transistor T5 initializes the fifth node N5 to the initialization voltage Vinit in response to the second scan signal SCAN2( 1 ). As the fourth transistor T4 is turned on, the voltage of the second node N2 becomes the initialization voltage Vini. The second transistor T2 connects the first node N1 and the second node N2 in response to the second scan signal SCAN2( 1 ). Accordingly, the gate electrode and the drain electrode of the driving transistor are in a diode connection state, and the voltage of the first node N1 also becomes the initialization voltage Vini.

In the sampling period Ts, the first scan signal SCAN1 ( 1 ) and the second scan signal SCAN2 ( 1 ) are applied at an on level, and the emission signal EM( 1 ) is applied at an off level . In the sampling period Ts, the third transistor T3 is turned off, and the first transistor T1 is turned on in response to the first scan signal SCAN1(1), so that the fourth node N4 is The data voltage is charged. In addition, the gate electrode and the drain electrode of the driving transistor DT maintain a diode connection state. In the sampling period Ts, the fourth transistor T4 is turned off so that the second node N2 is in a floating state. In addition, the voltage of the second node N2 increases due to the current flowing from the third node N3 to the second node N2 , and accordingly, the voltage of the first node N1 also increases. As the voltage of the first node N1 increases, the Vgs value of the driving transistor DT decreases. In the sampling period, the current flowing from the third node N3 to the second node N2 flows until Vgs of the driving transistor DT becomes equal to the threshold voltage of the driving transistor DT. That is, in the sampling period Ts, the voltages of the first node N1 and the second node N2 are obtained by subtracting the absolute value of the threshold voltage Vth from the high potential driving voltage VDD-|Vth| saturated with

In the emission period Te, the emission signal EM(1) is applied at an on level, and the first scan signal SCAN1(1) and the second scan signal SCAN2(1) are applied at an off level. do. The third transistor T3 applies the initial voltage Vini to the fourth node N4 in response to the emission signal EM( 1 ). As a result, the voltage of the fourth node N4 changes by a value obtained by subtracting the initial voltage Vini from the data voltage Vdata.

Due to the coupling effect, a voltage corresponding to the potential change Vdata-Vinit of the fourth node N4 is reflected to the first node N1 . That is, the voltage of the first node N1 corresponds to a value obtained by subtracting the potential change Vdata-Vinit of the fourth node N4 from the voltage level VDD-|Vth| in the sampling period Ts. VDD-|Vth| -(Vdata-Vinit)".

The fourth transistor T4 connects the second node N2 and the fifth node N5 in response to the emission signal EM( 1 ). At this time, the relational expression for the driving current Ioled flowing through the organic light emitting diode OLED is expressed as Equation 2 below.

[Equation 2]

IOLED=k/2(Vsg-|Vth|)^2 = k/2((Vs-Vg)- |Vth|)^2 = k/2[(VDD-{VDD-|Vth| -(Vdata-Vinit) )}-|Vth|]^2 = k/2(Vdata - Vinit)^2

In Equation 2, k/2 indicates a proportional constant determined by electron mobility, parasitic capacitance, and channel capacitance of the driving transistor DT. As can be seen from Equation 2, the threshold voltage Vth component of the driving transistor DT in the relational expression of the driving current Ioled is erased. Through this, the influence of the threshold voltage Vth change on the driving current Ioled is removed.

The first scan signal SCAN1 ( 1 ) and the second scan signal SCAN2 ( 1 ) for driving the pixel structure according to the second embodiment may be generated using the scan driver illustrated in FIG. 5 . However, since the pulse widths of the first scan signals SCAN1 ( 1 ) and the second scan signals SCAN2 ( 1 ) according to the second embodiment are different, the first clock input terminal CLKP1 and the second clock input terminal CLKP2 are different. ), the clocks applied to each other are different. That is, the pulse width of each of the first scan 1 clock CLK1_SCAN1 to fourth scan 1 clock CLK4_SCAN1 applied to the first clock input terminal CLKP1 is one horizontal period 1H, and the second clock input terminal CLKP2 has a pulse width. A pulse width of each of the first scan 2 clocks CLK1_SCAN2 to fourth scan 2 clocks CLK4_SCAN2 applied to is 2 horizontal periods (2H).

10 is a diagram illustrating clocks for generating scan signals and voltage changes of important nodes according to the second embodiment, and [Table 2] is a table showing clocks applied to each scan driver.

VP CLKP1 CLKP2 RCLK SD1 VST CLK1_SCAN1 CLK1_SCAN2 CLK3_SCAN2 SD2 SCAN2(1) CLK2_SCAN1 CLK2_SCAN2 CLK4_SCAN2 SD3 SCAN2(2) CLK3_SCAN1 CLK3_SCAN2 CLK1_SCAN2 SD4 SCAN2(3) CLK4_SCAN1 CLK4_SCAN2 CLK2_SCAN2 SD5 SCAN2(4) CLK1_SCAN1 CLK1_SCAN2 CLK3_SCAN2 SD6 SCAN2(5) CLK2_SCAN1 CLK2_SCAN2 CLK4_SCAN2

In FIG. 10 , the initial period Ti, the sampling period Ts, and the emission period Te indicate the operation timing of the first scan driver SD1 for driving the first pixel line HL1 . Also, in FIG. 10 , the high potential voltage of the first scan 1 clock CLK1_SCAN1 to the fourth scan 1 clock CLK4_SCAN1 and the first scan 2 clock CLK1_SCAN2 to the fourth scan 2 clock CLK4_SCAN2 is the gate high voltage ( VGH), and the low potential voltage may use the gate low voltage VGL. 5 and 10, an operation of the scan driver for outputting scan signals according to the second embodiment will be described as follows. In particular, an embodiment will be described focusing on the operation of the first scan driver SD1 that generates the first and second scan signals SCAN1 ( 1 ) and SCAN2 ( 1 ).

During the precharge period Tpre, the start signal input terminal VP receives the start signal VST. The precharge period Tpre may be defined as a period from when the start signal VST is applied to after one horizontal period 1H, and corresponds to the last horizontal period of the light emission period Te. During the precharge period Tpre, the first transistor T1 precharges the Q node to the first voltage level VL1 that is the low potential voltage VGL in response to the start signal VST. And the first node control transistor Ta precharges the BST1 node to the Q node voltage. While the Q node is the turn-on voltage, the fifth transistor T5 supplies the high potential voltage VGH to the QB node so that the first and second pull-down transistors Tpd1 and Tpd2 are stably turned off. keep

During the precharge period Tpre, since the Q node is precharged to the low potential voltage VGL and the gate voltages of the first and second node control transistors Ta and Tb are the low potential voltage VGL, the first and the second node control transistors Ta and Tb are at the turn-off state level. As a result, the Q node, the BST1 node, and the BST2 node are in a floating state. During the precharge period Tpre, the voltages of the BST1 node and the BST2 node become the low potential voltage VGL, and the first and second clock input terminals ( The voltages of CLKP1 and CLKP2 are high potential voltages (VGH). That is, Vgs of the first and second pull-up transistors Tpu1 and Tpu2 is equal to or greater than the turn-on voltage. However, the voltage of the first and second output terminals Nout1 and Nout2 connected to the drain electrodes of the first and second pull-up transistors Tpu1 and Tpu2 is the high potential voltage VGH at the same level as the voltage of the source electrode. Therefore, no current flows between the source electrode and the drain electrode of the first and second pull-up transistors Tpu1 and Tpu2 .

During the initial period Ti, the first scan second clock CLK1_SCAN2 of the low potential voltage VGL is input to the second clock input terminal CLKP2. That is, the voltage level of the source electrode of the second pull-up transistor Tpu2 is lowered from the high potential voltage VGH to the low potential voltage VGL. In the floating state of the BST2 node, the voltage of the BST2 node is bootstrapping from the first voltage level VL1 to the second voltage level VL2 according to the voltage change of the source electrode of the second pull-up transistor Tpu2, The second output terminal Nout2 outputs a second scan signal SCAN2(1) having a turn-on voltage level. The second voltage level VL2 at which the BST2 node is bootstrapped is “VGL-(VGH-VGL)” because the voltage change amount of the source electrode of the second pull-up transistor Tpu2 is reflected. As such, since the voltage of the gate electrode of the second pull-up transistor Tpu2 is also bootstrapped while the first scan second clock CLK1_SCAN2 of the low potential voltage VGL is applied, Vgs of the second pull-up transistor Tpu2 is Maintain turn-on voltage.

Since the second node control transistor Tb maintains the turned-off state while the second scan signal SCAN2(1) is output, the BST2 node and the Q node are not electrically connected. As a result, even if the BST2 node is bootstrapped while the second scan signal SCAN2(1) is output, the voltage of the Q node is prevented from being bootstrapped according to the BST2 node. Accordingly, when the Q node is lowered to the second voltage level, the operational reliability of the transistors connected to the Q node is prevented from being deteriorated.

Meanwhile, while the start signal VST is applied, the fourth transistor T4 is turned on, so that the QB node is in a high potential voltage VGH state, which is a turn-off voltage. As a result, the first and second pull-down transistors Tpd1 and Tpd2 stably maintain a turn-off state. As such, the fourth and fifth transistors T4 and T5 suppress the operations of the first and second pull-down transistors Tpd1 and Tpd2 so that the first and second pull-up transistors Tpu1 and Tpu2 are turned on. During the operation, the first and second output terminals Nout1 and Nout2 can stably output the scan signals SCAN1 ( 1 ) and SCAN2 ( 1 ).

During the sampling period Ts, the first scan 1 clock CLK1_SCAN1 is input to the first clock input terminal CLKP1. Similarly to the principle that the BST2 node is bootstrapped, the BST1 node is bootstrapped while the first pull-up transistor Tpu1 maintains a turn-on voltage. In addition, the first output terminal Nout1 becomes a low potential voltage VGL by the first scan 1 clock CLK1_SCAN1 of the low potential voltage VGL applied to the first clock input terminal CLKP1, so that the first output terminal Nout1 becomes the first voltage level of the turn-on voltage level. One scan signal SCAN1(1) is output. While the first scan signal SCAN1 ( 1 ) is output, the first node control transistor Ta maintains a turned-off state, and as a result, the Q node is prevented from being bootstrapped.

When the light emission period Te starts, the first scan first clock CLK1_SCAN1 and the first scan second clock CLK1_SCAN2 become the high potential voltage VGH, and as a result, the first and second output terminals Nout1 and Nout2 The voltage becomes a high potential voltage (VGH). As a result, during the light emission period Te, the second output terminal Nout2 also becomes the high potential voltage VGH together with the first output terminal Nout1 which becomes the high potential voltage VGH when the sampling period Ts starts.

And when the light emission period Te starts, the third scan 2 clock CLK3_SCAN2 is applied to the reset clock input terminal RP. In response to the third scan second clock CLK3_SCAN2 , the second transistor T2 supplies the low potential voltage VGL to the QB node. As a result, the third transistor T3 is turned on to charge the Q node to the high potential voltage VGH. In addition, the first and second pull-down transistors Tpd1 and Tpd2 are turned on, and the first and second output terminals Nout1 and Nout2 stably maintain the high potential voltage VGH. Also, as the Q node becomes the high potential voltage VGH, the BST1 node and the BST2 node become the high potential voltage VGH, and as a result, the first and second pull-up transistors Tpu1 and Tpu2 are turned off. .

As described above, the turn-off voltages of the first and second output terminals Nout1 and Nout2 may be stably maintained by the third scan second clock CLK3_SCAN2 applied to the reset clock input terminal RCLK.

As described above, the first scan driver SD1 generates a first scan signal SCAN1(1) and a second scan signal SCAN2(1). In addition, the second to nth scan drivers SD2 to SDn operate in the same manner as the above-described first scan driver SD1 , but clock signals for controlling the operation timing are different.

Clocks applied to each of the scan drivers SD1 to SDn are shown in [Table 2]. That is, the first scan1 clock CLK1_SCAN1 to the fourth scan1 clock CLK4_SCAN1 for generating the first scan signal SCAN1( 1 ) are applied to the first clock input terminal CLKP1 . In addition, the first scan second clock CLK1_SCAN2 to fourth scan second clock CLK4_SCAN2 for generating the second scan signal SCAN2( 1 ) are applied to the second clock input terminal CLKP2 .

And, the reset clock RCLK applied to the i-th scan driver SDi (i is a natural number less than “n-2”) is the second of the (i+2)-th scan driver SD(i+2). It is the same as the scan 2 clock applied to the clock input terminal.

Those skilled in the art through the above description will be able to make various changes and modifications without departing from the technical spirit of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: timing controller
120: data driving circuit 130, 140: gate driving circuit
EMD1 to EMDn: Emission driver SD1 to SDn: Scan driver

Claims (11)

a display panel in which pixels are disposed on each of the first to nth pixel lines; and
a shift register for supplying scan signals to first and second scan lines connected to each of the pixels;
The shift register includes first to nth (n is a natural number) scan drivers that are dependently connected to each other,
The i-th (i is a natural number less than or equal to "n-2") scan driver
a first scan signal supplied to the first scan line connected to the pixels of the i-th pixel line; and
generating a second scan signal supplied to the second scan line connected to the pixels of the i-th pixel line;
a first transistor precharging the Q node in response to the start signal;
a first pull-up transistor configured to output the first scan signal through a first output terminal using a clock signal received from a first clock input terminal in a state in which the Q node is precharged; and
and a second pull-up transistor configured to output the second scan signal through a second output terminal using a clock signal provided from a second clock input terminal in a state in which the Q node is precharged.
delete The method of claim 1,
a gate electrode of the first pull-up transistor is connected to a node BST1, a gate electrode of the second pull-up transistor is connected to a node BST2;
The i-th scan driver is
a first node control transistor comprising a gate electrode connected to an input terminal of a low potential voltage, a drain electrode connected to the Q node, and a source electrode connected to the BST1 node; and
The display device further comprising a second node control transistor comprising a gate electrode connected to an input terminal of a low potential voltage, a drain electrode connected to the Q node, and a source electrode connected to the BST2 node.
4. The method of claim 3,
The BST1 node is in a floating state as the first transistor is turned off, and bootstrapped when a clock signal is applied to the first clock input terminal,
The BST2 node is in a floating state as the first transistor is turned off, and is bootstrapped when a clock signal is applied to the second clock input terminal.
5. The method of claim 4,
The first clock input terminal receives any one scan clock from among the first to fourth scan clocks,
The second clock input terminal receives any one scan clock from among the first to fourth scan clocks,
A display device having a phase difference between the scan clock input to the first clock input terminal and the scan clock clock input to the second clock input terminal by one horizontal period.
6. The method of claim 5,
a first pull-down transistor including a gate electrode connected to a QB node having a potential opposite to the Q node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the first output terminal; and
a second pull-down transistor including a gate electrode connected to the QB node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the second output terminal;
A second transistor comprising a gate electrode connected to a reset clock input terminal, a drain electrode connected to the QB node, and a source electrode connected to the low potential voltage input terminal;
The reset clock applied to the i-th scan driver is the same as the scan clock applied to the first clock input terminal of the (i+2)-th scan driver.
5. The method of claim 4,
The first clock input terminal receives any one scan clock from among the first to fourth scan 1 clocks,
The second clock input terminal receives any one scan clock from among the first to fourth scan 2 clocks,
A pulse width of each of the first to fourth scan 1 clocks is one horizontal period,
The pulse width of each of the first to fourth scan 2 clocks is 2 horizontal periods, and the scan 2 clock applied to the second clock input terminal of the i-th scan driver is applied to the first clock input terminal of the i-th scan driver. A display device that overlaps one scan clock and one horizontal period.
8. The method of claim 7,
a first pull-down transistor including a gate electrode connected to the QB node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the first output terminal; and
a second pull-down transistor including a gate electrode connected to the QB node, a drain electrode connected to an input terminal of a high potential voltage, and a source electrode connected to the second output terminal;
A second transistor comprising a gate electrode connected to a reset clock input terminal, a drain electrode connected to the QB node, and a source electrode connected to the low potential voltage input terminal;
The reset clock applied to the i-th scan driver is the same as the scan-2 clock applied to the second clock input terminal of the (i+2)-th scan driver.
A shift register comprising: a plurality of scan drivers for supplying a first scan signal and a second scan signal to first and second scan lines connected to each of the pixels, the plurality of scan drivers cascadingly connected to each other, the shift register comprising:
Each of the scan drivers
a first transistor to precharge the Q node in response to the start signal;
first and second node control transistors that are turned on when the Q node is precharged to precharge the BST1 node and the BST2 node, respectively, and are turned off after a predetermined period of time to float the BST1 node and the BST2 node, respectively;
a first pull-up transistor configured to output the first scan signal while bootstrapping the BST1 node according to a scan clock applied to a first clock input terminal; and
and a second pull-up transistor configured to output the second scan signal while bootstrapping the BST2 node according to a scan clock applied to a second clock input terminal.
10. The method of claim 9,
After the first transistor is turned off, the Q node and the BST1 node and the BST2 node are in a floating state,
The BST1 node is a shift register that is bootstrapped according to a scan clock input after the first transistor is turned off.
10. The method of claim 9,
the first node control transistor is connected between the BST1 node and the Q node, and a gate electrode is connected to an input terminal of a low potential voltage;
the second node control transistor is connected between the BST2 node and the Q node, and a gate electrode is connected to an input terminal of a low potential voltage;
The first and second node control transistors are shift registers that are turned off when the Q node is precharged.

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