KR102426423B1 - Display substrate and Liquid crystal display apparatus including the same - Google Patents

Abstract

An embodiment of the present invention includes a transistor disposed on a base substrate and a storage capacitor electrically connected to the transistor, the transistor comprising a gate electrode, an active layer electrically insulated from the gate electrode and including a semiconductor material, and the a first electrode and a second electrode disposed on an active layer spaced apart from each other, wherein the storage capacitor is electrically connected to a lower electrode including a light inflow path and the second electrode, Disclosed is a thin film transistor array substrate including an upper electrode disposed to face the electrode.

Description

Thin film transistor array substrate and liquid crystal display apparatus including the same

Embodiments of the present invention relate to a thin film transistor array substrate and a liquid crystal display including the same, and more particularly, to a thin film transistor array substrate including an active capacitor and a liquid crystal display including the same.

With the development of various electronic devices such as cell phones, PDAs, computers, and large TVs, the demand for flat panel display devices applicable thereto is increasing. Among flat panel displays, a liquid crystal display (LCD) has advantages such as low power consumption, easy video display, and high contrast ratio.

A liquid crystal display device includes a liquid crystal layer disposed between two display substrates, and by applying an electric field to the liquid crystal layer, the arrangement direction of liquid crystal molecules is changed to change the polarization of incident light. By controlling whether or not the image is displayed.

The liquid crystal display includes a display substrate on which a gate line, a data line, a thin film transistor, a capacitor, and the like, intersecting each other are disposed. The data voltage is charged to the pixel electrode through the thin film transistor. The arrangement state of the liquid crystal layer is determined by an electric field formed between the voltage charged to the pixel electrode and the common voltage applied to the common electrode, and the data voltage may be applied with different polarities for each frame.

The voltage applied to the pixel electrode may have a different value from the data voltage by the liquid crystal capacitor and/or the parasitic capacitor, and this voltage difference is referred to as a kickback voltage.

The value of the kickback voltage is changed by a change in capacitance of the storage capacitor, the liquid crystal capacitor, and/or the parasitic capacitor, and thus the voltage applied to the pixel electrode is changed. Due to the difference in luminance due to the voltage deviation of the pixel electrodes, there are problems in that vertical stripes, flicker defects, and afterimages are generated in an image implemented in the liquid crystal display.

In particular, when the storage capacitor is an active capacitor including a semiconductor material, the capacity of the storage capacitor is changed according to voltage and frequency, which causes a problem in that the kickback voltage is changed.

SUMMARY OF THE INVENTION The present invention is to solve various problems including the above problems, and a liquid crystal display device in which vertical streaks, flicker defects, and afterimages that may occur in an image implemented by minimizing a change in capacity of a storage capacitor are improved aims to provide However, these problems are exemplary, and the scope of the present invention is not limited thereto.

An embodiment of the present invention includes a transistor disposed on a base substrate and a storage capacitor electrically connected to the transistor, the transistor comprising a gate electrode, an active layer electrically insulated from the gate electrode and including a semiconductor material, and the a first electrode and a second electrode disposed on an active layer spaced apart from each other, wherein the storage capacitor is electrically connected to a lower electrode including a light inflow path and the second electrode, Disclosed is a thin film transistor array substrate including an upper electrode disposed to face the electrode.

In an embodiment, a dielectric layer disposed between the lower electrode and the upper electrode may be further included, and the dielectric layer may include an insulating layer and a semiconductor layer sequentially disposed on the lower electrode.

In an embodiment, the insulating layer may include silicon nitride, and the semiconductor layer may include amorphous silicon.

In an embodiment, the upper electrode may include a first layer including doped amorphous silicon, and a second layer disposed on the first layer and including at least one metal layer.

In an embodiment, the light inlet passage may include at least one opening included in the lower electrode.

In an embodiment, the light inlet passage may include at least one groove included in the lower electrode.

In an embodiment, the active layer includes amorphous silicon, the first electrode and the second electrode each include a lower layer including doped amorphous silicon, and an upper layer disposed on the lower layer and including at least one metal layer may include.

In an embodiment, the first electrode and the second electrode may be in direct contact with the active layer, respectively.

In an embodiment, the light inflow path may correspond to an empty space overlapping the upper electrode in plan view and at least partially surrounded by a material constituting the lower electrode.

Another embodiment of the present invention provides a transistor disposed on a base substrate, a storage capacitor electrically connected to the transistor, a pixel electrode electrically connected to the transistor and the storage capacitor, a liquid crystal layer disposed on the pixel electrode, and the a common electrode for applying an electric field to the liquid crystal layer together with a pixel electrode; a first electrode and a second electrode, wherein the storage capacitor includes a lower electrode including a light inflow path, and an upper electrode electrically connected to the second electrode and disposed to face the lower electrode. Disclosed is a liquid crystal display device comprising:

In an embodiment, a dielectric layer disposed between the lower electrode and the upper electrode may be further included, and the dielectric layer may include an insulating layer and a semiconductor layer sequentially disposed on the lower electrode.

In an embodiment, the insulating layer may include silicon nitride, and the semiconductor layer may include amorphous silicon.

In an embodiment, the upper electrode may include a first layer including doped amorphous silicon, and a second layer disposed on the first layer and including at least one metal layer.

In an embodiment, the light inlet passage may include at least one opening included in the lower electrode.

In an embodiment, the light inlet passage may include at least one groove included in the lower electrode.

In one embodiment, the active layer includes amorphous silicon, and the first electrode and the second electrode each include a lower layer including doped amorphous silicon, and an upper layer disposed on the lower layer and including at least one metal layer. may include

In an embodiment, the first electrode and the second electrode may be in direct contact with the active layer, respectively.

In an embodiment, the light inflow path may correspond to an empty space overlapping the upper electrode in plan view and at least partially surrounded by a material constituting the lower electrode.

In an embodiment, the pixel electrode may be electrically connected to the upper electrode, and the common electrode may be disposed to face the pixel electrode with the liquid crystal layer interposed therebetween.

In an embodiment, the base substrate further comprises a backlight unit disposed in a direction opposite to a direction in which the transistor and the storage capacitor are arranged, irradiating light in the direction of the base substrate, the light emitted from the backlight unit Silver may be incident on at least a portion of the semiconductor layer through the light inlet passage.

Other aspects, features and advantages other than those described above will become apparent from the following drawings, claims, and detailed description of the invention.

According to one embodiment of the present invention made as described above, it is possible to provide a liquid crystal display device in which vertical line-shaped stains, flicker defects, and afterimages that may be generated in an image implemented by minimizing a change in capacity of a storage capacitor are improved. have.

Also, since the dielectric layer of the storage capacitor includes a semiconductor layer, a high-capacity storage capacitor may be implemented without increasing an area, and thus a high-resolution liquid crystal display may be realized.

Of course, the scope of the present invention is not limited by these effects.

1 is an equivalent circuit diagram of one pixel included in a liquid crystal display according to an exemplary embodiment.
2 is a plan view schematically illustrating a thin film transistor array substrate according to an embodiment.
FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2 .
4 is a graph illustrating capacitance (C) according to voltage (V) of a storage capacitor included in a thin film transistor array substrate when light is not introduced into the thin film transistor array substrate and when light is introduced into the thin film transistor array substrate according to an exemplary embodiment; .
5A is a plan view schematically illustrating a storage capacitor included in a thin film transistor array substrate according to another exemplary embodiment.
FIG. 5B is a cross-sectional view taken along the line V _b - V _b of FIG. 5A.
6A is a plan view schematically illustrating a storage capacitor included in a thin film transistor array substrate according to another exemplary embodiment.
6B is a cross-sectional view taken along the line VI _b -VI _b of FIG. 6A .
7 is a cross-sectional view schematically illustrating a liquid crystal display device including the thin film transistor array substrate of FIG. 3 .

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense.

In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility that one or more other features or components may be added is not excluded in advance.

In the following embodiments, when it is said that a part such as a film, region, or component is on or on another part, not only when it is directly on the other part, but also another film, region, component, etc. is interposed therebetween. Including cases where there is

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

A liquid crystal display device according to an embodiment includes a plurality of pixels, and the liquid crystal display device has a thin film transistor array substrate on which a thin film transistor for driving each pixel, a capacitor, and wires are disposed, and a thin film transistor array substrate facing the thin film transistor array substrate an upper substrate, and a liquid crystal layer disposed between the thin film transistor array substrate and the upper substrate.

A pixel represents a minimum unit for displaying an image, and the liquid crystal display displays an image through a plurality of pixels.

1 is an equivalent circuit diagram of one pixel included in a liquid crystal display according to an exemplary embodiment.

A liquid crystal display according to an exemplary embodiment includes a display area displaying an image and a peripheral area disposed around the display area. A plurality of pixels is disposed in the display area, and each of the plurality of pixels may be driven by a driving circuit unit and a plurality of wires applying an electrical signal to the driving circuit unit.

Referring to FIG. 1 , the driving circuit unit and the plurality of wires may be disposed on a thin film transistor array substrate included in a liquid crystal display device, and the driving circuit unit includes a thin film transistor Tr and a storage capacitor C _st , and includes a plurality of The wirings apply the data signal Data to the gate line GL _n applying the gate signal Gate to the gate electrode GE of the thin film transistor Tr and the first electrode SE of the thin film transistor Tr. It may include a data line DL _m .

The gate line GL _n and the data line DL _m may extend along directions crossing each other. The liquid crystal display includes a plurality of gate lines GL _n and a plurality of data lines DL _m , and a pixel may be disposed in each region where the gate line GL _n and the data line DL _m intersect.

When a turn-on signal is applied to the gate electrode GE of the thin film transistor Tr, the data signal Data applied to the first electrode SE is transferred to the second electrode DE, and the second electrode DE ) may be electrically connected to the upper electrode 150 ( FIG. 3 ) and the pixel electrode 180 ( FIG. 3 ) of the storage capacitor C _st . That is, the data electrode DE, the upper electrode 150 , and the pixel electrode 180 may be connected to the first node N1 .

The storage capacitor C _st includes an upper electrode 150 and a lower electrode 120 opposite to the upper electrode 150 , and a capacitor voltage V _st is connected to the lower electrode 120 by a capacitor line SL. ) can be approved.

The liquid crystal display device further includes a common electrode 190 ( FIG. 7 ) for applying a common voltage V _com in addition to the pixel electrode 180 to apply an electric field to the liquid crystal included in the liquid crystal display device, and the pixel electrode ( The liquid crystal capacitor C _lc may be formed by overlapping the common electrode 190 with the 180 . In addition, the gate electrode GE and the second electrode DE of the thin film transistor Tr may include overlapping regions on a plane, thereby forming a parasitic capacitor C _gs .

The data voltage corresponding to the image to be implemented applied by the data line DL _m by the parasitic capacitor C _gs and the voltage applied to the pixel electrode 180 may have different values, and the data A difference between the voltage and the voltage applied to the pixel electrode 180 is referred to as a kickback voltage.

When a kickback voltage varies according to an applied data voltage within one pixel or when pixels disposed at different locations have different kickback voltages, flicker and stains may occur in the implemented image.

The storage capacitor C _st according to an embodiment is an active capacitor in which the semiconductor layer 140a ( FIG. 3 ) is disposed between the lower electrode 120 and the upper electrode 150 of the storage capacitor C _st . Also, the capacitance of the active capacitor may vary according to a voltage applied to the lower electrode 120 and/or the upper electrode 150 . This change in capacitance may cause a change in kickback voltage.

In the storage capacitor C _st included in the liquid crystal display according to the exemplary embodiment, the lower electrode 120 includes the light inlet passage LP ( FIG. 3 ), and the capacity change of the storage capacitor C _st through this configuration can be minimized. This will be described later.

According to an embodiment, the first electrode SE and the second electrode DE of the thin film transistor Tr may be a source electrode and a drain electrode, respectively, but the present invention is not limited thereto. According to another embodiment, the liquid crystal display device may include different types of thin film transistors Tr, and in this case, the first electrode and the second electrode may be a drain electrode and a source electrode, respectively.

FIG. 2 is a plan view schematically showing a thin film transistor array substrate according to an embodiment, FIG. 3 is a cross-sectional view taken along line III-III of FIG. 2, and FIG. These are graphs showing the capacitance (C) according to the voltage (V) of the storage capacitor included in the thin film transistor array substrate when light is not introduced and when light is introduced.

2 and 3 , a thin film transistor array substrate Sub1 according to an exemplary embodiment includes a transistor Tr disposed on the base substrate 100 and a storage capacitor C _st electrically connected to the transistor Tr. The transistor Tr includes a gate electrode GE, an active layer 140b electrically insulated from the gate electrode GE and including a semiconductor material, and a first electrode spaced apart from each other on the active layer 140b. (SE) and a second electrode (DE), and the storage capacitor (C _st ) is electrically connected to the lower electrode 120 and the second electrode (DE) including a light inflow path (LP) and may include an upper electrode 150 disposed to face the lower electrode 120 .

The base substrate 100 is made of glass or plastic, and may be divided into a plurality of pixel areas. The plurality of pixel areas may be defined by a gate line GL _n extending in one direction and a data line DL _m extending in a direction crossing the one direction. FIG. 2 illustrates only regions corresponding to a portion of two adjacent pixels, and the liquid crystal display includes a plurality of pixel regions that are the same as or similar to the pixel regions illustrated in FIG. 2 , and an image may be realized therefrom.

A transistor Tr is disposed on one region of the base substrate 100 , and the transistor Tr is formed on the gate electrode GE and the active layer 140b disposed on the gate electrode GE, and the active layer 140b. It may include a first electrode SE and a second electrode DE disposed to be spaced apart from each other. According to an embodiment, the first electrode SE and the second electrode DE may be a source electrode and a drain electrode, respectively.

A gate insulating layer 130b may be disposed between the gate electrode GE and the active layer 140b. According to an embodiment, the active layer 140b may be made of amorphous silicon, and the gate insulating layer 130b may be a single layer or multiple layers made of an inorganic material. According to an embodiment, the gate insulating layer 130b may be a single layer made of silicon nitride (SiN _x ).

A first electrode SE and a second electrode DE having conductivity are disposed on the active layer 140b, and the first electrode SE and the second electrode DE have lower layers SEa and DEa and lower layers, respectively. and upper layers SEb and DEb disposed on SEa and DEa. The active layer 140b includes a region disposed between the first electrode SE and the second electrode DE disposed to be spaced apart from each other, and electrically connects the first electrode SE and the second electrode DE. It can function as a channel with or without connection.

According to an embodiment, the lower layers SEa and DEa of the first electrode SE and the second electrode DE may be amorphous silicon doped with impurities to have conductivity, for example, n ⁺ amorphous silicon. have. The lower layers SEa and DEa of the first electrode SE and the second electrode DE are disposed between the active layer 140b and the first electrode SE/second electrode DE, the active layer 140b and the second electrode DE It may be an ohmic contact layer that reduces a work function difference between the first electrode SE and the second electrode DE. The first electrode SE and the second electrode DE may directly contact the active layer 140b, respectively. That is, the active layer 140b and the lower layers SEa and DEa, and the lower layers SEa and DEa and the upper layers SEb and DEb may be in direct contact.

The upper layers SEb and DEb of the first electrode SE and the second electrode DE may include at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). It may include a metal layer including a material, and according to an embodiment, it may be a double layer composed of titanium (Ti)/copper (Cu) or a triple layer composed of titanium (Ti)/copper (Cu)/titanium (Ti). .

The gate electrode GE may be a region protruding from the gate line GL _n , and may receive a gate signal from the gate line GL _n . The first electrode SE may be a region protruding from the data line DL _m , and may receive a data signal from the data line DL _m . The second electrode DE is disposed to be spaced apart from the first electrode SE with an active layer 140b made of a semiconductor material therebetween, and when a turn-on signal is applied to the gate electrode GE, the first electrode SE ) can receive a data signal.

A storage capacitor C _st is disposed on one region of the base substrate 100 , and the storage capacitor C _st may include a lower electrode 120 and an upper electrode 150 facing the lower electrode 120 . . A buffer layer 110 for planarizing the base substrate 100 and blocking impurities from flowing from the base substrate 100 may be disposed between the base substrate, the transistor Tr, and the storage capacitor C _st .

According to an embodiment, the lower electrode 120 is disposed on the same layer as the gate electrode GE and may be made of the same material, and the upper electrode 150 is the first electrode SE of the transistor Tr. and the second electrode DE and may be disposed on the same layer and made of the same material.

The upper electrode 150 is electrically connected to the second electrode DE of the transistor Tr, and according to an embodiment, the upper electrode 150 may be a region in which the second electrode DE extends.

The upper electrode 150 includes a first layer 151 including amorphous silicon doped with impurities and having conductivity, and a second layer 152 disposed on the first layer 151 and including at least one metal layer. may include According to an embodiment, the first layer 151 may be n ⁺ amorphous silicon, and the second layer 152 may include molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). It includes a metal layer including at least one material selected from the group, and may be a single layer or multiple layers.

A dielectric layer DEL is disposed between the lower electrode 120 and the upper electrode 150 , and it depends on the refractive index of the dielectric layer DEL and the area where the lower electrode 120 and the upper electrode 150 overlap. The capacity of the storage capacitor C _st may be determined. That is, as the refractive index of the dielectric layer DEL increases, the capacity of the storage capacitor C _st increases. By configuring the refractive index of the dielectric layer DEL to be large, the area where the lower electrode 120 and the upper electrode 150 overlap is increased. Even if it is not increased, the capacity of the storage capacitor C _st may be increased.

The capacity of the storage capacitor C _st may occupy about 15% or more of the total capacity of the capacitors included in the liquid crystal display, and the kickback voltage may be about 2.5 V or less.

According to an embodiment, the dielectric layer DEL may include an insulating layer 130a and a semiconductor layer 140a sequentially disposed on the lower electrode 120 . The insulating layer 130a may be a single layer or multiple layers made of an inorganic material, and according to an embodiment, the gate insulating layer 130b may be a single layer made of silicon nitride (SiN _x ). The semiconductor layer 140a may be made of amorphous silicon.

The insulating layer 130a and the semiconductor layer 140a may be regions in which the gate insulating layer 130b and the active layer 140b of the transistor Tr extend, respectively.

The refractive index of amorphous silicon constituting the semiconductor layer 140a is about 3.5 or more, and has a much higher refractive index than that of an inorganic insulating material having a refractive index of about 2.0 or less. Accordingly, since the storage capacitor C _st includes the dielectric layer DEL including the semiconductor layer 140a having a high refractive index, it may have a high capacity in a predetermined space.

However, when the storage capacitor C _st includes the dielectric layer DEL including the semiconductor layer 140a, the capacitance varies according to voltage and frequency. Referring to the graph shown in the upper part of FIG. 4 , it can be seen that the capacity of the storage capacitor C _st changes as the value of the voltage difference applied to the lower electrode 120 and the upper electrode 150 changes. The graph shows the capacity of the storage capacitor C _st measured when light does not flow into the semiconductor layer 140a, that is, in an environment in which light does not exist. As shown in the graph, the change in capacity according to the voltage difference may vary according to the frequency.

Such a change in the capacity of the storage capacitor C _st causes a change in the kickback voltage, and thus a difference between the voltage of the pixel electrode 180 and the applied data voltage is different. However, referring to the graph shown in the lower part of FIG. 4 , it can be seen that when light is introduced into the semiconductor layer 140a, the change in capacitance according to the voltage difference at a frequency of 100 Hz or less is remarkably reduced. In this phenomenon, carriers are generated in the semiconductor layer by the light introduced into the semiconductor layer 140a, and due to this, when the voltage applied to the semiconductor layer 140a is negative, in the semiconductor layer 140a. This may be because the depletion layer is not completely formed. Due to this, the decrease in capacity in the negative voltage difference is reduced, and the change in capacity according to the voltage difference as a whole is reduced.

The light irradiated to the thin film transistor array substrate Sub1 from the backlight unit (FIG. 7, BLU), etc., is disposed between the base substrate 100 and the semiconductor layer 140a and the storage capacitor C _st is the lower electrode 120 . Therefore, it may hardly be incident on the semiconductor layer 140a.

However, according to an embodiment, the lower electrode 120 of the storage capacitor C _st may include a light inflow path (LP) for introducing light into the semiconductor layer 140a. The light inlet passage LP may correspond to an empty space overlapping the upper electrode 150 in plan view and at least partially surrounded by a material constituting the lower electrode 120 . That is, since the material constituting the lower electrode 120 is not disposed in the light inlet passage LP, light irradiated from the backlight unit BLU or the like through the light inlet passage LP may be incident on the semiconductor layer 140a. can

According to an embodiment, the light inlet passage LP may include at least one opening 120a included in the lower electrode 120 . The opening 120a may be disposed under the upper electrode 150 , that is, in a region overlapping the upper electrode 150 in plan view. In FIG. 2 , the number of the openings 120a is plural and the shape of the openings 120a is shown to be a square shape, but the shape and number of the openings 120a is not limited thereto.

The lower electrode 120 may be a region protruding from the capacitor line SL extending in one direction, and a capacitor voltage V _st may be applied to the lower electrode 120 from the capacitor line SL. The capacitor line SL may be disposed on the same layer as the gate line GL _n and may extend in the same direction as the gate line GL _n . A branch portion SL _br extending from the capacitor line SL to a region in which the pixel electrode 180 is disposed in a direction intersecting the one direction may be disposed on the base substrate 100 . At least a portion of the portion SL _br may be disposed to overlap at least a portion of the pixel electrode 180 in a plan view to form a capacitor. The capacitor may constitute a part of the storage capacitor C _st , thereby increasing the capacity of the storage capacitor C _st .

A via insulating layer 160 may be disposed on the base substrate 100 to cover the transistor Tr and the storage capacitor C _st , and may be connected to the transistor Tr and the storage capacitor C _st by the via insulating layer 160 . The step difference may be flattened.

The via insulating layer 160 may include a via hole VIA exposing a portion of the upper electrode 150 of the storage capacitor C _st . A pixel electrode 180 is disposed on the via insulating layer 160 , and the pixel electrode 180 may be connected to the upper electrode 150 through a via hole VIA. The pixel electrode 180 may be disposed to be independent of each of a plurality of pixels included in the liquid crystal display.

FIG. 2 illustrates that the pixel electrode 180 includes a central branch 180a and a minute branch 180b extending from the central branch 180a, but the present invention is not limited thereto and the pixel electrode 180 is not limited thereto. ) can be configured in various shapes such as a square plate shape, a cross shape, and the like.

According to an embodiment, the lower electrode 120 of the storage capacitor C _st includes a light inlet passage LP for irradiating light to the semiconductor layer 140a, through which the lower electrode 120 and the upper electrode A change in capacity of the storage capacitor C _st according to a voltage difference applied to 150 may be minimized.

That is, by minimizing a change in the kickback voltage according to a change in the capacity of the storage capacitor C _st , problems such as vertical stripes, flicker defects, and afterimages that may occur in an image implemented by the liquid crystal display device can be improved

5A is a plan view schematically illustrating a storage capacitor included in a thin film transistor array substrate according to another exemplary embodiment, and FIG. _5B is a cross-sectional view taken along line Vb - Vb of _FIG . 5A . 5A and 5B show modified examples of the storage capacitor C _st included in the thin film transistor array substrate of FIG. 3 .

According to an embodiment, the buffer layer 210 is disposed on the base substrate 200 , and the storage capacitor C _st including the lower electrode 220 and the upper electrode 250 may be disposed on the buffer layer 210 . .

An insulating layer 230a made of silicon nitride (SiN _x ) and a semiconductor layer 240a made of amorphous silicon are disposed on the insulating layer 230a between the lower electrode 220 and the upper electrode 250 ) A dielectric layer DEL including

The semiconductor layer 240a has a high refractive index of about 3.5 or more, and thus a storage capacitor C _st having a high capacity may be implemented.

The upper electrode 250 may include a first layer 251 made of n ⁺ amorphous silicon and a second layer 252 disposed on the first layer 251 and including at least one metal layer.

The lower electrode 220 may include a light inlet passage LP through which the light incident from the base substrate 200 is incident on the semiconductor layer 240a. The light inlet passage LP may include at least one groove 220a included in the lower electrode 220 , and the groove 220a is formed below the upper electrode 250 , that is, the upper electrode 250 and the upper electrode 250 . It may be disposed in an overlapping area on a plane. According to an embodiment, the plurality of grooves 220a may be formed in a rectangular shape from one edge of the lower electrode 220, but the present invention is not limited thereto.

The groove 220a may be formed in the lower electrode 220 in a direction substantially perpendicular to a direction connecting the lower electrode 220 and the upper electrode 250, and therefore, as shown in FIG. 5A , in a plan view When viewed, it may have a finger shape.

The groove 220a may correspond to an empty space surrounded by a material constituting the lower electrode 220, and light irradiated from the backlight unit (BLU, FIG. 7), etc. passes through the groove 220a and the semiconductor layer 240a. ) can be entered.

6A is a plan view schematically illustrating a storage capacitor included in a thin film transistor array substrate according to another exemplary embodiment, and FIG. 6B is a cross-sectional view taken along line VI _b - VI _b of FIG. 6A .

6A and 6B show a modified example of the storage capacitor Cst included in the thin film transistor array substrate of FIG. 3 .

According to an embodiment, the buffer layer 310 is disposed on the base substrate 300 , and the storage capacitor C _st including the lower electrode 320 and the upper electrode 350 may be disposed on the buffer layer 310 . .

Between the lower electrode 320 and the upper electrode 350, the insulating layer 330a made of silicon nitride (SiN _x ) and the insulating layer 330a are disposed on the semiconductor layer 340a made of amorphous silicon. A dielectric layer DEL including

The semiconductor layer 340a has a high refractive index of about 3.5 or more, and thus a storage capacitor C _st having a high capacity may be implemented.

The upper electrode 350 may include a first layer 351 made of n ⁺ amorphous silicon and a second layer 352 disposed on the first layer 351 and including at least one metal layer.

The lower electrode 320 may include a light inlet passage LP through which the light incident from the base substrate 300 is incident on the semiconductor layer 340a. The light inlet passage LP may include at least one opening 320a included in the lower electrode 320 , and the opening 320a is formed below the upper electrode 350 , that is, the upper electrode 350 and the upper electrode 350 . It may be disposed in an overlapping area on a plane. According to an embodiment, the openings 320a may be plural, and each opening 320a may have a circular shape.

The opening 320a may correspond to an empty space surrounded by a material constituting the lower electrode 320 , and light irradiated from a backlight unit (BLU, FIG. 7 ), etc. passes through the opening 320a to pass through the semiconductor layer 340a. ) can be entered.

7 is a cross-sectional view schematically illustrating a liquid crystal display device including the thin film transistor array substrate of FIG. 2 .

Referring to FIG. 7 , a liquid crystal display according to an exemplary embodiment includes a liquid crystal layer LC and a thin film transistor array disposed on the thin film transistor array substrate Sub1 and the thin film transistor array substrate Sub1 of FIGS. 2 and 3 . An upper substrate Sub2 sealing the liquid crystal layer LC together with the substrate Sub may be included.

The liquid crystal display includes a transistor Tr disposed on the base substrate 100 , a storage capacitor C _st electrically connected to the transistor Tr , a transistor Tr , and a pixel electrically connected to the storage capacitor C _st . The electrode 180 , the liquid crystal layer LC disposed on the pixel electrode 180 , and the pixel electrode 180 may include a common electrode 190 applying an electric field to the liquid crystal layer LC.

According to an embodiment, the common electrode 190 may be disposed to face the pixel electrode 180 with the liquid crystal layer LC interposed therebetween. That is, the common electrode 190 may be disposed on a surface of the upper substrate Sub2 opposite to the pixel electrode 180 . In this case, an electric field is formed in a vertical direction by different voltages applied to the pixel electrode 180 and the common electrode 190 , and thus liquid crystals included in the liquid crystal layer LC may be aligned.

However, the present invention is not limited thereto, and the common electrode 190 may be disposed on the thin film transistor array substrate Sub1 to be insulated from the pixel electrode 180 . In this case, an electric field is formed in a horizontal direction between the common electrode 190 and the pixel electrode 180 , and thus liquid crystals included in the liquid crystal layer LC may be aligned. That is, the pixel electrode 180 and the common electrode 190 may be arranged in various shapes according to a driving mode of the liquid crystal display.

Although not shown, the liquid crystal display has an alignment layer (not shown) on the upper and lower portions of the liquid crystal layer LC that determines the alignment direction of the liquid crystal material included in the liquid crystal layer LC in a state where an electric field is not applied to the liquid crystal layer LC. city) can be placed.

The liquid crystal display implements an image in the direction of the upper substrate Sub2 , and is disposed in a direction opposite to the direction in which the transistor TR and the storage capacitor C _st of the base substrate 100 are arranged, the base substrate 100 . A backlight unit (BLU) for irradiating light in a direction may be further included. The light emitted from the backlight unit BLU may pass through the light introduction path LP included in the lower electrode 120 of the storage capacitor C _st and be incident on at least a portion of the semiconductor layer 140a.

The transistor Tr includes a gate electrode GE, an active layer 140b electrically insulated from the gate electrode GE and including a semiconductor material, a first electrode SE spaced apart from each other on the active layer 140b, and The second electrode DE is included, and the storage capacitor C _st is electrically connected to the lower electrode 120 including the light inlet passage LP and the second electrode DE and faces the lower electrode 120 . It may include an upper electrode 150 disposed to do so.

Components included in the thin film transistor array substrate Sub1 have been described in detail in the description of FIGS. 2 and 3 , and thus will be omitted herein.

In FIG. 7 , the storage capacitor C _st included in the thin film transistor array substrate Sub1 has the shape of FIGS. 2 and 3 , but the storage capacitor C _st has the shape of FIG. 5A or 6A . may have

In the thin film transistor array substrate Sub1 and the liquid crystal display including the same according to an embodiment of the present invention made as described above, the semiconductor layers 140a, 240a, 340a are formed on the dielectric layer DEL of the storage capacitor C _st . By disposing , a high-capacity storage capacitor Cst can be implemented without an increase in area, and thus a high-resolution liquid crystal display can be realized.

In addition, by including the light inlet passage LP in the lower electrodes 120 , 220 , 320 of the storage capacitor C _st , the change in capacity of the storage capacitor C _st is minimized to form a vertical line that may occur in an image implemented. It is possible to improve stains, flicker defects, and afterimages.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

Sub1: thin film transistor array substrate
Sub2: upper substrate BLU: backlight unit
LP: light inlet passage 100, 200, 300: base substrate
110, 210, 310: buffer layer 120, 220, 320: lower electrode
120a, 320a: opening 220a: groove
130a, 230a, 330a: insulating layer 130b: gate insulating film
140a, 240a, 340a: semiconductor layer 140b: active layer
150, 250, 350: upper electrode 151, 251, 351: first layer
152, 252, 352: second layer 160: via insulating film
180: pixel electrode 190: common electrode

Claims (20)

A transistor disposed on a base substrate, the transistor including a gate electrode, an active layer electrically insulated from the gate electrode and including a semiconductor material, and first and second electrodes spaced apart from each other on the active layer;
The storage capacitor is electrically connected to the transistor and includes a lower electrode including a light inflow path, and an upper electrode integrally connected to the second electrode and disposed to face the lower electrode. ;
a capacitor line extending in a first direction and integrally connected to the lower electrode;
first and second branches integrally connected to the capacitor line and extending from the capacitor line in a second direction intersecting the first direction and spaced apart from each other in the first direction;
the dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including an insulating layer disposed on the lower electrode and a semiconductor layer disposed on the insulating layer and integrally connected to the active layer;
a via insulating layer disposed on the transistor and the storage capacitor and having a via hole exposing a portion of the upper electrode of the storage capacitor; and
a first pixel electrode disposed on the via insulating layer and connected to the upper electrode of the storage capacitor through the via hole; and
In a plan view, the first pixel electrode is disposed between the first branch and the second branch, and at least a portion of the first pixel electrode includes the capacitor line, the first branch, and the second branch. A thin film transistor array substrate surrounded by The method of claim 1,
a gate line extending in the first direction and integrally connected to the gate electrode; and
a second pixel electrode spaced apart from the first pixel electrode in the second direction;
In a plan view, the gate line partially overlaps an edge of the second pixel electrode. The method of claim 1,
The thin film transistor array substrate, wherein the insulating layer comprises silicon nitride (silicon nitride), the semiconductor layer comprises amorphous silicon (amorphous silicon). The method of claim 1,
The upper electrode is
a first layer comprising doped amorphous silicon; and
A thin film transistor array substrate including; a second layer disposed on the first layer and including at least one metal layer. The method of claim 1,
The light inlet passage includes at least one opening included in the lower electrode, the thin film transistor array substrate. The method of claim 1,
The light inlet passage includes at least one groove included in the lower electrode, the thin film transistor array substrate. The method of claim 1,
The active layer includes amorphous silicon,
The first electrode and the second electrode each include a lower layer comprising doped amorphous silicon, and an upper layer disposed on the lower layer and including at least one metal layer, the thin film transistor array substrate. 8. The method of claim 7,
The first electrode and the second electrode are in direct contact with the active layer, respectively, a thin film transistor array substrate. The method of claim 1,
The light inflow path overlaps the upper electrode in plan view and corresponds to an empty space at least partially surrounded by a material constituting the lower electrode. A transistor disposed on a base substrate, the transistor including a gate electrode, an active layer electrically insulated from the gate electrode and including a semiconductor material, and first and second electrodes spaced apart from each other on the active layer;
The storage capacitor is electrically connected to the transistor and includes a lower electrode including a light inflow path, and an upper electrode integrally connected to the second electrode and disposed to face the lower electrode. ;
a capacitor line extending in a first direction and integrally connected to the lower electrode;
first and second branches integrally connected to the capacitor line and extending from the capacitor line in a second direction intersecting the first direction and spaced apart from each other in the first direction;
the dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including an insulating layer disposed on the lower electrode and a semiconductor layer disposed on the insulating layer and integrally connected to the active layer;
a via insulating layer disposed on the transistor and the storage capacitor and having a via hole exposing a portion of the upper electrode of the storage capacitor;
a first pixel electrode disposed on the via insulating layer and connected to the upper electrode of the storage capacitor through the via hole;
a liquid crystal layer disposed on the first pixel electrode; and
a common electrode for applying an electric field to the liquid crystal layer together with the first pixel electrode;
In a plan view, the first pixel electrode is disposed between the first branch and the second branch, and at least a portion of the first pixel electrode includes the capacitor line, the first branch, and the second branch. surrounded by, liquid crystal display. 11. The method of claim 10,
a gate line extending in the first direction and integrally connected to the gate electrode; and
a second pixel electrode spaced apart from the first pixel electrode in the second direction;
In a plan view, the gate line partially overlaps an edge of the second pixel electrode. 11. The method of claim 10,
The insulating layer includes silicon nitride and the semiconductor layer includes amorphous silicon. 11. The method of claim 10,
The upper electrode is
a first layer comprising doped amorphous silicon; and
and a second layer disposed on the first layer and including at least one metal layer. 11. The method of claim 10,
The light inlet passage includes at least one opening included in the lower electrode. 11. The method of claim 10,
The light inlet passage includes at least one groove included in the lower electrode. 11. The method of claim 10,
The active layer includes amorphous silicon,
The first and second electrodes each include a lower layer including doped amorphous silicon, and an upper layer disposed on the lower layer and including at least one metal layer. 17. The method of claim 16,
The first electrode and the second electrode are in direct contact with the active layer, respectively. 11. The method of claim 10,
The light inflow path corresponds to an empty space overlapping the upper electrode in plan view and at least a portion of which is surrounded by a material constituting the lower electrode. 11. The method of claim 10,
and the common electrode is disposed to face the first pixel electrode with the liquid crystal layer interposed therebetween. 11. The method of claim 10,
and a backlight unit disposed in a direction opposite to a direction in which the transistor and the storage capacitor of the base substrate are arranged and irradiating light in a direction of the base substrate;
The light emitted from the backlight unit passes through the light inlet passage and is incident on at least a portion of the semiconductor layer.

Images