KR102469612B1 - Thin film transistor array substrate, and display device including the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate and a display device using the same, which includes a thin film transistor array disposed on a substrate, a first ground wire connected to the thin film transistor array on the substrate, and the thin film transistor array and a floating wire disposed on the substrate to be separated from the first ground wire.

Description

Thin film transistor array substrate and display device using the same

The present invention relates to a thin film transistor substrate having a floating ground line and a display device using the same.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence device. As an example of an electroluminescence device, an active matrix type organic light emitting display device (hereinafter referred to as “OLED display device”) is commercially available.

An active matrix type display device drives pixels using thin film transistors (hereinafter referred to as “TFTs”) formed for each pixel. When electrostatic discharge (ESD) flows into a display panel of such a display device, pixels or a driving circuit of the display panel may be damaged. Various designs for discharging static electricity are applied to display panels so that static electricity is not applied to pixels. Elements that turn on when static electricity is applied to discharge static electricity are formed on the substrate of the display panel, and are provided as an electrostatic discharge path between the display panel and the case member. However, a circuit of a display panel may be damaged due to static electricity even in a display device having such a design for blocking static electricity.

The present invention provides a TFT array substrate reinforced with an electrostatic blocking structure and a display device using the same.

The TFT array substrate of the present invention comprises a TFT array disposed on a substrate, a first ground wire connected to the TFT array on the substrate, and a floating wire disposed on the substrate to be separated from the TFT array and the first ground wire. provide The floating wire is spaced apart from the TFT array with the first ground wire interposed therebetween.

A distance between the first ground wire and the floating wire is 0.1 mm or more.

The floating wiring is disposed at the outermost part of the substrate.

The TFT array substrate further includes one or more second ground wires disposed between the first ground wire and the floating wire.

The TFT array substrate further includes a bridge pattern connecting the first ground wire and the second ground wire.

A display device of the present invention includes a first substrate including a TFT array, a first ground wire connected to the TFT array, and a floating wire separated from the TFT array and the first ground wire; and a second substrate bonded to the first substrate with a sealant. The floating wire is spaced apart from the TFT array with the first ground wire interposed therebetween.

The second substrate further includes a transparent conductive film disposed on an outer surface of the second substrate.

The display device further includes a plastic case top covering an edge of the display panel including the first and second substrates.

A distance between the first ground wire and the floating wire is 0.1 mm or more, and a distance between the upper transparent conductive layer and the first ground wire is 0.6 mm or more.

The present invention can protect the TFT array from static electricity by lowering the electrostatic voltage below the dielectric breakdown voltage of the substrate by arranging the floating wiring on the electrostatic path.

1 is a diagram showing the structure of a display device according to an embodiment of the present invention.
2 is a diagram showing a display panel driving circuit and an ESD element.
3 is a diagram showing a path through which static electricity is applied to a TFT array of a display panel.
FIG. 4 is a view showing a path through which static electricity flows in a cross-section of the display panel taken along the line A-A' in FIG. 2 .
5 is a plan view showing a TFT array and floating wiring.
FIG. 6 is a cross-sectional view showing an edge structure of the display panel shown in FIG. 5 .
7 is a circuit diagram showing a decrease in static electricity level due to a floating wire.
8 and 9 are diagrams showing the structure of a display panel according to another embodiment of the present invention.
10 is a cross-sectional view showing an example in which a floating wire is covered with a sealant.
11 to 14 are cross-sectional views showing various cross-sectional structures of display panels to which floating wires are applied.

Advantages and features of the present invention, and methods of achieving them, will become clear with reference to the detailed description of the following embodiments taken in conjunction with the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, only the embodiments will make the disclosure of the present invention complete, and those of ordinary skill in the art to which the present invention belongs It is provided to fully inform the scope of the invention, the invention is defined only by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, the present invention is not limited to those shown in the drawings. Like reference numbers designate substantially like elements throughout the specification. In addition, in describing the present invention, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted.

When "comprises", "includes", "has", "consists of", etc. mentioned in this specification is used, other parts may be added unless '~ only' is used. When a component is expressed in the singular, it may be interpreted in the plural unless specifically stated otherwise.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, when a positional relationship between two components is described as 'on ~', 'on top of ~', 'on the bottom of ~', 'next to', etc., ' One or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

Although first, second, etc. may be used to distinguish the components, the function or structure of these components is not limited to the ordinal number or component name attached to the front of the component.

The following embodiments may be partially or wholly combined or combined with each other, and technically various interlocking and driving operations are possible. Each of the embodiments may be implemented independently of each other or together in an association relationship.

In the following embodiments, the display device of the present invention will be described mainly as a liquid crystal display device, but is not limited thereto. For example, the electrostatic blocking reinforcing structure applied to the TFT array substrate of the present invention may be applied to a TFT array substrate of an OLED display device as well as a liquid crystal display device.

The display device of the present invention includes a cover or case member such as a guide panel, a cover bottom, and a case top on a display panel and a backlight unit (BLU). The backlight unit (BLU) may be omitted in a self-light emitting device such as an OLED display device.

1 and 2 , the display device of the present invention includes a display panel 100, a backlight unit (BLU) that radiates light to the display panel 100, and a display panel connected to the display panel 100. A driving circuit and the like are provided.

The display panel driving circuit includes a data driver 200, a gate driver 300, a timing controller 500, a Vcom generator 400, and the like. The display panel driving circuit may further include a touch sensor driving unit (not shown). The touch sensor driver senses each touch input by driving the touch sensors.

The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit. In the case of a self-luminous device, for example, an OLED display device, a backlight unit is not required. The backlight unit shown in FIG. 1 is an example of an edge type backlight unit.

The backlight unit radiates light from the display panel 100 to the display panel 100 using an optical layer. The optical layer includes a light emitting diode assembly (LED assembly) 15, a light guide plate 16, an optical sheet 14, a reflective sheet 18, and the like.

The backlight unit includes an LED assembly 15, a light guide plate 16, and a plurality of optical sheets 14, and transmits light from the LED assembly 15 through the light guide plate 16 and the optical sheets 14. It is converted into a uniform surface light source and irradiates light to the display panel 100 . The LED assembly 15 includes a substrate on which a plurality of light-emitting diodes (LEDs) are mounted. The LED is used as a light source of the backlight unit. The optical sheets 14 include a prism sheet and a diffusion sheet to diffuse light incident through the front surface of the light guide plate 16 and refract the light propagation path at an angle perpendicular to the light incident surface of the display panel 100. let it A reflective sheet 18 for reflecting light is disposed on the rear surface of the light guide plate 16 . A cover bottom 17 is disposed below the light guide plate 16 . The cover bottom 17 may be made of a metal plate.

A guide panel 13 and a case top 11 are assembled to the edge of the display panel 100 . The guide panel 13 supports the display panel 100 under the display panel 100 and covers the side surface of the backlight unit. The case top 11 is a rectangular frame structured to cover the front edge of the display panel 100 and the outer surface of the guide panel 13 . The case top 11 may be fixed to at least one of the guide panel 13 and the cover bottom 17 with a hook or a screw 19 . The case top 11 and the guide panel 13 cover the front edge and side of the display module 10 .

The display panel 100 includes a first substrate and a second substrate facing each other with a liquid crystal layer interposed therebetween. A pixel array displaying an input image is formed in an active area of the display panel 100 . The pixel array includes pixels arranged in a matrix form by crossing data lines DL1 to DLn and gate lines GL1 to GLm. Each of the pixels may be divided into a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel for color implementation. Also, each of the pixels may further include a white (W) sub-pixel. If a rendering algorithm is applied to a pen tile pixel array, one pixel can be implemented with two sub-pixels. The pixels adjust the transmission amount of light using liquid crystal molecules driven by a voltage difference between the pixel electrode 1 charging the data voltage through the TFT and the common electrode 2 to which the common voltage Vcom is applied.

The first substrate 101 of the display panel 100 is a TFT array substrate. The first substrate 101 includes data lines DL1 to DLn, gate lines GL1 to GLm, TFTs disposed on each of the pixels, a pixel electrode 1 connected to the TFT, and a pixel electrode 1. and a TFT array 105 such as a Storage Capacitor (Cst) connected to

The TFTs formed on the first substrate 101 of the display panel 100 may be implemented as an amorphose Si (a-Si) TFT, a Low Temperature Poly Silicon (LTPS) TFT, an oxide TFT (TFT), or the like. The TFTs are formed at intersections of the data lines DL1 to DLn and the gate lines GL1 to GLm. The TFTs supply data voltages from the data lines to the pixel electrodes 1 in response to gate pulses.

The display panel 100 includes a color filter array including a black matrix (BM) and color filters. The color filter array may be formed on the first substrate 101 of the display panel together with the TFT array 105 or may be formed on the second substrate 102 opposing the first substrate 101 with a liquid crystal layer interposed therebetween. have. An upper transparent conductive film 103 for discharging static electricity (ESD) may be formed on an outer surface of the second substrate 102 exposed to a user. The upper transparent conductive film 103, the pixel electrode 1, and the common electrode 2 are formed of a transparent electrode material such as indium-tin oxide (ITO).

The common electrode 2 is formed on the second substrate in the case of vertical electric field driving methods such as TN (Twisted Nematic) mode and VA (Vertical Alignment) mode, and IPS (In-Plane Switching) mode and FFS (Fringe Field Switching) ) mode, it may be formed on the first substrate 101 together with the pixel electrode 1. Setting the pre-tilt angle of the liquid crystal molecules on the surface in contact with the liquid crystal layer with the polarizer attached to the outer surfaces of the first and second substrates 101 and 102 of the display panel 100, respectively. An alignment film is formed for 11 to 14, reference numerals “108” and “109” denote polarizing plates.

Touch sensors may be disposed on the active area of the display panel 100 . The touch sensors may be disposed on the display panel 100 in an on-cell type or an add-on type. The touch sensor driver receives the output signal of the touch sensor, generates coordinates of each of the touch inputs, and transmits them to a host system.

The data driver 200 and the gate driver 300 write data of an input image into pixels under the control of the timing controller 500 . As shown in FIG. 5 , the data driver 200 includes one or more source drive ICs (SICs). The data driver 200 receives digital video data of an input image from the timing controller 500 . The data driver 200 converts digital video data of an input image into a gamma compensation voltage under the control of the timing controller 500 and outputs a data voltage.

The gate driver 300 supplies gate pulses to the gate lines GL1 to GLm under the control of the timing controller 500 . The gate pulse is synchronized with the data voltage supplied to the data lines DL1 to DLn. The gate driver 300 may be directly formed on the lower substrate together with the TFT array. The gate driver 300 may be directly mounted on the first substrate 101 of the display panel 100 together with the pixels. The gate driver 300 sequentially shifts gate pulses applied to the gate lines GL1 to GLm using a shift register. The gate pulse is synchronized with the data voltage of the input image, that is, the pixel voltage, and sequentially selects pixels line by line to be charged with the data voltage.

The Vcom generator 400 generates a common voltage Vcom, compares the common voltage applied to the display panel 100 with a reference common voltage, and compensates for the common voltage Vcom with the difference voltage.

The timing controller 500 transmits data of the input image received from the host system to the data driver 200 . The timing controller 500 receives timing signals synchronized with input image data from the host system 110 . The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a main clock DCLK. The timing controller 500 controls operation timings of the data driver 200 and the gate driver 300 based on the timing signals Vsync, Hsync, DE, and DCLK. The timing controller 500 and the Vcom generator 400 are mounted on a printed circuit board (PCB) as shown in FIG. 5 .

The host system may be implemented as any one of a television system, a home theater system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), and a phone system. Also, the host system may be a system that controls a mobile device or a wearable device. The host system scales the digital video data of the input image according to the resolution of the display panel 100 . The host system transmits timing signals (Vsync, Hsync, DE, CLK) together with digital video data of an input image to the timing controller 500. The host system executes an application associated with coordinate information of a touch input from the touch sensor driver.

As shown in FIG. 2 , the display panel 100 includes a common voltage line 110 connected to the common electrode 2, and a common voltage Vcom connected to the common electrode 2 and applied to the display panel 100, Vcom A common voltage feedback wire 111 input to the generator 400, a first GND wire 130 connected to the TFT array 105, a plurality of ESD elements 112, a floating ground line 150, etc. more includes The metal wires 110 , 120 , 130 , and 140 and the ESD elements 112 are formed in a non-display area outside the active area of the display panel 100 . A GND ground voltage (GND) is supplied to the first GND wire 130 .

The ESD elements 112 include one or more diodes, which are turned on when static electricity (ESD) is generated and flows in through data lines DL1 to DLn and gate lines GL1 to GLm. The overvoltage is discharged through the first GND wire 130 to protect the pixels and the display panel driving circuit from static electricity.

The floating wire 150 is spaced apart from the TFT array 105 with the first GND wire 130 interposed therebetween. The floating wiring 150 is not connected to other components such as the TFT array 105, the display panel driving circuits 200, 300, and 400, other outer wirings 110, 111, and 130, and the ESD device 112. The floating wire 150 lowers the voltage of static electricity applied to the TFT array 105 when static electricity is generated. The floating wiring 150 may be disposed on the outermost side of the first substrate 101 on which the TFT array 105 is disposed, but is not limited thereto.

3 is a diagram showing a path through which static electricity is applied to a TFT array of a display panel. FIG. 4 is a view showing a path through which static electricity flows in a cross-section of the display panel taken along the line A-A' in FIG. 2 .

Referring to FIGS. 3 and 4 , the first and second substrates 101 and 102 of the display panel 100 are bonded with a sealant 104 with the liquid crystal layer Clc interposed therebetween.

Static electricity (ESD) may be applied to the TFT array 105 on the first substrate 101 through the second substrate 102 of the display panel 100 . The case top 11 may be made of non-conductive plastic. In this case, when static electricity (ESD) equal to or higher than the dielectric breakdown voltage of the substrates 101 and 102 is applied to the top transparent conductive film 103, it is not discharged to the outside through the case top 11, and the static electricity (ESD) is applied to the substrates. It may be applied to the pixel array 105 through (101, 102). In Fig. 4, "106" is an insulating film formed on the TFT array.

The floating wiring 150 is disposed on the outermost side of the first substrate 101 as shown in FIGS. 5 to 7 and the first GND wiring 130 connected to the TFT array 105 to reduce the voltage of ESD. The TFT array 105 is protected from static electricity (ESD) by lowering it below the dielectric breakdown voltage of the substrate.

5 is a plan view showing a TFT array and floating wiring. FIG. 6 is a cross-sectional view showing an edge structure of the display panel shown in FIG. 5 . 7 is a circuit diagram showing a decrease in static electricity level due to a floating wire.

5 to 7 , the floating wire 150 is spaced apart from the first GND wire 130 connected to the TFT array 105 on the first substrate 101 at a predetermined interval.

When ESD equal to or higher than the dielectric breakdown voltage of the substrates 101 and 102 is applied to the second substrate 102 , it is applied toward the first substrate 101 through the upper transparent conductive film 103 . Due to the impedance (R1) between the second substrate 102 and the floating wire 150, the voltage of static electricity (ESD) is lowered, and the impedance (R2) between the floating wire 150 and the first GND wire 130 ), the voltage of static electricity (ESD) is further lowered.

The distance between the upper transparent conductive film 103 and the GND wiring, which can protect the TFT array 105 from ESD of 15 kV or more, must be 0.6 mm or more, as can be seen from the calculation results below.

The cell gap (ΔG) of the liquid crystal layer Clc is very small, approximately 3 μm. Calculate ignoring the cell gap (ΔG).

Dielectric breakdown voltage of glass (GLS): 25~40kV/1mm

Dielectric breakdown voltage of the upper and lower plates of the display panel 100 when a 0.5 mm thick glass substrate is applied: 12.5 to 20 kV

Electrostatic Voltage: ±15kV

Let x be the distance between the first GND wire 130 and the floating wire 150, and x under the condition that dielectric breakdown does not occur at 15 kV is calculated as follows.

0.5mm:12.5kV(Min) = x : 15kV, x=0.1mm

Therefore, if the thickness of the second substrate 102 is 0.5 mm, the distance between the upper transparent conductive film 103 and the floating wiring 150 is approximately 0.5 mm, and the distance between the floating wiring 150 and the first GND wiring 130 is approximately 0.5 mm. The distance (x) of is 0.1 mm. Accordingly, the minimum distance between the upper transparent conductive film 103 and the first GND wire 130, which is not subject to dielectric breakdown at ESD of 15 kV or higher, is 0.6 mm. Of course, this distance depends on the substrate thickness and substrate material.

Considering the commercial substrate of the display panel 100 and the narrow bezel design, the distance (x) between the floating wire 150 and the first GND wire 130 is preferably about 0.1 mm to 0.5 mm. Therefore, the distance between the upper transparent conductive film 103 and the first GND wire 130, which can implement a narrow bezel and protect the TFT array 105 from ESD of 15 kV or higher, is approximately 0.6 mm to 1 mm.

8 and 9 are diagrams showing the structure of a display panel according to another embodiment of the present invention. FIG. 9 is a cross-sectional structure of the display panel 100 taken along the line “A-A'” in FIG. 8 .

Referring to FIGS. 8 and 9 , the first substrate 101 of the display panel 100 further includes one or more second GND wires 131 .

The second GND wire 131 is disposed between the first GND wire 130 and the floating wire 150 . The second GND wire 131 is not connected to the floating wire 150 . The second GND wire 131 is spaced apart from the first GND wire 130 by a predetermined distance and connected to the first GND wire 130 through one or more bridge patterns 132 . The GND wires 130 and 131 receive the ground voltage GND.

The second GND wire 131 is connected to the first GND wire 131 through the small bridge pattern 132, and most of the second GND wire 131 is connected to the first GND wire 130 with the substrate therebetween. are spaced apart Therefore, an electrically large resistance exists between the first GND wire 131 and the second GND wire 131 .

The static electricity voltage lowered through the floating wire 150 becomes lower due to the resistance between the second GND wire 131 between the first GND wire 130 . The second wiring 131 may be added within an optimal distance (0.6 mm to 1 mm) between the upper transparent conductive film 103 and the GND wiring 130 described in the above-described embodiment. The distance between the upper transparent conductive film 103 and the GND wire 130 may be longer by the distance between the first GND wire 130 and the second GND wire 131 .

At least one of the floating wire 150 and the second GND wire 131 may be overlapped with the sealant 104 and disposed under the sealant 104 as shown in FIG. 10 . In this case, a bezel may be smaller.

11 to 14 are cross-sectional views showing various cross-sectional structures of a display panel to which the floating wire 150 is applied. 11 and 12 are examples in which the color filter 124 is disposed on the TFT array 105 on the first substrate 101 and the black matrix 125 is disposed on the second substrate 102. to be. 13 and 14 are examples in which the color filter 124 and the black matrix 125 are formed on the second substrate 101 .

11 to 14, the floating wire 150 and the second GND wire 131 are patterned with a first metal layer, such as a gate of a TFT, as shown in FIGS. 11 and 12, or, although not shown, the source and drain of a TFT. It can be patterned with a second metal layer such as. The gate insulating layer 121 insulates patterns of the first metal layer and patterns of the second metal layer. The semiconductor pattern of the TFT is disposed under the second metal layer. The first and second protective films 122 and 123 cover the TFT array 105 . The patterns of the first metal layer are covered, and the first passivation layer 122 covers the patterns of the second metal layer. A color filter 124 may be disposed on the first passivation layer 122 . The gate insulating layer 121 and the first protective layer 122 may be formed of an inorganic insulating material such as SiNx or SiO2. The second passivation layer 123 is formed on the first passivation layer 122 to cover the color filter 124 . The second passivation layer 123 may be formed of an organic insulating material such as photo-acryl. A planarization layer 126 may be formed on the second substrate 102 . The flattening end 126 covers the black matrix 125 .

Through the above description, those skilled in the art will understand that various changes and modifications are possible without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

11: case top 12: display panel
13: panel guide 14: optical sheet
15: LED assembly 16: light guide plate
17: cover bottom 18: reflective sheet
101: first substrate of display panel 102: second substrate of display panel
103: upper transparent conductive film 104: sealant
130, 131: GND wiring 150: floating wiring
200: data driver 300: gate driver
400: Vcom generator 500: timing controller

Claims (15)

a thin film transistor array disposed on the substrate;
a first ground wire connected to the thin film transistor array on the substrate; and
A floating wiring disposed on the substrate to be separated from the thin film transistor array and the first ground wiring;
The floating wiring is spaced apart from the thin film transistor array with the first ground wiring interposed therebetween. delete According to claim 1,
The thin film transistor array substrate of claim 1 , wherein a distance between the first ground wire and the floating wire is between 0.1 mm and 0.5 mm. According to claim 1,
The thin film transistor array substrate wherein the floating wiring is disposed at an outermost part of the substrate. The method of any one of claims 1, 3, and 4,
The thin film transistor array substrate further comprising one or more second ground wires disposed between the first ground wires and the floating wires. According to claim 5,
The thin film transistor array substrate further comprising a bridge pattern connecting the first ground wire and the second ground wire. a first substrate including a thin film transistor array, a first ground wire connected to the thin film transistor array, and a floating wire separated from the thin film transistor array and the first ground wire; and
a second substrate bonded to the first substrate with a sealant;
The floating wire is spaced apart from the thin film transistor array with the first ground wire interposed therebetween. According to claim 7,
The second substrate is
The display device further comprising a transparent conductive film disposed on an outer surface of the second substrate. According to claim 8,
and a plastic case top covering an edge of the display panel including the first and second substrates. According to claim 8,
The distance between the first ground wire and the floating wire is 0.1 mm to 0.5 mm,
A display device in which a distance between the upper transparent conductive film and the first ground wire is 0.6 mm to 1 mm. According to claim 7,
A display device in which the floating wire is disposed at an outermost part of the substrate. According to claim 7,
The first substrate,
and at least one second ground wire disposed between the first ground wire and the floating wire. According to claim 12,
and a bridge pattern connecting the first ground wire and the second ground wire. According to claim 7,
A display device in which the floating wire is disposed under the sealant. According to claim 12,
The display device wherein the floating wire and the second ground wire are disposed under the sealant.

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