KR102473526B1 - Organic light emitting display device - Google Patents

Abstract

According to the present application, the voltage deviation of the reference power supply voltage can be reduced by preventing the VSS Rising phenomenon, which is a phenomenon in which the potential of the reference power supply voltage rises due to the sheet resistance of the source/drain metal layer and the cathode electrode for each area of the display panel. It relates to an organic light emitting display device. An organic light emitting display device according to the present application includes a display panel having a display area provided with pixels displaying images and a non-display area provided to surround the display area, a cathode electrode integrally disposed on the display area and the non-display area, and It includes a plurality of reference power supply voltage lines disposed in the non-display area to supply the reference power supply voltage to the cathode electrode. Each of the plurality of reference power supply voltage lines supplies different reference power supply voltages.

Description

Organic light emitting display device {ORGANIC LIGHT EMITTING DISPLAY DEVICE}

The present application relates to an organic light emitting display device.

In the information society, a lot of technologies in the field of display devices for displaying visual information as images or images are being developed. Among display devices, an organic light emitting diode display displays an image using an organic light emitting diode that generates light by recombination of electrons and holes. The organic light emitting display device has a fast response speed and at the same time is capable of expressing low gradation according to self-emission, and thus has been spotlighted as a next-generation display.

An organic light emitting display device includes a display panel having a display area in which pixels displaying images are provided and a non-display area disposed outside the display area and not displaying an image. Each of the pixels is driven by the scan signal and emits light with brightness corresponding to the size of the data voltage.

In addition, in order to drive the display panel, a reference power supply voltage (VSS voltage) must be supplied to the cathode electrode of the display panel. To supply the reference power supply voltage, the reference power supply voltage was connected to a reference power supply voltage line formed of one source/drain metal layer and supplied to a cathode electrode deposited on the front surface of the display panel through a contact hole penetrating the planarization layer. In this case, a difference occurs in the reference power supply voltage of the cathode electrode within the surface of the display panel due to the surface resistance of the cathode electrode and the line resistance of the reference power supply voltage line.

The potential of the reference power supply voltage is lower than that of the ground voltage. Accordingly, the potential value of the reference power supply voltage has a negative (-) value. A VSS rising phenomenon, which is a phenomenon in which a potential of a reference power supply voltage rises due to sheet resistance of a source/drain metal layer and a cathode electrode for each area of the display panel, occurs. When the VSS rising phenomenon occurs, a voltage deviation of the reference power voltage occurs between the upper part of the display panel, which is the part to which the reference power supply voltage is supplied, and the lower part of the display panel, which is opposite to the part to which the reference power supply voltage is supplied. . As a result of the simulation, the lower part of the display panel is the worst point. When the reference power supply voltage in the normal case is -2.5V, the reference power supply voltage is -2.18V at the bottom of the display panel, and a VSS rising phenomenon of 0.32V occurs.

The present application is an organic light emitting display that can reduce the voltage deviation of the reference power supply voltage by preventing the VSS Rising phenomenon, which is a phenomenon in which the potential of the reference power supply voltage rises due to the sheet resistance of the source/drain metal layer and the cathode electrode for each area of the display panel. We want to provide you with a device.

An organic light emitting display device according to the present application includes a display panel having a display area provided with pixels displaying images and a non-display area provided to surround the display area, a cathode electrode integrally disposed on the display area and the non-display area, and It includes a plurality of reference power supply voltage lines disposed in the non-display area to supply the reference power supply voltage to the cathode electrode. Each of the plurality of reference power supply voltage lines supplies different reference power supply voltages.

The present application may provide a structure in which voltage deviation for each region of a display panel is reduced by separating the reference power supply voltage lines and differentially applying the reference power voltages supplied to each reference power supply voltage line. The present application can reduce the voltage deviation of the cathode electrode of the worst point when the VSS Rising phenomenon occurs. The simulation result of setting the reference power supply voltage supplied to the upper part of the display panel to -2.5V and the reference power supply voltage supplied to the lower part of the display panel to -2.7V shows that the VSS rising level is 0.09V, which is the VSS rising level in the existing structure. 70% decrease compared to 0.32V.

1 is a conceptual block diagram of an organic light emitting display device according to the present application.
2 is an internal circuit diagram of a pixel according to an example of the present application.
3 is a cross-sectional view of a pixel according to an example of the present application.
4 is a plan view illustrating a plurality of reference power supply voltage lines and a cathode electrode according to an example;
5 is an equivalent circuit diagram of FIG. 4 .
6 is a plan view illustrating a plurality of reference power supply voltage lines and a cathode electrode according to another example.
7 is a plan view illustrating a plurality of reference power supply voltage lines, an anode electrode, and a cathode electrode according to another example.
FIG. 8 is a cross-sectional view taken along line I-I′ of FIG. 7 .
9 is a plan view illustrating a plurality of reference power supply voltage lines, an anode electrode, and a cathode electrode according to another example.
FIG. 10 is a cross-sectional view taken along line II-II′ of FIG. 9 .

Advantages and features of the present application, and methods of achieving them, will become clear with reference to examples described below in detail in conjunction with the accompanying drawings. However, the present application is not limited to the examples disclosed below and will be implemented in a variety of different forms, only examples of the present application make the disclosure of the present application complete, and common knowledge in the art to which this application belongs It is provided to fully inform the person who has the scope of the invention, and this application is only defined by the scope of the claims.

Since the shape, size, ratio, angle, number, etc. disclosed in the drawings for explaining an example of the present application are exemplary, the present application is not limited to the matters shown. Like reference numbers designate like elements throughout the specification. In addition, in describing the present application, if it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present application, the detailed description will be omitted.

When 'includes', 'has', 'consists', etc. mentioned in this specification is used, other parts may be added unless 'only' is used. In the case where a component is expressed in the singular, the case including the plural is included unless otherwise explicitly stated.

In interpreting the components, even if there is no separate explicit description, it is interpreted as including the error range.

In the case of a description of a positional relationship, for example, 'on top of', 'on top of', 'at the bottom of', 'next to', etc. Or, unless 'directly' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal precedence relationship is described in terms of 'after', 'following', 'next to', 'before', etc. It can also include non-continuous cases unless is used.

Although first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present application.

"First horizontal axis direction", "second horizontal axis direction", and "vertical axis direction" should not be interpreted only as a geometric relationship in which the relationship between each other is made vertically, and the range in which the configuration of the present application can function functionally It can mean having a wider direction than within.

The term “at least one” should be understood to include all possible combinations from one or more related items. For example, "at least one of the first item, the second item, and the third item" means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item, and the third item. It may mean a combination of all items that can be presented from one or more.

Each feature of the various examples of the present application can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each example can be implemented independently of each other or can be implemented together in a related relationship. .

Hereinafter, preferred examples of the organic light emitting display device according to the present application will be described in detail with reference to the accompanying drawings. In adding reference numerals to components of each drawing, the same components may have the same numerals as much as possible even if they are displayed on different drawings.

1 is a conceptual block diagram of an organic light emitting display device according to the present application. An organic light emitting display device according to the present application includes a display panel 100 , a gate driver 110 , a data driver 120 , and a timing controller (T-CON) 130 .

The display panel 100 includes a display area and a non-display area provided around the display area. The display area is an area where the pixels P are provided to display an image. The non-display area is located outside the display panel 100 and protects the display area from external impact. Gate lines GL1 to GLp (where p is a positive integer greater than or equal to 2), data lines DL1 to DLq (where q is a positive integer greater than or equal to 2), and sensing lines SL1 to SLq are provided in the display panel 100 . do.

The data lines DL1 to DLq and the sensing lines SL1 to SLq may cross the gate lines GL1 to GLp. The data lines DL1 to DLq and the sensing lines SL1 to SLq may be parallel to each other. The display panel 100 may include a lower substrate on which the pixels P are provided and an upper substrate performing an encapsulation function to protect the pixels P from external foreign substances. Each of the pixels P may be connected to one of the gate lines GL1 to GLp, one of the data lines DL1 to DLq, and one of the sensing lines SL1 to SLq.

The gate driver 120 receives the gate driver control signal GCS from the timing controller 130, generates gate signals according to the gate driver control signal GCS, and supplies them to the gate lines GL1 to GLp.

The data driver 120 receives the data driver control signal DCS from the timing controller 130, generates data voltages according to the data driver control signal DCS, and supplies them to the data lines DL1 to DLq. In addition, the data driver 120 senses voltage and current characteristics of each of the pixels P to generate sensed data SEN and supplies it to the timing controller 130 .

The timing controller 130 receives a timing signal TS for controlling the display timing of an image and digital video data DATA including color-specific information for realizing an image from the outside. The timing signal TS and digital video data DATA are input to the input terminal of the timing controller 130 according to a set protocol. Also, the timing controller 130 receives sensing data SEN according to voltage and current characteristics of each of the pixels P from the data driver 120 .

The timing signal TS includes a vertical sync signal (Vsync), a horizontal sync signal (Hsync), a data enable signal (DE), and a dot clock (DCLK). include The timing controller 130 compensates the digital video data DATA based on the sensing data SEN.

The timing controller 130 generates driver control signals for controlling operation timings of the gate driver 110 , the data driver 120 , the scan driver, and the sensing driver. The driver control signals include a gate driver control signal (GCS) for controlling the operation timing of the gate driver 110, a data driver control signal (DCS) for controlling the operation timing of the data driver 120, and an operation timing of the scan driver. A scan driver control signal for controlling and a sensing driver control signal for controlling an operation timing of the sensing driver are included.

The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal. The display mode is a mode in which the pixels P of the display panel 100 display an image, and the sensing mode is a mode in which a current of the driving transistor DT of each of the pixels P of the display panel 100 is sensed. When the waveform of the scan signal and the sensing signal supplied to each of the pixels P in the display mode and the sensing mode are changed, the data driver control signal DCS, the scan driver control signal and the The sensing driver control signal may also be changed. Accordingly, the timing controller 130 generates the data driver control signal DCS, the scan driver control signal, and the sensing driver control signal corresponding to the corresponding mode depending on which mode is selected from among the display mode and the sensing mode.

The timing controller 130 outputs the gate driver control signal GCS to the gate driver 110 . The timing controller 130 outputs the compensated digital video data and the data driver control signal DCS to the data driver 120 . The timing controller 130 outputs the scan driver control signal to the scan driver. The timing controller 130 outputs the sensing driver control signal to the sensing driver.

In addition, the timing controller 130 generates a mode signal for driving the data driver 120, the scan driver, and the sensing driver according to which mode among the display mode and the sensing mode is to be driven. The timing controller 130 operates the data driver 120, the scan driver, and the sensing driver in one of a display mode and a sensing mode according to a mode signal.

2 is an internal circuit diagram of a pixel P according to an example of the present application. The pixel P according to an example includes a driving transistor DT, a light emitting element EL, a storage capacitor Cst, and first to sixth transistors T1 to T6. In the following description, the driving transistor DT and the first to sixth transistors T1 to T6 according to an example of the present application have a gate electrode, a source electrode, and a drain electrode. Assume that it is implemented with a P-type MOSFET.

The gate electrode of the driving transistor DT is a first node (N1) to which one side electrode of the storage capacitor Cst, the drain electrode of the first transistor T1, and the drain electrode of the fifth transistor T5 are connected. connected to The source electrode of the driving transistor DT is connected to the drain electrode of the third transistor T3 receiving the pixel driving power source ELVDD as the source electrode. The drain electrode of the driving transistor DT is connected to the source electrode of the fourth transistor T4.

When a voltage higher than the threshold voltage is supplied to the gate electrode of the driving transistor DT, it is turned on. The turned-on driving transistor DT flows a driving current from the source electrode to the drain electrode.

The light emitting element EL includes an anode electrode and a cathode electrode. The light emitting element EL flows a driving current from the anode electrode to the cathode electrode. The anode electrode of the light emitting element EL is connected to the second node N2 to which the drain electrode of the fourth transistor T4 is connected. The cathode electrode of the light emitting element EL is connected to the ground line on which the low potential power supply voltage ELVSS is formed. The light emitting element EL emits light with brightness corresponding to the driving current flowing from the driving transistor DT.

The storage capacitor Cst has both electrodes. One electrode of the storage capacitor Cst is connected to the first node N1. The other electrode of the storage capacitor Cst is connected to the pixel driving power ELVDD line.

The storage capacitor Cst stores a difference voltage between the pixel driving power source ELVDD and the first node N1 when the fifth transistor T5 connected to the first node N1 is turned on. The storage capacitor Cst maintains the differential voltage stored in the first node N1 when the fifth transistor T5 is turned off. Also, the storage capacitor Cst may control driving of the driving transistor DT using the stored and maintained voltage.

The gate electrode of the first transistor T1 receives the second scan signal Scan2. The source electrode of the first transistor T1 is connected to the drain electrode of the driving transistor DT. The drain electrode of the first transistor T1 is connected to the first node N1. The first transistor T1 is turned on by the second scan signal Scan2, and the voltage of the first node N1 is Vdata, which is the sum of the data voltage Vdata and the threshold voltage Vtp of the driving transistor DT. Raise to +Vtp.

The gate electrode of the second transistor T2 receives the second scan signal Scan2. The source electrode of the second transistor T2 is connected to the data line DL to receive the data voltage Vdata. The drain electrode of the second transistor T2 is connected to the source electrode of the driving transistor DT. The second transistor T1 is turned on by the second scan signal Scan2 and supplies the data voltage Vdata to the source electrode of the driving transistor DT.

The gate electrode of the third transistor T3 receives the emission control signal EM. The source electrode of the third transistor T3 receives the pixel driving power source ELVDD. The drain electrode of the third transistor T3 is connected to the source electrode of the driving transistor DT. The third transistor T3 is turned on by the emission control signal EM to supply the pixel driving power source ELVDD to the driving transistor DT so that the driving transistor DT can flow a driving current.

The gate electrode of the fourth transistor T4 receives the emission control signal EM. The source electrode of the fourth transistor T4 is connected to the drain electrode of the driving transistor DT. The drain electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 is turned on by the emission control signal EM, so that a driving current flows through the light emitting element EL, thereby causing the light emitting element EL to emit light.

The gate electrode of the fifth transistor T5 receives the first scan signal Scan1. The source electrode of the fifth transistor T5 receives the initialization voltage Vinit. A drain electrode of the fifth transistor T5 is connected to the first node N1. The fifth transistor T5 is turned on by the first scan signal Scan1 to initialize the voltage at the first node N1 to the initialization voltage Vinit.

The gate electrode of the sixth transistor T6 receives the first scan signal Scan1. The source electrode of the sixth transistor T6 receives the initialization voltage Vinit. The drain electrode of the sixth transistor T6 is connected to the second node N2. The sixth transistor T6 is turned on by the first scan signal Scan1 to initialize the voltage of the second node N2 to the initialization voltage Vinit.

The pixel P according to the first embodiment of the present invention is composed of seven thin film transistors (TFTs) and one capacitor, and is collectively referred to as a 7T1C compensation circuit. Also, the pixel P according to the first embodiment of the present invention operates with two types of scan signals (Scan) and one type of emission control signal (EM).

When a certain frame starts, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT maintains the gate low voltage VGL. In addition, the emission control signal EM is also in the gate low voltage VGL state. Accordingly, the third and fourth transistors T3 and T4 are turned on. Accordingly, a certain amount of driving current flows through the driving transistor DT, thereby causing the light emitting element EL to emit light.

Thereafter, the emission control signal EM has a gate high voltage VGH, and the source and drain electrodes of the driving transistor DT become a floating state.

Thereafter, the pixel P has an initialization step. In the initialization step, when the first scan signal Scan1 becomes the gate low voltage VGL, the fifth transistor T5 is turned on and the initialization voltage Vinit is applied to the first node N1. After the initialization step, when the first scan signal Scan1 becomes the gate high voltage VGH again, the fifth transistor T5 is turned off and the first node N1 is in a floating state.

After that, the pixel P has a programming step. In the programming step, when the second scan signal Scan2 becomes the gate low voltage VGL, the first, second, and sixth transistors T1, T2, and T6 are turned on. The light emitting element EL is reset by the sixth transistor T6. Also, the second transistor T2 is turned on and the data voltage Vdata is supplied to the source electrode of the driving transistor DT.

The initialization voltage Vinit of the pixel P according to an example of the present application is lower than the data voltage Vdata. In addition, the data voltage Vdata is supplied to the source electrode of the driving transistor DT, and the initialization voltage is supplied to the gate electrode of the driving transistor DT. Accordingly, the difference voltage Vgs between the gate voltage and the source voltage of the driving transistor DT has a negative (-) voltage value.

When the difference voltage Vgs between the gate voltage and the source voltage has a negative voltage value, the driving transistor DT operates in a linear region. Accordingly, the voltage of the drain electrode of the driving transistor DT rises. Since the first transistor T1 is in a turned-on state, the drain electrode and the gate electrode of the driving transistor can be electrically regarded as the same node. As a result, the voltage of the first node N1 rises to Vdata+Vth, which is a sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT. Here, the threshold voltage (Vth) has a negative voltage value.

Thereafter, the pixel P has a threshold voltage (Vth) sensing step. In the threshold voltage (Vth) sensing step, since the voltage of the first node (N1) rises to the sum of the data voltage (Vdata) and the threshold voltage (Vth) of the driving transistor (DT), the driving transistor (DT) It is turned off and only the leakage (subthreshold) current flows.

In this case, the threshold voltage Vth may be sensed by sensing Vdata+Vth, which is the voltage of the gate electrode of the driving transistor DT, based on the data voltage Vdata.

Thereafter, when the emission control signal EM becomes the gate low voltage VGL again, the pixel driving voltage ELVDD is supplied to the drain electrode of the driving transistor. Accordingly, the next frame starts, and the light emitting element EL emits light.

3 is a cross-sectional view of a pixel P according to an example of the present application. The pixel P according to an example includes a base layer 210, a buffer layer 220, a semiconductor layer 230, a gate insulating layer 235, a gate metal layer 240, a first bridge 241, and a source/drain metal layer. 250, a first interlayer insulating film 260, an intermediate metal layer 270, a second interlayer insulating film 280, a planarization film 290, an anode electrode 300, a light emitting layer 320, a cathode electrode 330, and A partition wall 340 is included.

The base layer 210 forms the lowest layer of the organic light emitting display device. The base layer 210 may support circuit elements and wires constituting the circuit unit provided thereon. Alternatively, the base layer 210 may be formed of flexible plastic to make the organic light emitting display device flexible.

The buffer layer 220 covers the top of the base layer 210 . The buffer layer 220 is formed of a material having excellent insulating properties. The buffer layer 220 protects circuit elements and wires constituting the circuit unit provided on the base layer 210 from external impact or static electricity.

The semiconductor layer 230 is disposed on top of the buffer layer 220 . The semiconductor layer 230 is made of a doped semiconductor. The semiconductor layer 230 forms a channel of a thin film transistor constituting the pixel P. The semiconductor layer 230 includes a gate channel 231 , a first channel 232 , and a second channel 233 . The gate channel 231 forms a channel of a gate electrode of a thin film transistor. The first and second electrode layers 233 form channels of the source and drain electrodes of the thin film transistor.

The gate insulating layer 235 is disposed on the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 entirely covers the buffer layer 220 and the semiconductor layer 230 . The gate insulating layer 235 is formed of a material having excellent insulating properties. The gate insulating layer 235 prevents the semiconductor layer 230 from being short-circuited with the gate metal layer 240 and separates channels of thin film transistors formed by the semiconductor layer 230 .

A gate metal layer 240 is disposed on top of the gate insulating layer 235 . The gate metal layer 240 is a gate metal layer forming gate electrodes and gate lines GL1 to GLp of the thin film transistor. The gate metal layer 240 may be formed of a metal or alloy having excellent electrical conductivity.

The first interlayer insulating film 260 is disposed on the gate metal layer 240 and the first bridge 241 . The first interlayer insulating film 260 is formed of a material having excellent electrical insulating properties.

The middle metal layer 270 is disposed on the first interlayer insulating layer 260 . The middle metal layer 270 is disposed overlapping with the gate metal layer 240 forming the gate electrode of the thin film transistor among the gate metal layers 240 . The middle metal layer 270 forms mutual capacitance with the gate metal layer 240 forming the gate electrode of the thin film transistor. The middle metal layer 270 serves as an electrode on one side of the storage capacitance.

The second interlayer insulating film 280 is disposed on the first interlayer insulating film 260 and the intermediate metal layer 270 . The second interlayer insulating film 280 is formed of a material having excellent electrical insulating properties.

The source/drain metal layer 250 is disposed on the second interlayer insulating layer 280 . The source/drain metal layer 250 forms the first electrode 251 and the second electrode 252 of the thin film transistor constituting the pixel P. The source/drain metal layer 250 forms a first electrode 253 of the first connection transistor CT1 , an inversion enable line 254 , an enable line 255 , and a turn-on test data line 256 . The source/drain metal layer 250 is a source/drain metal layer disposed on top of the gate metal layer 240 . The source/drain metal layer 250 may be formed of a metal or alloy having excellent electrical conductivity.

The planarization layer 290 is disposed on the second interlayer insulating layer 280 and the source/drain metal layer 250 . The planarization layer 290 reduces the height difference of the upper surface. Accordingly, the planarization layer 290 can solve the deviation of the height in the Z-axis direction relative to the base layer 210 depending on the region.

The anode electrode 300 is disposed on the planarization film 290 . The anode electrode 300 is connected to the second electrode 252 of the thin film transistor constituting the pixel P. The anode electrode 300 supplies a driving voltage or a data voltage to the second electrode 252 of the thin film transistor. The anode electrode 300 may be classified for each pixel P. Between adjacent anode electrodes 300 may be electrically insulated due to the barrier rib 340 .

The light emitting layer 320 is provided on the anode electrode 300 . The light emitting layer 320 may include a hole transporting layer, an organic light emitting layer, and an electron transporting layer. In the light emitting layer 320, when voltage is applied to the anode electrode 300 and the cathode electrode 330, holes and electrons move to the organic light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the organic light emitting layer to emit light.

The cathode electrode 330 is provided on the light emitting layer 320 and the bank 340 . The cathode electrode 330 supplies a driving voltage.

The bank 340 is provided between the anode electrodes 300 of the pixels P. The bank 340 divides the pixels P.

4 is a plan view illustrating a plurality of reference power supply voltage lines VSSL1 to VSSL3 and a cathode electrode 330 according to an example.

The plurality of reference power supply voltage lines VSSL1 to VSS3 according to an example may include first to third reference power supply voltage lines VSSL1 to VSSL3 . However, it is not limited thereto, and the number of the plurality of reference power supply voltage lines VSSL1 to VSS3 may be more or less than three.

The first reference power supply voltage line VSSL1 is disposed innermost among the plurality of reference power supply voltage lines VSSL1 to VSS3. The first reference power supply voltage line VSSL1 is disposed adjacent to the display area. The first reference power supply voltage line VSSL1 supplies the first reference power supply voltage VSS1.

The second reference power supply voltage line VSSL2 is disposed outside the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 is electrically separated from the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 is disposed farther from the display area than the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 supplies the second reference power supply voltage VSS2.

The third reference power supply voltage line VSSL3 is disposed outside the second reference power supply voltage line VSSL2. The third reference power supply voltage line VSSL3 is electrically separated from the second reference power supply voltage line VSSL2. The third reference power supply voltage line VSSL3 is disposed farther from the display area than the second reference power supply voltage line VSSL2. The third reference power supply voltage line VSSL3 supplies the third reference power supply voltage VSS3.

The cathode electrode 330 is integrally disposed on the entire display area and a part of the non-display area. The cathode electrode 330 partially or completely overlaps the first to third reference power supply voltage lines VSSL1 to VSSL3 in the non-display area. The cathode electrode 330 overlaps each of the first to third reference power supply voltage lines VSSL1 to VSSL3 in at least a partial area. For example, the cathode electrode 330 may be disposed in all regions on the first and second reference power supply voltage lines VSSL1 to VSSL2 and may be disposed in a partial region on the third reference power supply voltage line VSSL3.

An organic light emitting display device according to an example includes a display panel 100 having a display area in which pixels P displaying images are provided and a non-display area provided to surround the display area, and the display area and the non-display area are integrally disposed. a cathode electrode 330 and a plurality of reference power supply voltage lines VSSL1 to VSSL3 disposed in the non-display area to supply the reference power supply voltages VSS1 to VSS3 to the cathode electrodes 330 .

In the case of having a plurality of reference power supply voltage lines (VSSL1 to VSSL3) and supplying a reference power supply voltage having a single magnitude from a single reference power supply voltage line, characteristics of the display panel 100 and the cathode electrode 330 for each region It is possible to supply a reference power supply voltage of an appropriate size by reflecting this. Accordingly, it is possible to more stably supply the reference power supply voltage, thereby improving image quality and increasing drive stability.

In particular, each of the plurality of reference power supply voltage lines VSSL1 to VSSL3 according to an example supplies different reference power voltages VSS1 to VSS3. Accordingly, different reference power supply voltages VSS1 to VSS3 may be supplied to each region of the display panel 100 and the cathode electrode 330 . Different reference power supply voltages (VSS1 to VSS3) are set by reflecting the deviation of the reference power supply voltage by distance and area according to the surface resistance of the cathode electrode 330 and the line resistance of the plurality of reference power supply voltage lines (VSSL1 to VSSL3). can be supplied. Accordingly, deviation of the reference power voltage for each distance and region according to the line resistance of the plurality of reference power supply voltage lines VSSL1 to VSSL3 can be reduced.

The first reference power voltage VSS1 according to an example has a higher potential than the second reference power voltage VSS2. The reference power supply voltage refers to the potential of the cathode electrode of the light emitting element EL, and is a voltage supplied to a layer opposite to the drain electrode of the driving transistor DT to which the pixel driving power source ELVDD is supplied. Accordingly, the potential of the reference power supply voltage has a negative (-) potential lower than that of the ground voltage. Since the second reference power supply voltage VSS2 has a lower potential than the first reference power supply voltage VSS1, the magnitude of the absolute value of the second reference power supply voltage VSS2 is the absolute value of the first reference power supply voltage VSS1. larger than the size of For example, when the first reference power voltage VSS1 is -2.5V, the second reference power voltage VSS2 may be -2.6V.

Also, the second reference power voltage VSS2 according to an example has a higher potential than the third reference power voltage VSS3. Since the third reference power supply voltage VSS3 has a lower potential than the second reference power supply voltage VSS2, the magnitude of the absolute value of the third reference power supply voltage VSS3 is the absolute value of the second reference power supply voltage VSS2. larger than the size of For example, when the second reference power voltage VSS2 is -2.6V, the third reference power voltage VSS3 may be -2.7V.

The reference power supply voltage should originally have a negative (-) voltage, but is approximated to the ground voltage by the line resistance of the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the sheet resistance of the cathode electrode 330. That is, a VSS rising phenomenon in which the potential of the reference power supply voltage rises occurs. The rising value of the potential of the reference power supply voltage due to the VSS rising phenomenon increases as the length of the reference power supply voltage line increases. In addition, the increase value of the potential of the reference power supply voltage due to the VSS rising phenomenon increases as the distance from the point to which the reference power supply voltage is supplied increases. Accordingly, a voltage deviation of the reference power supply voltage occurs between the upper portion of the display panel 100, which is a portion to which the reference power supply voltage is supplied, and the lower portion of the display panel, which is opposite to the portion to which the reference power voltage is supplied, of the display panel 100. do.

The plurality of reference power supply voltage lines VSSL1 to VSSL3 according to an example supply the first reference power supply voltage VSS1 to the first reference power supply voltage line VSSL1 for supplying the reference power voltage to the upper portion of the display panel 100 . do. In addition, the second reference power supply voltage VSS2 is supplied to the second reference power supply voltage line VSSL2 supplying the reference power voltage to the central region of the display panel 100 . In addition, the third reference power supply voltage VSS3 is supplied to the third reference power supply voltage line VSSL3 supplying the reference power voltage to the lower region of the display panel 100 .

Accordingly, the first reference power supply voltage VSS1 having the same potential as the original reference power supply voltage may be supplied to the top of the display panel 100 according to an example. At the same time, the VSS rising phenomenon at the center of the display panel 100 may be compensated for by supplying the second reference power supply voltage VSS2 having a lower potential than the first reference power supply voltage VSS1 to the central portion of the display panel 100 . have. At the same time, a third reference power supply voltage VSS3 having a lower potential than the second reference power supply voltage VSS2 is supplied to the lower portion of the display panel 100 to compensate for the VSS rising phenomenon at the lower portion of the display panel 100. can

When calculating how much the reference power supply voltage rises for each area of the display panel 100 according to the VSS rising phenomenon and supplying a voltage at a potential as low as the calculated voltage rise value to the corresponding area as the reference power voltage, the display panel 100 The magnitudes of the reference power supply voltages at the top, center, and bottom of can all be the same. Accordingly, deviation of the reference power supply voltage for each region of the display panel 100 may be reduced, thereby improving luminance deviation and driving stability of the display panel 100 .

According to an example, the first reference power supply voltage line VSSL1 is connected to the cathode electrode 330 through the first contact hole CNT1 and the fourth contact hole CNT4, and the second reference power supply voltage line VSSL2 is It is connected to the cathode electrode 330 through the second contact hole CNT2 and the fifth contact hole CNT5, and the third reference power supply voltage line VSSL3 is connected to the third contact hole CNT3 and the sixth contact hole CNT6. ), and is connected to the cathode electrode 330 through the seventh contact hole CNT7. The first to seventh contact holes CNT1 to CNT7 are formed on the same layer. The first to seventh contact holes CNT1 to CNT7 are formed so as not to overlap each other. The first to seventh contact holes CNT1 to CNT7 are formed through the planarization layer 290 .

The first contact hole CNT1 and the fourth contact hole CNT4 are the cathode electrodes receiving the first reference power supply voltage VSS1 in the region where the first reference power supply voltage line VSSL1 and the cathode electrode 330 overlap ( 300) is disposed adjacent to the top. For example, when the first reference power supply voltage VSS1 is supplied from the upper portion of the cathode electrode 330, the first contact hole CNT1 is disposed on the upper left side of the cathode electrode 330, and the fourth contact hole CNT4 ) may be disposed on the upper right side of the cathode electrode 330. The first contact hole CNT1 and the fourth contact hole CNT4 may be symmetrically disposed on upper portions of both sides of the cathode electrode 330 .

The second contact hole CNT2 and the fifth contact hole CNT5 are the cathode electrodes receiving the second reference power supply voltage VSS2 among the regions where the second reference power supply voltage line VSSL2 and the cathode electrode 330 overlap. 300) is disposed adjacent to the central portion. For example, when the second reference power supply voltage VSS2 is supplied from the top of the cathode electrode 330, the second contact hole CNT2 is disposed in the central left portion of the cathode electrode 330, and the fifth contact hole CNT5 ) may be disposed on the right central portion of the cathode electrode 330 . The second contact hole CNT2 and the fifth contact hole CNT5 may be symmetrically disposed in the central portion of both sides of the cathode electrode 330 .

The third contact hole CNT3 and the sixth contact hole CNT6 are the cathode electrodes receiving the third reference power supply voltage VSS3 among the areas where the third reference power supply voltage line VSSL3 and the cathode electrode 330 overlap. 330) is disposed adjacent to the lower portion. For example, when the third reference power supply voltage VSS3 is supplied from the top of the cathode electrode 330, the third contact hole CNT3 is disposed on the lower left side of the cathode electrode 330, and the sixth contact hole CNT6 ) may be disposed on the lower right side of the cathode electrode 330. The third contact hole CNT3 and the sixth contact hole CNT6 may be symmetrically disposed on both lower portions of the cathode electrode 330 .

The seventh contact hole CNT7 is disposed below the cathode electrode 330 receiving the third reference power supply voltage VSS3 in an area where the third reference power supply voltage line VSSL3 and the cathode electrode 330 overlap. For example, when the third reference power supply voltage VSS3 is supplied from the upper portion of the cathode electrode 330 , the seventh contact hole CNT7 is disposed at the lower center of the cathode electrode 330 .

The size of the seventh contact hole CNT7 may be larger than that of the first to sixth contact holes CNT1 to CNT6. The seventh contact hole CNT7 is connected to the lower center of the lower part of the cathode electrode 330 to which the third reference power supply voltage VSS3 is supplied, the farthest from the supply point of the third reference power supply voltage VSS3. Accordingly, in order to smoothly supply the third reference power voltage VSS3, the seventh contact hole CNT7 is wider than the first to sixth contact holes CNT1 to CNT6 at the lower center of the cathode electrode 330. can have an area.

Also, when the area of the seventh contact hole CNT7 increases, the contact area between the third reference power supply voltage line VSSL3 and the cathode electrode 330 also increases in the seventh contact hole CNT7. Accordingly, the contact resistance between the third reference power supply voltage line VSSL3 and the cathode electrode 330 is reduced, thereby reducing the VSS rising phenomenon due to the voltage drop due to the contact resistance in the seventh contact hole CNT7.

In one example, as shown in FIG. 4 , the first reference power supply voltage line VSSL1 is disposed to surround the display area, and the second reference power supply voltage line VSSL2 is disposed to surround the first reference power supply voltage line VSSL1. , the third reference power supply voltage line VSSL3 is arranged to surround the second reference power supply voltage line VSSL2.

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is formed to be connected to both side corners and lower corners of the display area, with the display area as the center. Accordingly, while connecting the first to third reference power supply voltage lines VSSL1 to VSSL3 to a desired region on the cathode electrode 330, the first to third reference power supply voltages are connected in the same form as the conventional single reference power supply voltage line structure. Since the lines VSSL1 to VSSL3 may be formed, additional manufacturing costs for forming the first to third reference power supply voltage lines VSSL1 to VSSL3 may be minimized.

5 is an equivalent circuit diagram of FIG. 4 . Referring to the equivalent circuit of FIG. 5 , the line resistance of the first to third reference power supply voltage lines VSSL1 to VSSL3 and the area-specific surface resistance of the cathode electrode 330 on the display panel 100 are defined as resistance R. modeled.

The distance from the point where the first to third reference power supply voltages VSS1 to VSS3 are supplied increases toward the lower region of the cathode electrode 330 . When the surface resistance of each region of the cathode electrode 330 is uniform, the VSS rising phenomenon according to the voltage drop principle of the first to third reference power supply voltages VSS1 to VSS3 increases toward the lower region of the cathode electrode 330. do.

When the first to third reference power supply voltage lines VSSL1 to VSSL3 are arranged as shown in FIG. 5 , the first to third reference power supply voltages VSS1 to VSS3 are located on the upper, middle, and lower portions of the cathode electrode 330 . supplied individually. Accordingly, the upper, central, and It is possible to reduce the deviation of the resistance to the lower part.

6 is a plan view illustrating a plurality of reference power supply voltage lines VSSL1 to VSSL3 and a cathode electrode 330 according to another example.

According to another example, the first reference power supply voltage line VSSL1 is disposed at a portion of the corner of the non-display area, and the second reference power supply voltage line VSSL2 is disposed to extend beyond the first reference power supply voltage line VSSL1. 3 The reference power supply voltage line VSSL3 is disposed to extend beyond the second reference power supply voltage line VSSL2.

The first reference power supply voltage line VSSL1 extends from a point where the first reference power supply voltage VSS1 is supplied to a point where the first and fourth contact holes CNT1 and CNT4 are disposed. For example, when the first reference power supply voltage VSS1 is supplied from the upper center of the display panel 100, one side of the first reference power supply voltage line VSSL1 is at the upper part of the non-display area where the cathode electrode 330 is formed. It extends from the center to the upper left corner. In addition, the other side of the first reference power supply voltage line VSSL1 extends from the upper center to the upper right corner of the non-display area where the cathode electrode 330 is formed.

The second reference power supply voltage line VSSL2 extends from a point where the second reference power supply voltage VSS2 is supplied to a point where the second and fifth contact holes CNT2 and CNT5 are disposed. For example, when the second reference power supply voltage VSS3 is supplied from the upper center of the display panel 100, one side of the second reference power supply voltage line VSSL2 is located at the upper part of the non-display area where the cathode electrode 330 is formed. It extends from the center to the left midsection. In addition, the other side of the second reference power supply voltage line VSSL2 extends from the upper center to the right center of the non-display area where the cathode electrode 330 is formed.

The third reference power voltage line VSSL3 extends from a point where the third reference power voltage VSS3 is supplied to a point where the third contact hole, the sixth contact hole, and the seventh contact hole CNT3, CNT6, and CNT7 are disposed. is extended For example, when the third reference power supply voltage VSS3 is supplied from the upper center of the display panel 100, one side of the third reference power supply voltage line VSSL3 is at the upper part of the non-display area where the cathode electrode 330 is formed. It extends from the center to the lower left corner. In addition, the other side of the third reference power supply voltage line VSSL3 extends from the upper center to the lower right corner of the non-display area where the cathode electrode 330 is formed. In addition, the third reference power supply voltage line VSSL3 is formed over the entire area where the seventh contact hole CNT7 is formed, among the non-display areas where the cathode electrode 330 is formed. Accordingly, the third reference power supply voltage line VSSL3 is disposed to surround the display area, the first reference power supply voltage line VSSL1, and the second reference power supply voltage line VSSL2.

According to another example, a width of a region in which the second and fifth contact holes CNT2 and CNT5 of the second reference power supply voltage line VSSL2 are formed is wider than that of the first reference power supply voltage line VSSL1, and the third reference power supply The width of the region where the third and sixth contact holes CNT2 and CNT5 of the voltage line VSSL3 are formed is wider than that of the second reference power supply voltage line VSSL2.

A region in which the second and fifth contact holes CNT2 and CNT5 of the second reference power supply voltage line VSSL2 are formed may be defined as an extended portion of the second reference power supply voltage line VSSL2. Also, the region where the third contact hole, the sixth contact hole, and the seventh contact hole (CNT3, CNT6, CNT7) of the third reference power supply voltage line VSSL2 are formed is an extension of the third reference power supply voltage line VSSL3. can be defined in parts.

In the extended portion of the second reference power supply voltage line VSSL2, the width of the second reference power supply voltage line VSSL2 is greater than the width of the remaining portion of the second reference power supply voltage line VSSL2. In the extended portion of the second reference power supply voltage line VSSL2, the width of the second reference power supply voltage line VSSL2 increases in the direction of the first reference power supply voltage line VSSL1. The second reference power supply voltage line VSSL2 includes the width of the remaining portion of the second reference power supply voltage line VSSL2 in the extended portion, the width of the first reference power supply voltage line VSSL1, the first and second reference voltage lines ( VSSL1, VSSL2) has a width that is the sum of the distances between them.

In the extended portion of the third reference power supply voltage line VSSL3, the width of the third reference power supply voltage line VSSL3 is thicker than that of the remaining portion of the third reference power supply voltage line VSSL3. In the extended portion of the third reference power supply voltage line VSSL3, the width of the third reference power supply voltage line VSSL3 increases in the direction of the first and second reference power supply voltage lines VSSL1 and VSSL2. The third reference power supply voltage line VSSL3 has a width greater than the sum of the widths of the first and second reference power supply voltage lines VSSL1 to VSSL3 at the extended portion.

As such, when the widths of the extended portions of the second and third reference power voltage lines VSSL2 and VSSL3 are increased, the second to third and fifth to seventh contact holes CNT2 to CNT3 and CNT5 to CNT7 It is possible to increase the area of this disposed region. Accordingly, the second and third reference power supply voltage lines VSSL2 and VSSL3 and the second to third and fifth to seventh contact holes CNT2 to CNT3 and CNT5 to CNT7 more stably interact with the cathode electrode 330. allow it to connect. In addition, when the area of the region where the second to third and fifth to seventh contact holes CNT2 to CNT3 and CNT5 to CNT7 are disposed is increased, the second and third reference power supply voltage lines VSSL2 and VSSL3 and the cathode An area in contact with the electrode 330 may be increased. Accordingly, contact resistance between the second and third reference power supply voltage lines VSSL2 and VSSL3 and the cathode electrode 330 is reduced, thereby preventing a VSS rising phenomenon due to a voltage drop due to the contact resistance.

7 is a plan view illustrating a plurality of reference power supply voltage lines VSSL1 to VSSL3, an anode electrode 300, and a cathode electrode 330 according to another example.

An organic light emitting display device according to another example further includes an anode electrode 300 disposed on a non-display area. The anode electrode 300 is disposed along the plurality of reference power supply voltage lines VSSL1 to VSSL3. In FIG. 7 , only the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the anode electrode 300 disposed on one side of the cathode electrode 330 are shown. However, it is not limited thereto, and the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the anode electrode 300 are disposed on both sides and all lower corners of the cathode electrode 330 . The node electrode 300 is disposed to overlap all of the plurality of reference power supply voltage lines VSSL1 to VSSL3 and the cathode electrode 330 in at least a partial area of the non-display area.

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is connected to the anode electrode 300 . Taking the first to third reference power supply voltage lines VSSL1 to VSSL3 provided on one side as an example, the first reference power supply voltage line VSSL1 is connected to the anode electrode 300 through the first contact hole CNT1. The second reference power supply voltage line VSSL2 is connected to the anode electrode 300 through the second contact hole CNT2. The third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the third contact hole CNT3.

In the same way, the first reference power supply voltage line VSSL1 provided on the other side is connected to the anode electrode 300 through the fourth contact hole CNT4. The second reference power supply voltage line VSSL2 is connected to the anode electrode 300 through the fifth contact hole CNT5. The third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the sixth contact hole CNT6.

In addition, the third reference power supply voltage line VSSL3 is connected to the anode electrode 300 through the seventh contact hole CNT3.

FIG. 8 is a cross-sectional view taken along line I-I′ of FIG. 7 .

Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 according to an example includes a source/drain metal layer 250 . Each of the first to third reference power supply voltage lines VSSL1 to VSSL3 is disposed on the same layer using the same material as the layer forming the source electrode and the drain electrode of the thin film transistor of the pixel P.

Each of the anode electrode 300 and the first to third reference power supply voltage lines VSSL1 to VSSL3 according to an example is provided through a contact hole penetrating the planarization film 290 disposed on the source/drain metal layer 250. electrically connected

The cathode electrode 330 and the anode electrode 300 according to an example are electrically connected through a contact hole penetrating the electrode separation layer 310 disposed above the anode electrode 300 . The electrode separation layer 310 is disposed on the anode electrode 300 to separate the anode electrode 300 and the cathode electrode 330 . The electrode separation layer 310 may be formed of an inorganic material that has excellent electrical insulation and is easy to prepare a contact hole.

As such, the first to seventh contact holes CNT1 to CNT7 according to an example all have a double contact hole structure including a contact hole penetrating the planarization layer 290 and a contact hole penetrating the electrode separation layer 310 . have Accordingly, the first to seventh contact holes CNT1 to CNT7 transmit first to third reference voltage lines from the first to third reference power supply voltage lines VSSL1 to VSSL3 to the cathode electrode 330 via the anode electrode 300. Power supply voltages (VSS1 to VSS3) can be supplied.

The anode electrode 300 according to an example is entirely disposed over the first to third reference power supply voltage lines VSSL1 to VSSL3.

The anode electrode 300 according to an example is connected to each of the first to third reference power supply voltage lines VSSL1 to VSSL3 through contact holes CNT1 to CNT7. Different reference power supply voltages are supplied through the respective contact holes CNT1 to CNT7. For example, since the first and fourth contact holes CNT1 and CNT4 are connected to the first reference power voltage line VSSL1, the first reference power voltage ( VSS1) is supplied. In addition, since the second and fifth contact holes CNT2 and CNT5 are connected to the second reference power supply voltage line VSSL2, the second reference power supply voltage VSS2 is passed through the second and fifth contact holes CNT2 and CNT5. ) is supplied. In addition, since the third contact hole, the sixth contact hole, and the seventh contact hole CNT3 , CNT6 , and CNT7 are connected to the third reference power supply voltage line VSSL3 , the third contact hole, the sixth contact hole, and the seventh contact hole The third reference power supply voltage VSS3 is supplied through the seven contact holes CNT3, CNT6, and CNT7.

9 is a plan view illustrating a plurality of reference power supply voltage lines VSSL1 to VSSL3, an anode electrode 300, and a cathode electrode 330 according to another example. FIG. 10 is a cross-sectional view taken along line II-II′ of FIG. 9 .

The anode electrode 300 according to another example is patterned and disposed above the first to third reference power supply voltage lines VSSL1 to VSSL3. The anode electrode 300 is patterned and disposed in each of the first to seventh contact holes CNT1 to CNT7.

Different reference power supply voltages are supplied to each of the patterned anode electrodes 300 according to another example. For example, since the first and fourth contact holes CNT1 and CNT4 are connected to the first reference power supply voltage line VSSL1, the anode electrode 300 disposed on the first and fourth contact holes CNT1 and CNT4 A first reference power supply voltage VSS1 is supplied. In addition, since the second and fifth contact holes CNT2 and CNT5 are connected to the second reference power supply voltage line VSSL2, the anode electrode 300 disposed on the second and fifth contact holes CNT2 and CNT5 has A second reference power voltage VSS2 is supplied. In addition, since the third contact hole, the sixth contact hole, and the seventh contact hole CNT3 , CNT6 , and CNT7 are connected to the third reference power supply voltage line VSSL3 , the third contact hole, the sixth contact hole, and the seventh contact hole The third reference power supply voltage VSS3 is supplied to the anode electrode 300 disposed on the 7 contact holes CNT3 , CNT6 , and CNT7 .

In this case, when the anode electrode 300 is disposed as a single layer, the anode electrode 300 having a different reference power source voltage may be disposed for each area of the cathode electrode 330 on the display panel 100 . Accordingly, different reference power supply voltages may be supplied to match characteristics of each region of the cathode electrode 330 . In particular, since a reference power supply voltage having a lower potential than that of an upper region can be supplied to the lower region of the cathode electrode 330, even if a VSS rising phenomenon occurs frequently in the lower region of the cathode electrode 330, this can be compensated for.

The present application may provide a structure in which voltage deviation for each region of a display panel is reduced by separating the reference power supply voltage lines and differentially applying the reference power voltages supplied to each reference power supply voltage line. The present application can reduce the voltage deviation of the cathode electrode of the worst point when the VSS Rising phenomenon occurs. The simulation result of setting the reference power supply voltage supplied to the upper part of the display panel to -2.5V and the reference power supply voltage supplied to the lower part of the display panel to -2.7V shows that the VSS rising level is 0.09V, which is the VSS rising level in the existing structure. 70% decrease compared to 0.32V.

Through the above description, those skilled in the art will know that various changes and modifications are possible without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but should be defined by the claims.

100: display panel 110: gate driver
120: data driver 130: timing controller
P: Pixel DT: Driving Transistor
EL: light emitting element Cst: storage capacitor
T1 to T6: first to sixth transistors
VSSL1 to VSSL3: first to third reference power supply voltage lines
210: base layer 220: buffer layer
230: semiconductor layer 235: gate insulating layer
240: gate metal layer 250: source/drain metal layer
260: first interlayer insulating film 270: intermediate metal layer
280: second interlayer insulating film 290: planarization film
300: anode electrode 310: electrode separation layer
320: light emitting layer 330: cathode electrode
340: bank

Claims (9)

a display panel having a display area provided with pixels displaying images and a non-display area provided to surround the display area;
a cathode electrode integrally disposed on the entire display area and a portion of the non-display area; and
a plurality of reference power supply voltage lines disposed in the non-display area to supply a reference power supply voltage to the cathode electrode;
Each of the plurality of reference power supply voltage lines supplies different reference power supply voltages,
Among the plurality of reference power supply voltage lines, an outermost reference power supply voltage line is disposed to surround the display area;
Of the plurality of contact holes connecting the outermost reference power supply line and the cathode electrode, a contact hole disposed at a lower center of the cathode electrode has the largest area. According to claim 1,
The plurality of reference power supply voltage lines,
a first reference power supply voltage line disposed adjacent to the display area and supplying a first reference power supply voltage;
a second reference power supply voltage line disposed farther from the display area than the first reference power supply voltage line to supply a second reference power supply voltage; and
A third reference power supply voltage line disposed farther from the display area than the second reference power supply voltage line to supply a third reference power supply voltage;
The first reference power supply voltage has a higher potential than the second reference power supply voltage;
The second reference power supply voltage has a higher potential than the third reference power supply voltage. According to claim 2,
The first reference power supply voltage line is connected to the cathode electrode through a first contact hole and a fourth contact hole,
The second reference power supply voltage line is connected to the cathode electrode through a second contact hole and a fifth contact hole,
The third reference power supply voltage line is connected to the cathode electrode through a third contact hole, a sixth contact hole, and a seventh contact hole. According to claim 2,
The first reference power supply voltage line is arranged to surround the display area,
The second reference power supply voltage line is arranged to surround the first reference power supply voltage line;
The third reference power supply voltage line is arranged to surround the second reference power supply voltage line. According to claim 2,
The first reference power supply voltage line is disposed at a portion of a corner of the non-display area;
The second reference power supply voltage line is arranged to extend beyond the first reference power supply voltage line;
The third reference power supply voltage line is arranged to extend beyond the second reference power supply voltage line;
A width of an extended portion of the second reference power supply voltage line is wider than a width of the first reference power supply voltage line;
The organic light emitting display device of claim 1 , wherein a width of an extended portion of the third reference power supply line is greater than a width of the second reference power supply voltage line. According to claim 2,
Further comprising an anode electrode disposed on the non-display area,
Each of the first to third reference power supply voltage lines is connected to the anode electrode. According to claim 6,
Each of the first to third reference power supply voltage lines is formed of a source/drain metal layer,
The anode electrode and each of the first to third reference power supply voltage lines are electrically connected through a contact hole penetrating a planarization film disposed on the source/drain metal layer,
The cathode electrode and the anode electrode are electrically connected through a contact hole penetrating an electrode isolation layer disposed on the anode electrode. According to claim 6,
The anode electrode is entirely disposed above the first to third reference power supply voltage lines,
The anode electrode is connected to each of the first to third reference power supply voltage lines through a contact hole,
An organic light emitting display device in which different reference power supply voltages are supplied through the contact hole. According to claim 6,
The anode electrode is patterned and disposed above the first to third reference power supply voltage lines,
The organic light emitting display device of claim 1 , wherein different reference power supply voltages are supplied to each of the patterned anode electrodes.

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