KR102541937B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register that expands the operating range of a circuit by reducing limiting conditions of a clock and increasing an operating margin. In a shift register having a plurality of stages and outputting a scan pulse, each stage includes a set start signal. A set unit that sets the set node (Q) to the set voltage using a reset unit that resets the set node (Q) to the reset voltage using a reset start signal, and a state of the set node (Q) It is connected between an output unit for outputting one of the plurality of output clock signals as a scan pulse or a carry pulse, a clock transmission line for transmitting a clear clock pulse, and a reset node (QB). The capacitor C, which applies the clear clock pulse to the reset node QB, is turned on or turned off according to the voltage of the set node Q, and when turned on, the second discharge voltage VSS2 is turned on or turned off according to the voltage of the first switching element Tr1 supplying to the reset node QB and the voltage of the reset node QB, and when turned on, the third discharge voltage or another stage and a clear switching unit for supplying a scan pulse or carry pulse output from the terminal to a set node Q, wherein the clear switching unit is serially connected between the set node Q and the third voltage terminal for discharging. Turned on or turned off according to the voltage of the reset node Qb, and supplying the third discharge voltage or a scan pulse or carry pulse output from another stage to the set node Q when turned on A clear switching element and a third clear switching element (T3c) which is turned on or turned off according to the voltage of the set node (Q) and supplies a second charging voltage to the connection node of the first and second clear switching elements when turned on. ) is composed of.

Description

shift register {Shift register}

The present invention relates to a gate driver of a display device, and more particularly, to a shift register that widens the operating range of a circuit by reducing limiting conditions of a clock and increasing an operating margin.

A typical liquid crystal display device displays an image by adjusting light transmittance of liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which pixel regions are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device.

Generally, as shown in FIG. 1, a liquid crystal display device includes a liquid crystal panel 2 displaying an image and a gate driver 6 driving gate lines GL1 to GLn of the liquid crystal panel 2. And, the data driver 4 driving the data lines DL1 to DLm of the liquid crystal panel 2 and the image data RGB input from the outside are aligned and supplied to the data driver 4, and the gate and a timing controller 8 generating data control signals GCS and DCS to control the gate and data drivers 6 and 4 respectively.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel area defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm and connected to the thin film transistor. and a liquid crystal capacitor Clc. The liquid crystal capacitor Clc is composed of a pixel electrode connected to the thin film transistor and a common electrode disposed with the pixel electrode and the liquid crystal interposed therebetween. The thin film transistor supplies image signals from respective data lines DL1 to DLm to pixel electrodes in response to scan pulses from respective gate lines GL1 to GLn.

The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage SVcom applied to the common electrode, and adjusts the light transmittance by changing the arrangement of liquid crystal molecules according to the difference voltage. Implement gradation. In this case, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode of the thin film transistor and the gate line GL.

The data driver 4 receives data control signals (DCS) from the timing controller 8, for example, a source start signal (SSP; Source Start Pulse), a source shift clock (SSC; Source Shift Clock), and a source output input. Aligned data from the timing controller 8 is converted into an analog voltage, that is, a video signal, using a Source Output Enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data through the timing controller 8 according to the SSC, and then transmits a scan pulse to each gate line GL1 to GLn in response to the SOE signal. A video signal corresponding to one horizontal line is supplied to each of the data lines DL1 to DLm at each horizontal period.

The gate driver 6 sequentially drives each of the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8 . Specifically, the gate driver 4 includes a gate start signal (GSP), which is a gate control signal (GCS), a gate shift clock (GSC), and a gate output enable (GOE) signal. and the like are used to sequentially supply scan pulses of the gate high voltage (VGH) level to each of the gate lines GL1 to GLn. In addition, the gate low voltage is supplied during the remaining period when the scan pulse is not supplied.

The timing controller 8 controls the data driver 4 and the gate driver 6 respectively according to external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, and DE. Specifically, the timing controller 8 aligns image data RGB input from the outside to suit driving of the liquid crystal panel 2 and supplies the data driver 4 with the arrangement. In addition, the gate control signal (GCS) and the data control signal ( DCS) is generated and supplied to the gate driver 6 and the data driver 4, respectively.

The gate driver 6 includes a shift register to sequentially output scan pulses as described above.

The shift register includes a plurality of stages that sequentially output scan pulses to each of the gate lines GL1 to GLn based on a plurality of clock pulses provided from a timing controller.

A conventional stage includes a node controller for controlling charging and discharging states of a set node and a reset node, a pull-up switching element outputting a scan pulse according to the signal state of the set node, and a signal state of the reset node. A pull-down switching element outputting a discharge voltage is provided.

Here, the set node and the reset node are alternately charged and discharged. Specifically, when the set node is in a charged state, the reset node maintains a discharged state, and when the reset node is in a charged state, the set node will remain discharged.

At this time, when the set node is in a charged state, a scan pulse is output from the pull-up switching device, and when the reset node is in a charged state, a discharge voltage is output from the pull-down switching device of the output unit.

The scan pulse output from the pull-up switching element and the discharge voltage output from the pull-down switching element are supplied to the corresponding gate line.

Here, the gate electrode of the pull-up switching element is connected to the set node, the drain electrode is connected to the clock line to which the clock pulse is applied, and the source terminal is connected to the gate line. The clock pulse periodically has a high state and a low state and is supplied to the drain terminal of the pull-up switching device. At this time, the pull-up switching device outputs one of high-state clock pulses input every cycle at a specific time point. The clock pulse output at this specific point in time is the scan pulse for driving the gate line.

This specific point in time refers to the point in time after the set node is charged. That is, the pull-up switching element scans a high-state clock pulse input at the specific time point (ie, the time point when the set node is charged) among clock pulses periodically and continuously input to its own drain terminal. will be output as And, as the set node is maintained in a discharge state until the next frame period starts after outputting the scan pulse, the pull-up switching device outputs a scan pulse once per frame. However, since the clock pulse is output several times during one frame period, even when the pull-up switching element is turned off, that is, even when the set node is discharged, the clock pulse is continuously input to the drain electrode of the pull-up switching element. do.

In other words, the pull-up switching element is turned on only once during one frame, and outputs a clock pulse input to its drain electrode as a scan pulse during this turn-on period.

Then, the pull-up switching element is turned off until the start of the next frame period. Accordingly, during this turned-off period, the pull-up switching element outputs it as a scan pulse no matter how much a clock pulse is input to its drain electrode. Can not. However, as a clock pulse is periodically applied to the drain electrode of the pull-up switching device, a coupling phenomenon occurs between the set node to which the gate electrode of the pull-up switching device is connected and the drain electrode of the pull-up switching device. Due to this coupling phenomenon, the set node is continuously charged with a predetermined voltage according to the clock pulse.

Then, the set node can be maintained in a charged state at any moment. That is, the set node may be maintained in a charged state at an undesirable timing. In this case, the set node may be maintained in a charged state twice or more during one frame period, and thereby the pull-up switching element may be turned on two or more times during one frame period. As a result, a multi-output phenomenon in which one stage outputs two or more scan pulses during one frame period may occur due to the coupling phenomenon as described above.

In this way, when one stage outputs two or more scan pulses during one frame period, the quality of an image displayed on the liquid crystal panel is degraded.

Therefore, recently, a shift register capable of preventing multiple outputs has been developed by periodically discharging the voltage of the set node according to the cycle of the clock pulse to prevent accumulation of unwanted voltage at the set node (Patent Application 10- 2013-0089997).

A description of the conventional shift register as described above is as follows.

2 is a diagram showing a conventional shift register, and FIG. 3 is a diagram showing a timing diagram of various signals supplied or output to each stage of FIG. 2 .

As shown in FIG. 2, a conventional shift register includes a number of stages (ST_n-2 to ST_n+4). The stages ST_n−2 to ST_n+4 shown in FIG. 2 correspond to some of the entire stages included in the shift register.

Each of the stages ST_n-2 to ST_n+4 includes an output terminal OT, and each of these stages ST_n-2 to ST_n+4 uses its own output terminal OT for one frame period. It outputs one scan pulse (SP_n-2 to SP_n+4).

Each stage (ST_n-2 to ST_n+4) uses a scan pulse to drive a gate line connected thereto, and controls the operation of stages located before and after it.

The stages output scan pulses sequentially, starting with the stage assigned the fastest number. For example, the n-2 th stage outputs the n-2 th scan pulse, then the n-1 th stage (ST_n-1) outputs the n-1 th scan pulse (SP_n-1), and then n The stage ST_n outputs the nth scan pulse SP_n.

Such a shift register may be embedded in a liquid crystal panel. That is, the liquid crystal panel has a display portion for displaying an image and a non-display portion surrounding the display portion, and the shift register is embedded in the non-display portion.

Each stage of the shift register configured as described above receives at least one of the first to eighth clock pulses CLK1 to CLK4 circulating with a sequential phase difference from each other.

As shown in FIG. 2, each stage (ST_n−2 to ST_n+4) may be supplied with two clock pulses having different phases among the first to eighth clock pulses CLK1 to CLK8. . At this time, each stage (ST_n-2 to ST_n+4) uses one of these two as a clear clock pulse to stabilize the output by periodically discharging the voltage of the set node, and uses the other one for generating a scan pulse. Used as output clock pulse. That is, among two clock pulses, a clock pulse with a faster phase is used as a clear clock pulse to stabilize the output by periodically discharging the voltage of the set node, and a clock pulse with a relatively late phase is used as an output for generating a scan pulse. used as a clock pulse. For example, the 8k+1th stage uses the seventh clock pulse (CLK_7) as a clear clock pulse and uses the first clock pulse (CLK_1) as an output clock pulse.

Each stage performs a set operation by receiving a scan pulse from the stage located in the previous stage from itself. For example, the n-th stage ST_n is set by receiving scan pulses from the n-p-th stage, where p may be 1 as shown in FIG. 2 .

However, since no stage exists immediately before the first and second stages (not shown), the first and second stages are set in response to the start pulse Vst.

Each stage performs a reset operation in response to a scan pulse from the next stage. That the stage is reset means that the stage is in a state in which output is impossible, that is, in a state in which the stage cannot output the clock pulse supplied to itself as a scan pulse. For example, the nth stage is reset in response to a scan pulse from the n+qth stage, where q may be 3 as shown in FIG. 2 .

Meanwhile, since no stage exists after the aforementioned dummy stages, these dummy stages may also be reset in response to a start pulse from the timing controller.

The configuration of each stage (ST_n-2 to ST_n+2) in the shift register configured as described above is described in more detail as follows.

FIG. 4 is a diagram showing the configuration of a conventional stage, and FIG. 4 is a diagram showing the configuration of any one stage in FIG. 2 .

As shown in FIG. 4, the nth stage ST_n includes a set start switching element Tr_S, a reset start switching element Tr_R, a pull-up switching element Tr_U1, a pull-down switching element Tr_D1, and a capacitor C ), a clear switching element Tr_C and a first switching element Tr1.

The set start switching element Tr_S is turned on or turned off according to the scan pulse (SP_n-1) from the n-1st stage (ST_n-1), which is the set start signal (STS), and is charged when turned on. The supply voltage (VDD) is supplied to the set node (Q).

The reset start switching element Tr_R is turned on or off according to the scan pulse (SP_n + 3) from the n + 3 th stage (ST_n + 3), which is the reset start signal (RTS). When turned on, the third discharge voltage VSS3 is supplied to the set node Q.

The pull-up switching device Tr_U1 is turned on or off according to the voltage of the set node Q, and supplies the output clock pulse O-CLK to the output terminal OT when it is turned on.

The pull-down switching device Tr_D1 is turned on or off according to the voltage of the reset node QB, and supplies the fourth discharge voltage VSS4 to the output terminal OT when it is turned on.

The capacitor C applies the clear clock pulse C-CLK to the reset node QB. Here, the clear clock pulse (C-CLK) can be any one of the first to eighth clock pulses (CLK_1 to CLK_8) shown in FIG. 3, and the output clock pulse (O-CLK) is the third clock pulse. When the pulse CLK_3, the clear clock pulse C-CLK may become the first clock pulse CLK_1.

The clear switching element Tr_C is turned on or off according to the voltage of the reset node QB, and supplies the first discharge voltage VSS1 to the set node Q when it is turned on.

The first switching element Tr1 is turned on or off according to the voltage of the set node Q, and when turned on, supplies the second discharge voltage VSS2 to the reset node QB.

In the set start signal STS, the output clock pulse O-CLK, and the clear clock pulse C-CLK described above, the generation time of the set start signal STS is the clear clock pulse C -CLK) and earlier than or equal to the output clock pulse O-CLK.

Therefore, in the conventional shift register, the clear switching device Tr_C is periodically turned on according to the clear clock pulse C-CLK periodically supplied to the reset node QB through the capacitor C. As such, the voltage of the set node Q is discharged to the first discharge voltage VSS1 in each turn-on period. Therefore, the voltage of the set node Q is prevented from rising due to the coupling phenomenon.

However, in order for the conventional stage to operate normally, the threshold voltage (Vth) of each switching element constituting the stage must have a positive (+) appropriately large value (in the case of a P-type switching element, a negative (-) )). However, there are variations in the characteristics of the switching elements constituting each stage, and there may be cases where the threshold voltage of some of the switching elements is biased in the negative (-) direction due to an increase in temperature or a cause other than temperature. can

In this way, when the threshold voltage (Vth) of the N-type switching element constituting each stage is biased in the negative (-) direction or the threshold voltage (Vth) of the P-type switching element is biased in the positive (+) direction, A multi-output defect of a scan pulse may occur or a non-output defect of a scan pulse may occur.

That is, when the threshold voltage of the clear switching element Tr_C is biased in the negative (-) direction, the clear switching element Tr_C is not completely turned off during the set period, so that the set node Q is charged. A scan pulse may not be output due to leakage of the voltage VDD. This phenomenon becomes more severe if the voltage of the reset node Qb, which is raised due to the coupling of the clock pulse, does not decay quickly.

In addition, in order to suppress an increase in the voltage of the set node Q due to the coupling of the clock pulse, the voltage of the reset node Qb needs to be maintained for a certain period of time. However, when the threshold voltage of the first switching element Tr1 is biased in the negative (-) direction, the first switching element Tr1 is not completely turned off during the reset period, and the reset node Qb ) The voltage cannot be maintained for a certain period of time.

The present invention is to solve this conventional problem, and the discharge voltage applied to the first switching element is greater than or equal to the discharge voltage applied to the reset unit, so that the threshold voltage of the clear switching unit and the first switching element An object of the shift register is to provide a shift register with a wide operation range of a circuit by not outputting a scan pulse or maintaining a reset node voltage for a certain period of time even when the shift register is deflected in the negative (-) direction.

The shift register according to the present invention for achieving the above object is a shift register having a plurality of stages and outputting a scan pulse, each stage for setting a set node (Q) using a set start signal. A set unit for setting a voltage, a reset unit for resetting the set node (Q) to a reset voltage using a reset start signal, and one of a plurality of output clock signals input according to the state of the set node (Q). It is connected between an output unit that outputs one clock signal as a scan pulse or a carry pulse, a clock transmission line that transmits a clock pulse for clearing, and a reset node (QB) to transmit the clear clock pulse to the reset node (QB). A capacitor (C) applied to the capacitor (C) and a first switching element that is turned on or turned off according to the voltage of the set node (Q) and supplies a second discharge voltage to the reset node (QB) when turned on. (Tr1) and is turned on or off according to the voltage of the reset node (QB), and when turned on, the third discharge voltage or a scan pulse or carry pulse output from another stage is transmitted to the set node (Q). The clear switching unit is connected in series between the set node Q and the third voltage terminal for discharging, and the clear switching unit is turned on or turned on according to the voltage of the reset node Qb. First and second clear switching elements supplying the third discharge voltage or the scan pulse or carry pulse output from another stage to the set node Q when turned off and turned on, and the voltage of the set node Q It is characterized in that it is configured to include a third clear switching element (T3c) that is turned on or turned off according to the turn-on state to supply a second charging voltage to the connection node of the first and second clear switching elements.

Here, the set unit is turned on or off according to the start pulse Vst or the scan pulse or carry pulse output from the previous stage, and when turned on, the scan pulse or carry pulse output from the previous stage, the start pulse ( Vst) or a switching element (Tr_S) supplying the first charging voltage to the set node (Q), and the reset unit is turned on or turned on according to a reset pulse or a scan pulse or carry pulse output from a later stage. and a switching element (TR_R) for applying a first discharge voltage to the set node (Q) when it is turned off and turned on, and the output unit is turned on or off according to the logic state of the set node (Q). , A pull-up switching element that receives one of a plurality of clock signals for output and outputs it as a scan pulse when turned on, and is turned on or off according to a control signal input from the outside, and when turned on, a fourth discharge voltage is output to the output terminal. It is characterized by having a scan pulse output unit having a pull-down switching element outputting as .

The output unit is turned on or off according to the logic state of the set node Q, and when turned on, receives one of a plurality of clock signals for output or a plurality of clock signals for carry and outputs it as a carry pulse. It is characterized by further comprising a carry signal output unit having a switching element and a pull-down switching element that is turned on or off according to a control signal input from the outside and outputs a fifth discharge voltage to an output terminal when turned on.

The second voltage for discharge is greater than or equal to the first voltage for discharge, and the first voltage for discharge is greater than or equal to the third voltage for discharge.

The set unit is turned on or off according to the start pulse Vst or the scan pulse or carry pulse output from the previous stage, and when turned on, the scan pulse, carry pulse, or start pulse Vst output from the previous stage or a switching element (Tr_S) for supplying the first charging voltage to the set node (Q), and the reset unit is turned on or off according to a reset pulse or a scan pulse or a carry pulse output from a later stage A switching element (TR_R) for applying a first discharge voltage to the set node (Q) when turned on is provided, and the output unit is turned on or off according to the logic state of the set node (Q), and is turned on a pull-up switching element that receives one of a plurality of clock signals for output and outputs it as a scan pulse, and is turned on or off according to the logic state of the reset node, and when turned on, a fourth discharge voltage is supplied to the output terminal It is characterized by having a scan pulse output unit having a pull-down switching device for outputting.

The first discharge voltage and the second discharge voltage are equal to each other, and the third discharge voltage and the fourth discharge voltage are equal to each other.

A source terminal of the switching element Tr_R of the reset unit and a source terminal of the first switching element Tr1 are connected to the first voltage for discharging or the second voltage for discharging, and the second clear switching of the clear switching unit The source terminal of the element T3b and the source terminal of the pull-down switching element of the carry pulse output unit are connected to the third voltage for discharge or the fifth voltage for discharge.

The output unit is turned on or off according to the logic state of the set node Q, and when turned on, receives one of a plurality of clock signals for output or a plurality of clock signals for carry and outputs it as a carry pulse. It is characterized by further comprising a carry signal output unit having a switching element and a pull-down switching element which is turned on or off according to the logic state of the reset node and outputs a fifth discharge voltage to an output terminal when turned on.

At a rising edge of the output clock pulse, the clear clock pulse has a high state or is a rising edge, and a duty ratio of the clear clock pulse is equal to or different from that of the output clock pulse.

The high section width of the clear clock pulse is smaller than the width of the high section of the output clock pulse.

The output unit includes a carry signal output unit, a first scan signal output unit, and a second scan signal output unit, and the carry signal output unit is turned on or off according to the logic state of the set node Q, and is turned on. a pull-up switching element that receives one clock signal from among a plurality of output clock signals and outputs it as a carry pulse, and is turned on or off according to the logic state of the reset node Qb, and when turned on, a fifth discharge voltage is provided with a pull-down switching device that outputs to an output terminal, and the first scan signal output unit is turned on or off according to the logic state of the set node Q, and when turned on, one clock signal among a plurality of output clock signals is provided. A first pull-up switching element that receives and outputs a scan pulse, and is turned on or off according to the logic state of the reset node Qb, and outputs a fourth discharge voltage to an output terminal when turned on. device, wherein the second scan signal output unit is turned on or off according to the logic state of the set node Q, and when turned on, among a plurality of clock signals for output, a clock signal different from that of the first scan signal output unit A second pull-up switching element that receives a clock signal and outputs it as a scan pulse, and is turned on or off according to the logic state of the reset node Qb, and outputs a fourth discharge voltage to an output terminal when turned on. It is characterized by having a pull-down switching element.

Instead of at least one pull-down switching element among the plurality of pull-down switching elements, the external control signal or reset node Qb is connected in series between the output terminal and the fourth or fifth voltage terminal for discharging. third and fourth pull-down switching elements that turn on or turn off according to the logic state of and supply the fourth or fifth discharge voltage to the output terminal when turned on, and turn according to the voltage of the set node Q It is characterized in that it is configured to include a fifth pull-down switching element that is turned on or turned off and supplies a second charging voltage (VC) to the connection node of the third and fourth pull-down switching elements when turned on.

It is characterized in that the voltage of the set node (Q) is inverted and applied to the gate terminal of at least one pull-down switching element among the plurality of pull-down switching elements through an inverter.

The set unit is connected in series between the set voltage input terminal and the set node Q and turned on or off according to the set start signal to supply the set voltage to the set node Q when turned on. and a second set of switching elements;

It is characterized by comprising a third set of switching elements that are turned on or turned off according to the voltage of the set node (Q) and supply a second charging voltage to the connection node of the first and second set switching elements when turned on. there is.

The reset unit is connected in series between the set node Q and the first voltage terminal for discharge, and is turned on or off according to the reset start signal, so that when turned on, the first discharge voltage is supplied to the set node Q. Connecting first and second reset switching elements supplying and discharging the set node Q, and turning on or off according to the voltage of the set node Q to turn on the first and second reset switching elements It is characterized in that it is configured with a third reset switching element for supplying the second charging voltage (VC) to the node.

It is characterized by further comprising an initialization unit that initializes the set node (Q) by an external initialization control signal.

The initialization unit is configured to include an initialization switching element that is turned on or turned off according to the external initialization control signal to supply the first discharge voltage to the set node to discharge the set node when turned on. .

The initialization unit is connected in series between the set node Q and the first discharge voltage terminal and is turned on or off according to the external initialization control signal to generate the first discharge voltage at the set node ( first and second initialization switching elements supplying power to Q) and discharging the set node Q, and turning on or off according to the voltage of the set node Q to turn on the first and second initialization switching devices It is characterized in that it is configured with a third initialization switching element for supplying the second charging voltage (VC) to the connection node of the element.

A second switching element is further provided between the set unit and the reset unit to be turned on or off according to the first charging voltage and to connect the set node and the reset unit when turned on. there is.

The output unit may further include a pull-down switching element controlled by a clock signal to supply a voltage for discharging to an output terminal when turned on.

The shift register according to the present invention having the above characteristics has the following effects.

First, even if the threshold voltage of the N-type switching element constituting the shift register is deflected in the negative (-) direction (in the case of a P-type switching element, the threshold voltage is in the positive (+) direction), the Q node Since leakage current is prevented, it is possible to suppress non-patent defects and multi-output defects of scan pulses.

Second, since no output and multi-output failures can be prevented as described above, the operation range of the circuit can be widened.

Third, since the width of the high section of the clear clock pulse may be smaller than the width of the high section of the output clock pulse, stress of the switching device may be reduced.

1 is a configuration circuit diagram showing a driving device of a general liquid crystal display device;
2 is a configuration diagram of a conventional shift register
3 is a timing diagram of various signals supplied or output to each stage of FIG. 2
4 is a circuit diagram of each stage of a conventional shift register.
5 is a conceptual configuration diagram of a shift register according to the present invention
6 is a circuit diagram of each stage of a shift register according to the first embodiment of the present invention;
7 is a timing diagram of a first embodiment of various signals supplied or output to each stage of FIG. 6;
8 is a timing diagram of a second embodiment of various signals supplied or output to each stage of FIG. 6;
9 is a circuit diagram of each stage of a shift register according to a second embodiment of the present invention.
10 is a circuit diagram of each stage of a shift register according to a third embodiment of the present invention.
11 is a circuit diagram of each stage of a shift register according to a fourth embodiment of the present invention.
12 is a circuit diagram of each stage of a shift register according to a fifth embodiment of the present invention.
13 is a circuit diagram of each stage of a shift register according to a sixth embodiment of the present invention.
14 is a circuit diagram of each stage of a shift register according to a seventh embodiment of the present invention.
15 is a circuit diagram of each stage of a shift register according to an eighth embodiment of the present invention.
16 is a circuit diagram of each stage of a shift register according to a ninth embodiment of the present invention.
17 is a circuit diagram of another embodiment of the set unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.
18 is a circuit diagram of another embodiment of the reset unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.
19 is a circuit diagram of another embodiment of the pull-down switching element of the output unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.
20 is a circuit diagram of another embodiment of the output unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.
21A to 21B are circuit diagrams of an embodiment of the inverter of FIG. 20
22A is a circuit diagram of a first embodiment of an initialization unit added to the circuit configuration of each stage of a shift register of each embodiment according to the present invention;
22B is a circuit diagram of a second embodiment of an initialization unit added to the circuit configuration of each stage of a shift register of each embodiment according to the present invention;

The shift register according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

5 is a conceptual configuration diagram of each stage of a shift register according to the present invention.

Each stage of the shift register according to the present invention, as shown in FIG. 5, uses a set start signal (start pulse or scan pulse or carry pulse output from the previous stage) to set the set node Q to the set voltage (start pulse). , the set unit 1 that sets the scan pulse or carry pulse output from the previous stage or the first charging voltage (VH), and the reset start signal (reset pulse or scan pulse or carry pulse output from the next stage) A reset unit (2) resetting the set node (Q) to a reset voltage (a first discharge voltage (VSS1) or a voltage (VL) opposite to the first charge voltage (VH)) using An output unit 3 that outputs one of a plurality of clock signals as a scan pulse or a carry pulse according to the state of the set node Q, and clock transmission that transmits a clear clock pulse (C-CLK) A capacitor (C) connected between a line and the reset node (QB) and applying the clear clock pulse (C-CLK) to the reset node (QB), and turned on according to the voltage of the set node (Q) Alternatively, the first switching element Tr1, which is turned off and supplies the second discharge voltage VSS2 to the reset node QB when turned on, and is turned on according to the voltage of the reset node QB. Alternatively, the clear switching unit 4 is turned off and supplies the third discharge voltage VSS3 to the set node Q when turned on.

Here, the clear switching unit 4 is connected in series between the set node Q and the third discharge voltage VSS3 and turned on or off according to the voltage of the reset node Qb. The first and second clear switching elements T3a and T3b supplying the third discharge voltage VSS3 to the set node Q when turned on, and turn on or turn on according to the voltage of the set node Q It is configured to include a third clear switching element (T3c) for supplying a second charging voltage (VC) to the connection node of the first and second clear switching elements (T3a, T3b) when turned off and turned on.

In the above, the start pulse and the reset pulse are pulse signals applied from the outside, and when the first stage and the clock pulse overlap, the start pulse is applied from the first stage to the next stage corresponding to the overlapping period, and the reset pulse When the last stage and the clock pulses overlap, the signal is applied from the last stage to the previous stage corresponding to the overlapping period.

In addition, when the shift register of the present invention is a shift register for bidirectional driving, the first charging voltage VH and the voltage VL opposite to the first charging voltage VH are used and can be changed for each frame.

6 is a circuit configuration diagram of each stage of the shift register according to the first embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the first embodiment of the present invention is shown in FIG.

That is, in FIG. 5 , the set unit 1 is turned on or off according to the start pulse Vst or the scan pulse Prev output from the previous stage, and when turned on, the scan output from the previous stage is turned on. A switching element (Tr_S) for supplying a pulse (Prev), a start pulse (Vst) or a first charging voltage (VH) to the set node (Q) is provided.

The reset unit 2 is turned on or off according to a reset pulse or a scan pulse (Next) output from a subsequent stage, and when turned on, the first discharge voltage (VSS1) is applied to the set node (Q). It is configured with a switching element (Tr_R) for applying.

The output unit 3 is turned on or off according to the logic state of the Q node, and when turned on, the pull-up switching element (Tu) receives one clock signal (O_CLK) among a plurality of output clock signals and outputs it as a scan pulse. ) and a scan signal output unit equipped with a pull-down switching element (Td) that is turned on or off according to a control signal (VD) input from the outside and outputs the fourth discharge voltage (VSS4) to an output terminal when turned on. it did

Here, the control signal (VD) is a pulse signal, and it is possible as long as the output pulse and the high period do not overlap. That is, an inverter output or clock pulse can be used.

And, the rest of the configuration is the same as in FIG.

Here, the clear clock pulse C-CLK applied to the capacitor C may be the same as or different from the output clock pulse. 6 illustrates that the clear clock pulse C-CLK is the first clock pulse CLK-1 and the output clock pulse O-CLK is the third clock pulse CLK-3.

Also, when the clear clock pulse C-CLK and the output clock pulse O-CLK are different, they may be output clock pulses of different stages or may have different phases or pulse widths.

For example, the output clock pulse may be a 4-phase or more cyclic clock pulse, and the clear clock pulse may be a 4-phase or more cyclic clock pulse having two or more pulses during one period.

In addition, a clock pulse of the same concept as described in FIG. 3 may be used.

FIG. 7 is a timing diagram of a first embodiment of various signals supplied or output to each stage of FIG. 6 .

The clear clock pulse C-CLK and the output clock pulse O-CLK may use two or more phase clock pulses, and in FIG. 7 , the clear clock pulse C-CLK and the output clock pulse O-CLK CLK) shows an example using an 8-phase clock pulse.

7, the first clock pulse CLK1 is used as the clear clock pulse C-CLK, and the second clock pulse CLK2 or the second clock pulse is used as the set start signal of the set unit 1. It is shown that the scan pulse output from the previous stage used as the output clock pulse is used, and the third clock pulse CLK3 is used as the output clock pulse O-CLK.

Here, the clear clock pulse C-CLK may use not only the first clock pulse CLK1 but also the second clock pulse CLK2 or the third clock pulse.

FIG. 8 is a timing diagram of a second embodiment of various signals supplied or output to each stage of FIG. 6 .

8 shows that the clear clock pulse (C-CLK) and the output clock pulse (O-CLK) are separately used and four-phase clock pulses are respectively used.

As shown in FIG. 8, at the rising edge of the output clock pulse O-CLK, the clear clock pulse C-CLK has a high state or has a rising edge. In the present invention, unlike the prior art, the position of the clear clock pulse is not limited. That is, the clear clock pulse C-CLK may be earlier or later than the set signal (time point when the set node Q is switched from low to high).

That is, a first clock pulse (()-CLK1) or a scan pulse output from a previous stage using the first clock pulse as an output clock pulse is used as the set start signal of the set unit 1 of FIG. It is shown that the second clock pulse O-CLK2 is used as the output clock pulse O-CLK, and the first clock pulse C-CLK1 is used as the clear clock pulse C-CLK.

Here, the duty ratio of each of the clear clock pulses C-CLK1 to C-CLK-4 may be different from that of the output clock pulses O-CLK1 to O-CLK4. That is, the width of the high section of each clear clock pulse (C-CLK1 - C-CLK-4) is smaller than the width of the high section of the output clock pulse (O-CLK1 - O-CLK4), so that the switching element of each stage can reduce stress

In FIG. 6 , the first charging voltage VH may be a always high voltage and may be DC power for at least one frame, and the second charging voltage VC may be a always high voltage. It may be a voltage having a high voltage while the set node Q is high. The first charging voltage VH and the second charging voltage VC may be the same.

In addition, the first discharge voltage VSS1, the second discharge voltage VSS2, the third discharge voltage VSS3, and the fourth discharge voltage VSS4 may be the same voltage or different voltages. .

Preferably, the second discharge voltage (VSS2) is greater than or equal to the first discharge voltage (VSS1) (VSS2 ≥ VSS1), and the first discharge voltage (VSS1) is the third discharge voltage (VSS3). ) can be greater than or equal to (VSS1 ≥ VSS3).

Each stage of the shift register according to the first embodiment of the present invention prevents scan pulses from not being output or multi-outputting of scan pulses even when the threshold voltages of the clear switching unit and the first switching element are biased in the negative (-) direction. can do.

That is, in FIG. 6, even if the threshold voltages of the first and second clear switching elements T3a and T3b are biased in the negative (-) direction, the third clear switching element is moved by the voltage of the set node Q. Since (T3c) is turned on and supplies the second charging voltage (VC) to the connection node of the first and second clear switching elements (T3a, T3b), the voltage charged in the set node (Q) is the first. It does not leak through the first and second clear switching devices T3a and T3b. Therefore, it is prevented that the scan pulse is not output.

In addition, the threshold voltage of the first switching element Tr1 is biased in the negative (-) direction, so that the first switching element Tr1 is fully is not turned off, the voltage at the reset node Qb may not be maintained for a certain period of time. However, in the present invention, since the second discharge voltage VSS2 is equal to or higher than the first discharge voltage VSS1, the voltage at the reset node Qb can be maintained for a predetermined time.

9 is a circuit diagram of each stage of the shift register according to the second embodiment of the present invention.

In the circuit configuration of each stage of the shift register according to the second embodiment of the present invention, in the circuit configuration of each stage of the shift register of the first embodiment of the present invention, the pull-down switching device Td is input to the gate electrode from the outside. It is not turned on or turned off according to the control signal (VD), but is turned on or turned off according to the voltage of the reset node (Qb), and outputs the fourth discharge voltage (VSS4) to the output terminal when turned on. . The rest of the circuit configuration of each stage of the shift register according to the second embodiment of the present invention is the same as that of each stage of the shift register of the first embodiment of the present invention.

In the second embodiment of the present invention, the third discharge voltage VSS3 may be a scan pulse (or carry pulse) of any one stage.

10 is a circuit diagram of each stage of the shift register according to the third embodiment of the present invention.

In the circuit configuration of each stage of the shift register according to the third embodiment of the present invention, in the circuit configuration of each stage of the shift register according to the second embodiment of the present invention, the first discharge voltage VSS1 and the second discharge voltage This is a case where the dedicated voltage VSS2 is the same and the third discharge voltage VSS3 and the fourth discharge voltage VSS4 are the same.

That is, the source terminal of the switching element Tr_R of the reset unit 2 and the source terminal of the first switching element Tr1 are both connected to the first discharge voltage VSS1, and the clear switching unit 4 The source terminal of the second clear switching element T3b of ) and the source terminal of the pull-down switching element Td of the output unit 3 are all connected to the fourth discharge voltage VSS4.

The rest of the circuit configuration of each stage of the shift register according to the third embodiment of the present invention is the same as that of each stage of the shift register according to the second embodiment of the present invention.

11 is a circuit configuration diagram of each stage of a shift register according to a fourth embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the fourth embodiment of the present invention, in the circuit configuration of FIG. 5, the output unit 3 outputs a scan signal and a scan signal output unit outputs a carry signal It is equipped with all signal outputs.

That is, in the circuit configuration of each stage of the shift register of the first embodiment of the present invention, a carry signal output unit is further provided.

The carry signal output unit is turned on or off according to the logic state of the set node Q, and when turned on, a pull-up switching element receiving one clock signal (O_CLK) among a plurality of output clock signals and outputting it as a carry pulse ( Tuc) and a pull-down switching element Tdc that is turned on or off according to the control signal VD2 input from the outside and outputs the fifth discharge voltage VSS5 to an output terminal when turned on.

Here, the control signals VD1 and VD2 may be signals that are opposite to the voltage of the set node Q.

And, the rest of the configuration is the same as in FIG.

12 is a circuit configuration diagram of each stage of a shift register according to a fifth embodiment of the present invention.

In the circuit configuration of each stage of the shift register according to the fifth embodiment of the present invention, in the circuit configuration of each stage of the shift register according to the fourth embodiment of the present invention, the pull-down switching element Td of the scan pulse output unit and the carry The pull-down switching element Tdc of the pulse output unit is not turned on or off according to the control signals VD1 and VD2 input from the outside, but is turned on or off according to the voltage of the reset node Qb. When turned on, the fourth discharge voltage VSS4 and the fifth discharge voltage VSS5 are output to output terminals, respectively. The rest of the circuit configuration of each stage of the shift register according to the fifth embodiment of the present invention is the same as that of each stage of the shift register according to the fourth embodiment of the present invention.

13 is a circuit diagram of each stage of a shift register according to a sixth embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the sixth embodiment of the present invention is the source of the switching element Tr_R of the reset unit 2 in the circuit configuration of each stage of the shift register according to the fifth embodiment of the present invention. terminal and the source terminal of the first switching element Tr1 are all connected to the first discharge voltage VSS1 or the second discharge voltage VSS2, and the second clear switching element of the clear switching unit 4 The source terminal of (T3b) and the source terminal of the pull-down switching element (Tdc) of the carry pulse output unit are both connected to the third voltage for discharge (VSS3) or the fifth voltage for discharge (Vss5).

In addition, in the circuit configuration of each stage of the shift register according to the fifth embodiment of the present invention, the pull-down switching element Td of the scan pulse output unit is turned on or off according to the control signal VD input from the outside, and when turned on The fourth discharge voltage (VSS4) is output to an output terminal, and the pull-down switching element (Tdc) of the carry pulse output unit is turned on or off according to the voltage of the reset node (Qb), and when turned on, the third discharge voltage (VSS4) is turned on. The dedicated voltage VSS3 or the fifth discharge voltage VSS5 is output to the output terminal.

The rest of the circuit configuration of each stage of the shift register according to the sixth embodiment of the present invention is the same as that of each stage of the shift register according to the fifth embodiment of the present invention.

14 is a circuit diagram of each stage of a shift register according to a seventh embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the seventh embodiment of the present invention is the same as that of the carry signal output unit and the carry signal output unit where the output unit 3 outputs the carry signal in the circuit configuration of FIG. A first scan signal output unit outputs a scan signal based on a clock pulse, and a second scan signal output unit outputs a scan signal based on a clock pulse different from the clock pulse of the first scan signal output unit.

That is, in the circuit configuration of each stage of the shift register of the fifth embodiment of the present invention, a second scan signal output unit is further provided.

That is, the output unit 3 includes a carry signal output unit, a first scan signal output unit, and a second scan signal output unit.

As shown in FIG. 14, the carry signal output unit is turned on or off according to the logic state of the set node Q, and when turned on, receives one clock signal O_CLK from among a plurality of output clock signals. A pull-up switching element (Tuc) that outputs a carry pulse and a pull-down switching element that is turned on or off according to the logic state of the reset node (Qb) and outputs the fifth discharge voltage (VSS5) to an output terminal when turned on. (Tdc).

The first scan signal output unit is turned on or off according to the logic state of the Q node, and when turned on, one clock signal (O_CLK) among a plurality of output clock signals (the same clock signal as the clock signal of the carry signal output unit) ) is supplied and output as a scan pulse, and is turned on or off according to the logical state of the reset node Qb, and when turned on, the fourth discharge voltage VSS4 is output to the output terminal. It is configured with a pull-down switching element (Td1) to.

The second scan signal output unit is turned on or off according to the logic state of the Q node, and when turned on, one clock signal (O_CLK) among a plurality of output clock signals (different from the clock signal of the first scan signal output unit) is turned on. clock signal) is supplied and outputs as a scan pulse, and is turned on or off according to the logical state of the reset node Qb, and outputs the fourth discharge voltage VSS4 when turned on. It is configured with a pull-down switching element (Td2) outputting to.

Here, the clock signal used in the second scan signal output unit is a clock signal having a later phase than the clock signal used in the first scan signal output unit. For example, in FIG. 7 or 8, if the clock signal used in the carry signal output unit and the first scan signal output unit is CLK_3, the clock signal used in the second scan signal output unit is CLK_4.

The rest of the circuit configuration of each stage of the shift register according to the seventh embodiment of the present invention is the same as that of each stage of the shift register according to the fifth embodiment of the present invention.

15 is a circuit diagram of each stage of a shift register according to an eighth embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the eighth embodiment of the present invention is, in FIG. 5, turned between the set unit 1 and the reset unit 2 according to the first charging voltage VH. - It is turned on or turned off, and when turned on, a second switching element (Tr2) connecting between the set node (Q) and the switching element (Tr_R) of the reset unit (2) is further provided.

That is, in FIG. 15, in FIG. 6, which is the circuit configuration of each stage of the shift register of the first embodiment of the present invention, the second Although it is shown that the switching element Tr2 is further provided, it is not limited thereto and can be applied to all embodiments described above.

Each stage of the shift register according to the eighth embodiment of the present invention consists of one node and two nodes.

16 is a circuit diagram of each stage of a shift register according to a ninth embodiment of the present invention.

The circuit configuration of each stage of the shift register according to the ninth embodiment of the present invention, in each embodiment described above, is turned on or off by the clock signal CLK6 in the output unit 3, and when turned on, the output terminal A pull-down switching element Tda supplying a discharge voltage (one of VSS1 to VSS5) may be further included.

In the circuit configuration of each stage of the shift register of each embodiment as described above, the pull-down switching elements of the set unit, the reset unit, and the output unit may be configured differently.

17 is a circuit configuration diagram of another embodiment of the set unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.

That is, instead of the switching element Tr-S of the set unit 1 of each embodiment, the set voltage (start pulse, scan pulse or carry pulse output from the previous stage, or first charging voltage (VH) ) It is connected in series between an input terminal and the set node Q and is turned on or off according to the set start signal (start pulse or scan pulse or carry pulse output from the previous stage), and when turned on, the set voltage is set to the set The first and second set switching elements T4a and T4b supplied to the node Q, and the first and second set switching elements when turned on or turned on according to the voltage of the set node Q It is configured to include a third set of switching elements T4c for supplying the second charging voltage VC to the connection nodes of T4a and T4b.

In each of the above embodiments, when the set unit 1 is composed of one switching element (Tr-S) and a start pulse, a scan pulse or a carry pulse output from a previous stage is used as the set voltage, and the When the threshold voltage of the switching element Tr_S is biased in the negative (-) direction, the switching element Tr_S is not completely turned off after the set period, and the voltage VDD charged at the set node Q is This leakage may cause the scan pulse not to be output.

However, in FIG. 17, even if the threshold voltages of the first and second set of switching elements T4a and T4b are biased in the negative (-) direction, the third set of switching elements is affected by the voltage of the set node Q. Since (T4c) turns on and supplies the second charging voltage (VC) to the connection node of the first and second set switching elements (T4a, T4b), the voltage charged in the set node (Q) is It does not leak through the first and second set of switching elements T4a and T4b. Therefore, it is prevented that the scan pulse is not output.

18 is a circuit configuration diagram of another embodiment of the reset unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.

That is, instead of the switching element Tr-R of the reset unit 2 of each embodiment, the reset start signal (reset It is turned on or off according to a pulse or a scan pulse or a carry pulse output from a later stage, and when it is turned on, the first discharge voltage VSS1 is supplied to the set node Q to discharge the set node Q. connection of the first and second reset switching elements T5a and T5b, which are turned on or off according to the voltage of the set node Q, and the first and second reset switching elements T5a and T5b are turned on when turned on. It is configured to include a third reset switching element T5c for supplying the second charging voltage VC to the node.

In each of the above embodiments, the reset unit 2 is composed of one switching element (Tr-R), and when the threshold voltage of the switching element (Tr_R) is deflected in the negative (-) direction, in a set period Since the switching element Tr_R is not completely turned off, the voltage charged in the set node Q leaks and a scan pulse may not be output.

However, in FIG. 18, even if the threshold voltages of the first and second reset switching devices T5a and T5b are biased in the negative (-) direction, the third reset switching device is affected by the voltage of the set node Q. Since (T5c) is turned on to supply the second charging voltage (VC) to the connection node of the first and second reset switching elements (T5a, T5b), the voltage charged in the set node (Q) is It does not leak through the first and second reset switching devices T5a and T5b. Therefore, it is prevented that the scan pulse is not output.

19 is a circuit configuration diagram of another embodiment of the pull-down switching element of the output unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention.

That is, instead of the pull-down switching element (Td, Tdc, Td1 or Td2) of the output unit 3 of each embodiment, the output terminal (SP_n, CP_N, SP_n + 1) and the fourth or fifth discharge voltage ( It is connected in series between VSS4 or VSS5) and is turned on or off according to the external control signal signal (VD, VD1 or VD2) or the logic state of the reset node (Qb), and when turned on, the fourth or fifth discharge The first and second pull-down switching elements T6a and T6b supply voltages VSS4 or VSS5 to the output terminal, and are turned on or off according to the voltage of the set node Q. It is configured to include a third pull-down switching element T6c for supplying the second charging voltage VC to the connection node of the second pull-down switching elements T6a and T6b.

In each of the above embodiments, the output unit 3 is composed of one pull-down switching element (Td, Tdc, Td1 or Td2), and the threshold voltage of the switching element (Td, Tdc, Td1 or Td2) is negative ( In the case of deflection in the direction of -), the switching element Tr_R is not completely turned off during the set period, so that the voltage of the output terminal leaks and the scan pulse may not be output.

However, in FIG. 19, even if the threshold voltages of the first and second reset switching devices T6a and T6b are biased in the negative (-) direction, the third pull-down switching is performed by the voltage of the set node Q. Since the device T6c is turned on and supplies the second charging voltage VC to the connection node of the first and second pull-down switching devices T6a and T6b, the voltage of the output terminal is 2 There is no leakage through the pull-down switching elements (T6a, T6b). Therefore, it is prevented that the scan pulse is not output.

On the other hand, in each of the above embodiments, instead of the control signal (VD, VD1 or VD2) input from the outside to the gate terminal of the pull-down switching element (Td, Tdc, Td1 or Td2) of the output unit 3, the inverter ( The voltage of the set node Q may be supplied to the gate terminal of the pull-down switching element Td, Tdc, Td1 or Td2 of the output unit 3 using an inverter.

20 is a circuit configuration diagram of another embodiment of the output unit in the circuit configuration of each stage of the shift register of each embodiment according to the present invention, and FIGS. 21A and 21B are circuit configuration diagrams of the embodiment of the inverter shown in FIG.

That is, as shown in FIG. 20, the voltage of the set node Q is supplied to the gate terminal of the pull-down switching element Td, Tdc, Td1 or Td2 of the output unit 3 through an inverter. can

As shown in FIG. 21A, the inverter includes first and second inverter switching elements Ia and Ib connected in series between a constant voltage (Vdd) terminal or a clock pulse (CLK(n)) terminal and a ground terminal (Vssb). The gate terminal and the source terminal of the first inverter switching element (Ia) are connected to the constant voltage (VDD) or clock pulse (CLK (n)) terminal, and the gate terminal of the second inverter switching element (Ib) is It is connected to the set node Q, and the connecting rods of the first and second inverter switching devices Ia and Ib are connected to gate terminals of the pull-down switching devices Td, Tdc, Td1 or Td2.

In addition, the configuration of the inverter is connected between the constant voltage (Vdd) terminal or clock pulse (CLK(n)) terminal and the A node (A node) as shown in FIG. )), a first inverter switching element Ia which is turned on or turned off according to turn-on and supplies the constant voltage Vdd or clock pulse CLK(n) to the A node, and the A node and the ground terminal A second inverter switching element (Ib) connected between (Vssb) and turned on or off according to the voltage of the set node (Q) to supply the ground voltage (Vssb) to the A node when turned on; and the constant voltage It is connected between the (Vdd) terminal or the clock pulse (CLK(n)) terminal and the output terminal (Vout) and is turned on or off according to the voltage of the node A. When turned on, the constant voltage (Vdd) or the clock pulse (CLK(n)) ) to the output terminal Vout, and is connected between the output terminal Vout and the ground terminal Vssb to turn on or turn on according to the voltage of the set node Q. It is configured to include a fourth inverter switching element (Id) for supplying the ground voltage (Vssb) to the output terminal (Vout) when turned off and turned on.

Here, the output terminal Vout is connected to the gate terminal of the pull-down switching element Td, Tdc, Td1 or Td2.

In addition, each embodiment of the present invention may further include an initialization unit that initializes the set node Q by an external control signal Init.

22A is a circuit diagram of a first embodiment of an initialization unit added to the circuit configuration of each stage of a shift register of each embodiment according to the present invention.

That is, the initialization unit according to the first embodiment of the present invention is turned on or off according to an external control signal (Init) and supplies the first discharge voltage (VSS1) to the set node (Q) when it is turned on. and an initialization switching element T0 for discharging the set node.

22B is a circuit diagram of a second embodiment of an initialization unit added to the circuit configuration of each stage of a shift register of each embodiment according to the present invention.

That is, the initialization unit according to the second embodiment of the present invention is connected in series between the set node Q and the first discharge voltage VSS1 and turned on or turned on according to the external control signal Init. first and second initialization switching elements T0a and T0b for discharging the set node Q by supplying the first discharge voltage VSS1 to the set node Q when turned off and turned on; A third initialization switching element that is turned on or off according to the voltage of the node Q and supplies a second charging voltage VC to a connection node of the first and second initialization switching elements T0a and T0b when turned on. (T0c).

As described above, when it is composed of one switching element T0 as shown in FIG. 22A, when the threshold voltage of the switching element T0 is deflected in the negative (-) direction, the switching element T0 during the set period. ) is not completely turned off, the voltage of the set node (Q) leaks and a scan pulse may not be output. However, as shown in FIG. Even if the threshold voltages of the second initialization switching devices T0a and T0b are biased in the negative (-) direction, the third initialization switching device T0c is turned on by the voltage of the set node Q, and the second initialization switching device T0c is turned on. Since the charging voltage VC is supplied to the connection node of the first and second full initialization switching elements T0a and T0b, the voltage of the set node Q is applied to the first and second initialization switching elements T0a and T0b. There is no leakage through T0b). Therefore, it is prevented that the scan pulse is not output.

The initialization unit may not be applied to a stage set by a start signal, but may be applied to a stage set by a scan pulse or a carry pulse output from a previous stage.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the technical field to which the present invention belongs that various substitutions, modifications, and changes are possible within a range that does not deviate from the technical spirit of the present invention. It will be clear to those who have knowledge of

1: set part 2: reset part
3: output unit 4: clear switching unit

Claims (20)

In a shift register having a plurality of stages and outputting scan pulses, each stage comprises:
a set unit for setting a set node Q to a set voltage using a set start signal;
A reset unit resetting the set node Q to a reset voltage using a reset start signal;
an output unit outputting one of a plurality of output clock signals or a plurality of carry clock signals as a scan pulse or a carry pulse according to the state of the set node Q;
a capacitor (C) connected between a clock transmission line for transmitting a clear clock pulse and a reset node (QB) and applying the clear clock pulse to the reset node (QB);
a first switching element (Tr1) that is turned on or turned off according to the voltage of the set node (Q) and supplies a second discharge voltage to the reset node (QB) when turned on;
It is turned on or turned off according to the voltage of the reset node (QB), and when it is turned on, a third discharge voltage or a scan pulse or a carry pulse output from an arbitrary stage is supplied to the set node (Q) It is configured with a clear switching unit,
The clear switching unit is connected in series between the set node Q and a third voltage for discharge supplying the third voltage for discharge, and is turned on or off according to the voltage of the reset node Qb to be turned on. first and second clear switching elements supplying the third discharge voltage or a scan pulse or a carry pulse output from another stage to the set node Q when turned on;
A third clear switching element (T3c) that is turned on or turned off according to the voltage of the set node (Q) and supplies a second charging voltage to the connection node of the first and second clear switching elements when turned on. shift register. According to claim 1,
The set unit is turned on or off according to the start pulse Vst or the scan pulse or carry pulse output from the previous stage, and when turned on, the scan pulse, carry pulse, or start pulse Vst output from the previous stage Or a switching element (Tr_S) for supplying the first charging voltage to the set node (Q),
The reset unit is turned on or off according to a reset pulse or a scan pulse or carry pulse output from a later stage, and when turned on, a switching element (TR_R) for applying a first discharge voltage to the set node (Q) to provide,
The output unit is turned on or off according to the logic state of the set node Q, and when turned on, a pull-up switching element receiving one of a plurality of clock signals for output and outputting it as a scan pulse, and A shift register having a scan pulse output unit having a pull-down switching element that is turned on or off according to a control signal and outputs a fourth discharge voltage to an output terminal when turned on. According to claim 2,
The output unit is turned on or off according to the logic state of the set node Q, and when turned on, receives one of a plurality of clock signals for output or a plurality of clock signals for carry and outputs it as a carry pulse. A shift register further comprising a carry signal output unit having a switching element and a pull-down switching element that is turned on or off according to a control signal input from the outside and outputs a fifth discharge voltage to an output terminal when turned on. According to claim 2 or 3,
The second voltage for discharge is greater than or equal to the first voltage for discharge, and the first voltage for discharge is greater than or equal to the third voltage for discharge. According to claim 1,
The set unit is turned on or off according to the start pulse Vst or the scan pulse or carry pulse output from the previous stage, and when turned on, the scan pulse, carry pulse, or start pulse Vst output from the previous stage Or a switching element (Tr_S) for supplying the first charging voltage to the set node (Q),
The reset unit is turned on or off according to a reset pulse or a scan pulse or carry pulse output from a later stage, and when turned on, a switching element (TR_R) for applying a first discharge voltage to the set node (Q) to provide,
The output unit is turned on or off according to the logic state of the set node Q, and when turned on, a pull-up switching element receiving one clock signal from among a plurality of output clock signals and outputting it as a scan pulse, and the reset node A shift register having a scan pulse output unit having a pull-down switching device that is turned on or off according to a logic state of the and outputs a fourth discharge voltage to an output terminal when turned on. According to claim 5,
The first voltage for discharge and the second voltage for discharge are equal to each other, and the third voltage for discharge and the fourth voltage for discharge are equal to each other. According to claim 5,
The output unit is turned on or off according to the logic state of the set node Q, and when turned on, receives one of a plurality of clock signals for output or a plurality of clock signals for carry and outputs it as a carry pulse. A shift register further comprising a carry pulse output unit including a switching element and a pull-down switching element that is turned on or off according to a logic state of the reset node and outputs a fifth discharge voltage to an output terminal when turned on. According to claim 7,
A source terminal of the switching element Tr_R of the reset unit and a source terminal of the first switching element Tr1 are connected to the first discharge voltage or the second discharge voltage,
A source terminal of the second clear switching element T3b of the clear switching unit and a source terminal of the pull-down switching element of the carry pulse output unit are connected to the third voltage for discharge or the fifth voltage for discharge. According to claim 1,
At a rising edge of the output clock signal, the clearing clock pulse has a high state or is a rising edge, and a duty ratio of the clearing clock pulse is equal to or different from that of the output clock signal. According to claim 9,
A shift register in which a width of a high section of the clearing clock pulse is smaller than a width of a high section of the output clock signal. According to claim 1,
The output unit includes a carry signal output unit, a first scan signal output unit and a second scan signal output unit,
The carry signal output unit is turned on or off according to the logic state of the set node Q, and when turned on, a pull-up switching element receiving one of a plurality of clock signals for output and outputting it as a carry pulse; A pull-down switching element that is turned on or off according to the logic state of the reset node (Qb) and outputs a fifth discharge voltage to an output terminal when turned on;
The first scan signal output unit is turned on or off according to the logic state of the set node Q, and receives one clock signal from among a plurality of output clock signals when turned on and outputs it as a scan pulse. device, and a first pull-down switching device that is turned on or turned off according to the logic state of the reset node (Qb) and outputs a fourth discharge voltage to an output terminal when turned on;
The second scan signal output unit is turned on or off according to the logic state of the set node Q, and receives a clock signal different from that of the first scan signal output unit among a plurality of clock signals for output when turned on. A second pull-up switching element outputting scan pulses and a second pull-down switching element that is turned on or off according to the logic state of the reset node Qb and outputs a fourth discharge voltage to an output terminal when turned on. One shift register. According to any one of claims 5 and 7,
Instead of at least one pull-down switching element among the pull-down switching elements, it is serially connected between the output terminal and the fourth or fifth voltage terminal for discharging to an external control signal or a logic state of the reset node Qb. third and fourth pull-down switching elements that are turned on or off according to the turn-on state to supply the fourth or fifth discharge voltage to the output terminal;
A fifth pull-down switching element which is turned on or off according to the voltage of the set node Q and supplies a second charging voltage VC to the connection nodes of the third and fourth pull-down switching elements when turned on. A shift register configured to include. According to any one of claims 5 and 7,
A shift register in which the voltage of the set node (Q) is inverted and applied to the gate terminal of at least one of the pull-down switching elements through an inverter. According to claim 1,
The set unit is connected in series between a set voltage input terminal and the set node Q and turned on or off according to the set start signal to supply a set voltage to the set node Q when turned on. 2 sets of switching elements;
A shift register comprising a third set switching element that is turned on or turned off according to the voltage of the set node Q and supplies a second charging voltage to a connection node of the first and second set switching elements when turned on. . According to claim 1,
The reset unit is connected in series between the set node Q and the first discharge voltage terminal and is turned on or off according to the reset start signal to supply the first discharge voltage to the set node Q when turned on. first and second reset switching elements for discharging the set node Q;
A third reset switching element that is turned on or turned off according to the voltage of the set node (Q) and supplies a second charging voltage (VC) to the connection node of the first and second reset switching elements when turned on Configured shift register. According to claim 1,
A shift register further comprising an initialization unit that initializes the set node (Q) by an external initialization control signal. 17. The method of claim 16,
The shift register comprising an initialization switching element that is turned on or turned off according to the external initialization control signal and supplies a first discharge voltage to the set node to discharge the set node when turned on. 17. The method of claim 16,
The initialization unit is connected in series between the set node Q and the first discharge voltage terminal and is turned on or off according to the external initialization control signal, and when turned on, the first discharge voltage is applied to the set node Q First and second initialization switching elements supplying to and discharging the set node (Q);
A third initialization switching element that is turned on or off according to the voltage of the set node Q and supplies a second charging voltage VC to a connection node of the first and second initialization switching elements when turned on Configured shift register. According to claim 1,
The shift register further comprising a second switching element between the set unit and the reset unit that is turned on or off according to a first charging voltage and connects the set node and the reset unit when turned on. According to any one of claims 2, 4, 8, 11,
The output unit further includes a pull-down switching device controlled by a clock signal to supply a voltage for discharging to an output terminal when turned on.

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