KR102557894B1 - Scan driver and display device including the same - Google Patents

Abstract

The scan driver includes first through nth scan signal output circuits respectively connected to the first through nth scan lines. Each of the first to nth scan signal output circuits includes a driving circuit and a sampling-buffer circuit. The driving circuit applies a first driving signal to a first driving node and a second driving signal to a second driving node based on a scan input signal, a first clock signal, a display on signal, and an on level voltage corresponding to a scan start signal or a previous scan signal. The sampling buffer-circuit outputs a scan-on signal or a scan-off signal through an output node based on the second clock signal, off-level voltage, first driving signal, and second driving signal, and stores a sampling voltage for providing a scan-on signal to a scan line to be sensed based on the sensing-on signal.

Description

Scan driver and display device including the same {SCAN DRIVER AND DISPLAY DEVICE INCLUDING THE SAME}

The present invention relates to a display device. More specifically, the present invention relates to a scan driver and a display device including the same.

In general, a display device includes a display panel, a scan driver, a data driver, a timing controller, and the like. At this time, the scan driver provides a scan signal (ie, composed of a scan-on signal and a scan-off signal) to the display panel through scan lines. To this end, the scan driver includes sequentially connected scan signal output circuits, and each of the scan signal output circuits is composed of oxide thin film transistors and operates. Recently, a display device compensates for deterioration or change in characteristics (eg, change in characteristics due to temperature) of a driving transistor by sensing a threshold voltage or mobility of a driving transistor included in a pixel circuit. At this time, since the scan schemes for the display operation, the mobility sensing operation, and the threshold voltage sensing operation are different from each other (for example, the mobility sensing operation is performed only for one scan line in a porch period, and one horizontal period of the threshold voltage sensing operation is different from one horizontal period of the display operation), the internal structure of a scan driver for performing the above operations is complicated. Accordingly, conventional display devices do not include a scan driver (i.e., built-in scan driver) directly formed on the display panel during a thin film transistor process of forming thin film transistors on the display panel, but include a scan driver (i.e., external scan driver) bonded to the display panel in the form of an integrated circuit or mounted externally.

An object of the present invention is to provide a scan driver having a simple internal structure that can be directly formed on a display panel during a thin film transistor process for forming thin film transistors in a display panel while selectively providing scan signals to a display panel in a progressive scan method or a random scan method according to a display operation, a mobility sensing operation, and a threshold voltage sensing operation.

Another object of the present invention is to provide a display device manufactured with a low manufacturing cost and a simple manufacturing process by including the scan driver.

However, the object of the present invention is not limited to the above-mentioned objects, and may be expanded in various ways without departing from the spirit and scope of the present invention.

In order to achieve one object of the present invention, a scan driver according to embodiments of the present invention may include first to nth scan signal output circuits respectively connected to first to nth scan lines (where n is an integer greater than or equal to 2). At this time, each of the first to n-th scan signal output circuits applies a first driving signal to a first driving node based on a scan start signal or a scan input signal corresponding to a previous scan signal, a first clock signal, a display on signal, and an on level voltage, and applies a second driving signal to a second driving node, and outputs a scan on signal or a scan off signal through a scan signal output node based on a second clock signal, an off level voltage, the first drive signal, and the second drive signal, and based on the sensing on signal A sampling-buffer circuit for storing a sampling voltage for providing the scan-on signal to a scan line subject to mobility sensing may be included.

According to an embodiment, when the display device is in a power-on state, one frame includes a display period and a porch period, the display device performs a display operation in the display period, the display device performs a mobility sensing operation in the porch period, and in the power-on state, the display device may repeatedly perform the frame.

According to an embodiment, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines in the display period, and in the display period, an m th scan signal output circuit (where m is an integer greater than or equal to 1 and less than or equal to n) may store the sampling voltage, and in the porch period, the m th scan signal output circuit may apply the scan on signal to the m th scan line.

According to an embodiment, when the display device is in a power off state, the frame includes a threshold voltage sensing section, the display device performs a threshold voltage sensing operation in the threshold voltage sensing section, and in the power off state, the display device may perform the frame a predetermined number of times.

According to an embodiment, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines in the threshold voltage sensing period.

According to an embodiment, one horizontal period of the threshold voltage sensing period may be longer than one horizontal period of the display period.

In an exemplary embodiment, the driving circuit may include a third transistor including a first terminal receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to the first node, a first terminal connected to the on-level voltage, a fourth transistor including a second terminal connected to the first node, and a gate terminal receiving the scan input signal, a fifth transistor including a first terminal connected to the second node, a second terminal connected to the on-level voltage, and a gate terminal receiving the first clock signal, the second node A sixth transistor including a first terminal connected to the on-level voltage and a gate terminal connected to the second node, a seventh transistor including a first terminal connected to the first node, a second terminal connected to the first node, and a gate terminal receiving the second clock signal, an eighth transistor including a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to a connection signal output node, and a gate terminal connected to the second node, a first terminal connected to the first node, and a second terminal connected to the connection signal output node; Then, a ninth transistor including a gate terminal receiving a connection signal, a first capacitor including a first terminal connected to the first node and a second terminal connected to the connection signal output node, a first terminal receiving the second clock signal, a second terminal connected to the connection signal output node, and a tenth transistor including a gate terminal connected to the first node, a first terminal connected to the connection signal output node, a second terminal connected to an auxiliary off-level voltage having a voltage level lower than the off-level voltage, and a gate terminal connected to the second node. A 11th transistor, a second capacitor including a first terminal connected to the second node and a second terminal connected to the auxiliary off-level voltage, a 12th transistor including a first terminal connected to the first node, a second terminal connected to the first driving node, and a gate terminal receiving the display-on signal, and a thirteenth transistor including a first terminal connected to the second node, a second terminal connected to the second driving node, and a gate terminal receiving the display-on signal.

According to an embodiment, the sampling-buffer circuit includes a 14th transistor including a first terminal receiving the subsequent connection signal, a second terminal connected to a sampling node and a gate terminal receiving the sensing-on signal, a third capacitor including a first terminal connected to the sampling node and a second terminal connected to the auxiliary off-level voltage, a first terminal including a sensing clock signal, a 15th transistor including a second terminal connected to the first driving node and a gate terminal connected to the sampling node, and a first connected to the second driving node. A sixteenth transistor including a second terminal and a gate terminal receiving the sensing clock signal, a seventeenth transistor including a first terminal connected to the second terminal of the sixteenth transistor, a second terminal connected to the off-level voltage, and a gate terminal connected to the sampling node, a first transistor including a first terminal receiving the second clock signal, a second terminal connected to the scan signal output node, and a gate terminal connected to the first driving node, and a first terminal connected to the scan signal output node and a gate terminal connected to the off-level voltage. A second transistor including two terminals and a gate terminal connected to the second driving node may be included.

According to an embodiment, the sampling-buffer circuit may further include a fourth capacitor including a first terminal receiving the sensing-on signal and a second terminal connected to the sampling node.

According to an embodiment, the sampling-buffer circuit may further include a fifth capacitor including a first terminal connected to the first driving node and a second terminal connected to the scan signal output node.

According to an embodiment, the sampling-buffer circuit may further include a sixth capacitor including a first terminal connected to the second driving node and a second terminal connected to the off-level voltage.

According to an embodiment, a rising edge of the second clock signal is positioned adjacent to a falling edge of the first clock signal, a rising edge of the first clock signal is positioned adjacent to a falling edge of the second clock signal, and an active period of the first clock signal and an active period of the second clock signal may not overlap each other.

According to an embodiment, when the display device is in a power-on state, one frame may include a display period and a porch period, the display-on signal may be activated and the sensing clock signal may be deactivated in the display period, and the first clock signal, the second clock signal, and the sensing clock signal may be activated during an inactivation period of the display-on signal in the porch period.

According to an embodiment, the sensing on signal may be activated or deactivated in an activation period of the subsequent connection signal within the display period.

According to an embodiment, when the display device is in a power off state, one frame may include a threshold voltage sensing period, and both the display on signal and the sensing clock signal may be activated during the threshold voltage sensing period.

In order to achieve another object of the present invention, a display device according to embodiments of the present invention may include a display panel including a plurality of pixel circuits, a data driver providing data signals to the display panel, a scan driver providing scan signals to the display panel, and a timing controller controlling the data driver and the scan driver. The scan driver may include first to nth scan signal output circuits connected to first to nth scan lines, respectively. At this time, each of the first to n-th scan signal output circuits applies a first driving signal to a first driving node based on a scan start signal or a scan input signal corresponding to a previous scan signal, a first clock signal, a display on signal, and an on level voltage, and applies a second driving signal to a second driving node, and outputs a scan on signal or a scan off signal through a scan signal output node based on a second clock signal, an off level voltage, the first drive signal, and the second drive signal, and based on the sensing on signal A sampling-buffer circuit for storing a sampling voltage for providing the scan-on signal to a scan line subject to mobility sensing may be included.

According to an embodiment, in a power-on state, one frame includes a display section and a porch section, a display operation is performed in the display section, a mobility sensing operation is performed in the porch section, and the frame can be repeatedly performed in the power-on state.

According to an embodiment, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines in the display period, and in the display period, an m th scan signal output circuit (where m is an integer greater than or equal to 1 and less than or equal to n) may store the sampling voltage, and in the porch period, the m th scan signal output circuit may apply the scan on signal to the m th scan line.

According to an embodiment, when the power is off, the frame may include a threshold voltage sensing section, a threshold voltage sensing operation may be performed in the threshold voltage sensing section, and the frame may be performed a preset number of times in the power off state.

According to an embodiment, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines in the threshold voltage sensing period.

A scan driver according to embodiments of the present invention provides a scan signal to a display panel to perform a threshold voltage sensing operation when the display device is in a power-off state, and provides a scan signal to the display panel so that a display operation and a mobility sensing operation are repeatedly performed in every frame when the display device is in a power-on state. While sequentially applying a scan on signal to perform a display operation in a display period of one frame to scan lines, a scan line to be subjected to mobility sensing is selected, and a target scan line for mobility sensing is to be performed. By applying a scan-on signal to a scan line subject to mobility sensing in the value period, a scan signal may be selectively provided to the display panel in a progressive scan method or a random scan method according to the display operation, mobility sensing operation, and threshold voltage sensing operation performed by the display device, while having a simple internal structure that can be directly formed on the display panel during a thin film transistor process for forming thin film transistors in the display panel.

By including the scan driver, the display device according to the exemplary embodiments of the present invention can be manufactured with a low manufacturing cost and a simple manufacturing process.

However, the effects of the present invention are not limited to the above-described effects, and may be variously extended within a range that does not deviate from the spirit and scope of the present invention.

1 is a block diagram illustrating a scan driver according to embodiments of the present invention.
FIG. 2 is a block diagram illustrating a scan signal output circuit included in the scan driver of FIG. 1 .
FIG. 3 is a circuit diagram illustrating an example of the scan signal output circuit of FIG. 2 .
FIG. 4 is a diagram illustrating an operation mode of the scan signal output circuit of FIG. 2 .
FIG. 5 is a timing diagram for explaining how the scan signal output circuit of FIG. 2 generates a scan signal for a display operation.
6 is a circuit diagram for explaining how the scan signal output circuit of FIG. 2 generates a scan signal for a display operation.
FIG. 7 is a timing diagram for explaining how the scan signal output circuit of FIG. 2 selects a scan line to be subjected to mobility sensing, which is a target of a mobility sensing operation.
FIG. 8 is a circuit diagram for explaining how the scan signal output circuit of FIG. 2 selects a scan line to be subjected to mobility sensing, which is a target of a mobility sensing operation.
9 is a timing diagram illustrating how the scan signal output circuit of FIG. 2 generates a scan signal for a mobility sensing operation.
10 is a circuit diagram for explaining how the scan signal output circuit of FIG. 2 generates a scan signal for a mobility sensing operation.
FIG. 11 is a timing diagram for explaining how the scan signal output circuit of FIG. 2 generates a scan signal for a threshold voltage sensing operation.
FIG. 12 is a circuit diagram for explaining how the scan signal output circuit of FIG. 2 generates a scan signal for a threshold voltage sensing operation.
13 is a block diagram illustrating a display device according to example embodiments.
14 is a block diagram illustrating an electronic device according to embodiments of the present invention.
15 is a diagram illustrating an example in which the electronic device of FIG. 14 is implemented as a smart phone.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

1 is a block diagram showing a scan driver according to embodiments of the present invention, FIG. 2 is a block diagram showing a scan signal output circuit included in the scan driver of FIG. 1, FIG. 3 is a circuit diagram showing an example of the scan signal output circuit of FIG. 2, and FIG. 4 is a diagram showing an operation mode of the scan signal output circuit of FIG.

1 to 4 , the scan driver 100 may include first to nth (where n is an integer greater than or equal to 2) scan signal output circuits 200(1), ..., 200(n). In this case, each of the first to nth scan signal output circuits 200(1), ..., 200(n) may include a driving circuit 220 and a sampling-buffer circuit 240.

The scan driver 100 may provide scan signals SCAN[1], ..., SCAN[n] (that is, composed of a scan on signal and a scan off signal) to the display panel through the first to nth scan lines SL(1), ..., SL(n). Accordingly, the scan driver 100 includes the first to nth scan signal output circuits 200(1), ..., 200(n), the first to nth scan signal output circuits 200(1), ..., 200(n) are sequentially connected to each other, and the first to nth scan signal output circuits 200(1), ..., 200(n) include the first to nth scan lines SL(1), ..., SL(n)), respectively. At this time, the scan driver 100 may selectively provide scan signals (SCAN[1], ..., SCAN[n]) to the display panel in a progressive scan method or a random scan method according to the display operation, the mobility sensing operation, and the threshold voltage sensing operation performed by the display device. That is, when the display device is in a power-off state, the scan driver 100 may provide scan signals (SCAN[1], ..., SCAN[n]) to the display panel so that the display device may perform a threshold voltage sensing operation, and may provide scan signals (SCAN[1], ..., SCAN[n]) to the display panel when the display device is in a power-on state so that the display device may repeatedly perform a display operation and a mobility sensing operation every frame. Specifically, the scan driver 100 provides scan signals (SCAN[1], ..., SCAN[n]) to the display panel in a progressive scan manner in a threshold voltage sensing period in which the threshold voltage sensing operation is performed in a power-off state of the display device, and provides scan signals (SCAN[1], ..., SCAN[n]) in a progressive scan method in a display period in which a display operation is performed in a power-on state of the display device, and performs a mobility sensing operation in a power-on state of the display device. In the porch section where this is performed, scan signals (SCAN[1], ..., SCAN[n]) may be provided to the display panel in a random scan manner. That is, as shown in FIG. 4 , the display device may repeatedly operate in the display mode 310 and the mobility sensing mode 320 in the power-on state, and operate in the threshold voltage sensing mode 330 in the power-off state.

When the display device operates in the display mode 310, the scan driver 100 may sequentially apply a scan on signal to the first to n th scan lines SL(1), ..., SL(n) in response to the scan start signal STV. For example, after the first scan signal output circuit 200(1) outputs the scan on signal, the second scan signal output circuit 200(2) outputs the scan on signal, after the second scan signal output circuit 200(2) outputs the scan on signal, the third scan signal output circuit 200(3) outputs the scan on signal, and after the n−1th scan signal output circuit 200(n−1) outputs the scan on signal, the nth scan signal The output circuit 200 (n) may output a scan on signal. Meanwhile, when the display device operates in the display mode 310, the scan driver 100 may select a scan line subject to mobility sensing on which a mobility sensing operation is to be performed in the mobility sensing mode 320 of the display device. Then, when the display device operates in the mobility sensing mode 320, the scan driver 100 may output a scan on signal to the mth scan line SL(m) selected as the mobility sensing target scan line. That is, the display device may sense the mobility of driving transistors inside the pixel circuits connected to one scan line (eg, the m th scan line SL(m)) per frame in the mobility sensing mode 320. In this way, the scan driver 100 sequentially applies the scan on signal to the first to n th scan lines SL(1), ..., SL(n) in the display period of one frame, while the first to n th scan lines in the porch period of the frame The scan-on signal may be applied only to one scan line (eg, the m-th scan line SL(m)) among the SL(1), ..., SL(n). When the display device operates in the threshold voltage sensing mode 330, the scan driver 100 may sequentially apply the scan-on signal to the first to n-th scan lines SL(1), ..., SL(n) in response to the scan start signal STV. After the first scan signal output circuit 200(1) outputs the scan on signal, the second scan signal output circuit 200(2) outputs the scan on signal, after the second scan signal output circuit 200(2) outputs the scan on signal, the third scan signal output circuit 200(3) outputs the scan on signal, and after the n−1th scan signal output circuit 200(n−1) outputs the scan on signal, the nth scan signal output circuit 200 (n)) may output a scan on signal However, one horizontal period when the display device operates in the threshold voltage sensing mode 330 may be longer than one horizontal period when the display device operates in the display mode 310.

As described above, the scan driver 100 selects the mobility sensing target scan line SL(m) on which the mobility sensing operation will be performed in the display section of one frame, and applies a scan on signal to the mobility sensing target scan line SL(m) in the porch section of the corresponding frame. By doing so, the internal structure can be simplified compared to the prior art, and thus, during the thin film transistor process of forming the thin film transistor on the display panel, it can be directly formed on the display panel. To this end, as shown in FIG. 2, each of the scan signal output circuits 200(1), ..., 200(n) may include a driving circuit 220 configured of oxide thin film transistors and a sampling-buffer circuit 240. Specifically, the driving circuit 220 may apply the first driving signal Q1 to the first driving node Q1N and apply the second driving signal Q2 to the second driving node Q2N based on the scan input signal corresponding to the scan start signal STV or the previous scan signal SCAN[m−1], the first clock signal CLK1, the display on signal DIS_ON, and the on level voltage VGH. The sampling-buffer circuit 240 may output a scan signal SCAN[m] (ie, a scan on signal or a scan off signal) through a scan signal output node ON based on the second clock signal CLK2, off level voltage VGL, first driving signal Q1 and second driving signal Q2, and may store a sampling voltage for providing a scan on signal to a scan line to be sensed based on the sensing on signal SEN-ON. As such, each of the scan signal output circuits 200 (1), ..., 200 (n) is composed of oxide thin film transistors and operates, and in each of the scan signal output circuits 200 (1), ..., 200 (n), the driving circuit 220 and the sampling-buffer circuit 240 may be connected to each other through the first driving node Q1N and the second driving node Q2N. When the display device is in a power-on state, one frame includes a display period and a porch period, the display device performs a display operation in the display period, and a mobility sensing operation is performed in the porch period. In this case, the first to nth scan signal output circuits 200(1), ..., 200(n) sequentially apply the scan on signal to the first to nth scan lines SL(1), ..., SL(n) in the display period of one frame, and the mth scan signal output circuit 200(m) among the first to nth scan signal output circuits 200(1), ..., 200(n) may store the sampling voltage. . Then, in the porch section of the corresponding frame, the mth scan signal output circuit 200(m) may apply a scan on signal to the mth scan line SL(m). When the display device is in a power-off state, one frame includes a threshold voltage sensing period, the display device performs a threshold voltage sensing operation in the threshold voltage sensing period, and the display device may perform the frame (i.e., threshold voltage sensing period) a predetermined number of times (e.g., once) in a power-off state of the display device. At this time, in the threshold voltage sensing period, the first to n th scan signal output circuits 200(1), ..., 200(n) may sequentially apply scan on signals to the first to nth scan lines SL(1), ..., SL(n), and one horizontal period of the threshold voltage sensing period may be longer than one horizontal period of the display period.

In one embodiment, as shown in FIG. 3 , the driving circuit 220 may include third to thirteenth transistors T3 to T13 and first and second capacitors C1 and C2. The third transistor T3 may include a first terminal receiving the first clock signal CLK1, a second terminal connected to the second node N2, and a gate terminal connected to the first node N1. The fourth transistor T4 may include a first terminal connected to the on-level voltage VGH, a second terminal connected to the first node N1, and a gate terminal receiving a scan input signal. Meanwhile, in FIG. 3, the scan input signal is shown as the previous scan signal (SCAN[m−1]), but in the case of the first scan signal output circuit 200(1), the scan input signal is the scan start signal (STV). It may be. Also, when the display on signal DIS_ON is activated, since the scan signal SCAN[m] and the connection signal L[m] have substantially the same waveform, the scan input signal may be the previous connection signal L[m−1]. The fifth transistor T5 may include a first terminal connected to the second node N2, a second terminal connected to the on-level voltage VGH, and a gate terminal receiving the first clock signal CLK1. The sixth transistor T6 may include a first terminal connected to the second node N2, a second terminal connected to the on-level voltage VGH, and a gate terminal connected to the second node N2. The seventh transistor T7 may include a first terminal connected to the first node N1, a second terminal connected to the first terminal of the eighth transistor T8, and a gate terminal receiving the second clock signal CLK2. The eighth transistor T8 may include a first terminal connected to the second terminal of the seventh transistor T7, a second terminal connected to the connection signal output node LN, and a gate terminal connected to the second node N2. The ninth transistor T9 may include a first terminal connected to the first node N1, a second terminal connected to the connection signal output node LN, and a gate terminal receiving the connection signal L[m+2] thereafter. Meanwhile, in FIG. 3, the subsequent connection signal L [m + 2] is shown as a connection signal output from the m + 2th scan signal output circuit 200 (m + 2), but depending on the embodiment, the subsequent connection signal (L [m + 2]) may be a connection signal output from another scan signal output circuit. The first capacitor C1 may include a first terminal connected to the first node N1 and a second terminal connected to the connection signal output node LN. The tenth transistor T10 may include a first terminal receiving the second clock signal CLK2, a second terminal connected to the connection signal output node LN, and a gate terminal connected to the first node N1. The eleventh transistor T11 may include a first terminal connected to the connection signal output node LN, a second terminal connected to the auxiliary off-level voltage VGL1 having a lower voltage level than the off-level voltage VGL, and a gate terminal connected to the second node N2. At this time, since the second transistor T2 is implemented as a relatively large transistor as a buffer transistor, the auxiliary off-level voltage VGL1 is provided to compensate for the fact that the second transistor T2 is not sufficiently discharged when the scan-off signal is output as the scan signal SCAN[m]. The second capacitor C2 may include a first terminal connected to the second node N2 and a second terminal connected to the auxiliary off-level voltage VGL1. The twelfth transistor T12 may include a first terminal connected to the first node N1, a second terminal connected to the first driving node Q1N, and a gate terminal receiving the display on signal DIS_ON. The thirteenth transistor T13 may include a first terminal connected to the second node N2, a second terminal connected to the second driving node Q2N, and a gate terminal receiving the display on signal DIS_ON.

In one embodiment, as shown in FIG. 3 , the sampling-buffer circuit 240 may include a first transistor T1, a second transistor T2, fourteenth to seventeenth transistors T14, ..., T17, and a third capacitor C3. The fourteenth transistor T14 may include a first terminal receiving the connection signal L[m+2], a second terminal connected to the sampling node SN, and a gate terminal receiving the sensing on signal SEN_ON. The third capacitor C3 may include a first terminal connected to the sampling node SN and a second terminal connected to the auxiliary off-level voltage VGL1. Depending on the embodiment, the second terminal of the third capacitor C3 may be connected to the off-level voltage VGL. The fifteenth transistor T15 may include a first terminal receiving the sensing clock signal S_CLK, a second terminal connected to the first driving node Q1N, and a gate terminal connected to the sampling node SN. The sixteenth transistor T16 may include a first terminal connected to the second driving node Q2N, a second terminal connected to the first terminal of the seventeenth transistor T17, and a gate terminal receiving the sensing clock signal S_CLK. The seventeenth transistor T17 may include a first terminal connected to the second terminal of the sixteenth transistor T16, a second terminal connected to the off-level voltage VGL, and a gate terminal connected to the sampling node SN. The first transistor T1 may include a first terminal receiving the second clock signal CLK2, a second terminal connected to the scan signal output node ON, and a gate terminal connected to the first driving node Q1N. The second transistor T2 may include a first terminal connected to the scan signal output node ON, a second terminal connected to the off-level voltage VGL, and a gate terminal connected to the second driving node Q2N. Depending on the embodiment, the sampling-buffer circuit 240 may further include a fourth capacitor C4 including a first terminal receiving the sensing-on signal SEN_ON and a second terminal connected to the sampling node SN. Depending on the embodiment, the sampling-buffer circuit 240 may further include a fifth capacitor C5 including a first terminal connected to the first driving node Q1N and a second terminal connected to the scan signal output node ON. Depending on the embodiment, the sampling-buffer circuit 240 may further include a sixth capacitor C6 including a first terminal connected to the second driving node Q2N and a second terminal connected to the off-level voltage VGL. When the sampling-buffer circuit 240 further includes a fourth capacitor C4, a fifth capacitor C5, and/or a sixth capacitor C6, each of the first to nth scan signal output circuits 200(1), ..., 200(n) may be more robust to a negative threshold voltage condition. Meanwhile, each of the first to nth scan signal output circuits 200(1), ..., 200(n) may receive the first clock signal CLK1 and the second clock signal CLK2, and output a scan on signal or a scan off signal based thereon. At this time, the rising edge of the second clock signal CLK2 is positioned adjacent to the falling edge of the first clock signal CLK1, the rising edge of the first clock signal CLK1 is positioned adjacent to the falling edge of the second clock signal CLK2, and the activation period of the first clock signal CLK1 and the activation period of the second clock signal CLK2 may not overlap each other. In addition, when the display device is in a power-on state, one frame includes a display period and a porch period. In the display period, the display on signal DIS_ON is activated and the sensing clock signal S_CLK is deactivated. In the inactive period of the display on signal DIS_ON in the porch period, the first clock signal CLK1, the second clock signal CLK2, and the sensing clock signal S_CLK are activated. Furthermore, the sensing on signal SEN_ON may be activated or deactivated in an activation period of the connection signal L[m+2] later in the display period. For example, when the sensing-on signal SEN_ON is activated in the activation period of the subsequent connection signal L[m+2] within the display period, the sampling voltage may be stored in the m-th scan signal output circuit 200(m), and if the sensing-on signal SEN_ON is not activated in the activation period of the subsequent connection signal L[m+2] within the display period, the sampling voltage may not be stored in the m-th scan signal output circuit 200(m). Meanwhile, when the display device is in a power off state, one frame includes a threshold voltage sensing period, and both the display on signal DIS_ON and the sensing clock signal S_CLK may be activated during the threshold voltage sensing period. However, the selective provision of scan signals (SCAN[1], ..., SCAN[n]) to the display panel by the scan driver 100 in a progressive scan method or a random scan method according to the display operation, the mobility sensing operation, and the threshold voltage sensing operation of the display device will be described in detail with reference to FIGS. 5 to 12.

As described above, the scan driver 100 provides scan signals (SCAN[1], ..., SCAN[n]) to the display panel to perform a threshold voltage sensing operation when the display device is in a power-off state, and provides scan signals (SCAN[1], ..., SCAN[n]) to the display panel so that a display operation and a mobility sensing operation are repeatedly performed every frame when the display device is in a power-on state. While sequentially applying (SL(1), ..., SL(n)), by selecting a mobility sensing target scan line on which mobility sensing operation will be performed and applying a scan on signal to the mobility sensing target scan line in the porch section of the corresponding frame, display while selectively providing scan signals (SCAN[1], ..., SCAN[n]) to the display panel in a progressive scan method or a random scan method according to the display operation performed by the display device, the mobility sensing operation, and the threshold voltage sensing operation, display During a thin film transistor process of forming a thin film transistor on a panel, it may have a simple internal structure that can be directly formed on the display panel. Accordingly, the display device including the scan driver 100 can be manufactured with low manufacturing cost and simple manufacturing process.

5 is a timing diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a display operation, and FIG. 6 is a circuit diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a display operation.

Referring to FIGS. 5 and 6 , an example in which the scan signal output circuit 200 generates a scan signal SCAN[m] for a display operation is shown. However, although the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are shown in FIG. 5, the scan signal output circuit 200 will be described on the assumption that the first clock signal CLK1 and the second clock signal CLK2 are received. That is, when the k-th scan signal output circuit 200 receives the first clock signal CLK1 and the second clock signal CLK2, the k+1-th scan signal output circuit 200 receives the third clock signal CLK3 and the fourth clock signal CLK4. Therefore, in the scan signal output circuit 200, the first clock signal CLK1 and the third clock signal CLK3 are signals performing the same role, and the second clock signal CLK2 and the fourth clock signal CLK4 are signals performing the same role. It is determined whether (CLK4) is input.

During the DISPLAY PERIOD of one frame of the display device, the sensing clock signal S_CLK may remain inactive (i.e., logic low level) and the display on signal DIS_ON may remain active (i.e., logic high level). At this time, when the scan input signal (that is, indicated by SCAN[m-1]) is activated and the fourth transistor T4 is turned on, the first node N1 and the first driving node Q1N are charged with the on-level voltage VGH. Accordingly, the signal applied to the first node N1 and the first driving signal Q1 applied to the first driving node Q1N may have the on-level voltage VGH. However, in FIG. 6, the scan input signal is shown as the previous scan signal (SCAN[m−1]), but when the display on signal (DIS_ON) is activated, the scan signal (SCAN[m]) and the connection signal (L[m]) Since they have substantially the same waveform, the scan input signal can be replaced with the previous connection signal (L[m−1]). In addition, in the case of the first scan signal output circuit 200 in the scan driver 100, it is natural that the scan input signal is the scan start signal (STV). On the other hand, when the scan input signal is activated and the fourth transistor T4 is turned on, the second node N2 and the second drive node Q2N are discharged to the inactive voltage of the first clock signal CLK1 by the first clock signal CLK1 disabled, and accordingly, the signal and the second driving node applied to the second node N2 and the second driving node and the second driving node. The second drive signal Q2 applied to (Q2N) may have an inactive voltage of the first clock signal CLK1. As a result, the first transistor T1 and the tenth transistor T10 may be turned on, and the second transistor T2 and the eleventh transistor T11 may be turned off. Accordingly, as the second clock signal CLK2 is activated, the scan signal SCAN[m] having the activation voltage of the second clock signal CLK2, that is, the scan on signal, may be output through the scan signal output node ON, and the connection signal L[m] having the activation voltage of the second clock signal CLK2 may be output through the connection node LN. Thereafter, as the second clock signal CLK2 is deactivated again, the scan signal SCAN[m] having the inactivation voltage of the second clock signal CLK2, that is, the scan off signal, may be output through the scan signal output node ON, and the connection signal L[m] having the inactivation voltage of the second clock signal CLK2 may be output through the connection node LN. That is, since the display on signal DIS_ON remains active, the scan signal SCAN[m] and the connection signal L[m] may have substantially the same waveform. In this way, the scan signal output circuits 200 sequentially connected to each other within the scan driver 100 can sequentially output the scan signal SCAN[m] having the activation voltage of the second clock signal CLK2, that is, the scan on signal, in the DISPLAY PERIOD of one frame of the display device. Meanwhile, for convenience of explanation, in FIG. 6 , transistors that are turned off when generating a scan signal for a display operation in a display period (DISPLAY PERIOD) of one frame of the display device are indicated by dotted lines.

7 is a timing diagram for explaining that the scan signal output circuit of FIG. 2 selects a scan line to be subjected to mobility sensing, which is an object of a mobility sensing operation, and FIG. 8 is a circuit diagram for explaining that the scan signal output circuit of FIG.

Referring to FIGS. 7 and 8 , an example in which the scan signal output circuit 200 selects a mobility sensing target scan line, which is a target of a mobility sensing operation, in a display period (DISPLAY PERIOD) of one frame of the display device is illustrated. As described above, in the display period (DISPLAY PERIOD) of one frame of the display device, the sensing clock signal S_CLK may remain inactive and the display on signal DIS_ON may remain active. At this time, when the connection signal L[n+2] is subsequently activated, the auxiliary off-level voltage VGL1 passes through the 11th transistor T11 and the ninth transistor T9 to reset the first node N1 and the first driving node Q1N. At this time, as the sensing on signal SEN_ON is activated while the connection signal L[n+2] is activated, the fourteenth transistor T14 is turned on, and accordingly, the sampling node SN can be charged with the activation voltage of the connection signal L[n+2]. As a result, the sampling node SN may store and maintain the sampling voltage using the third capacitor C3. As described above, since the display device senses the mobilities of driving transistors inside the pixel circuits connected to one scan line in the porch period (PORCH PERIOD) of one frame, one scan line to be subjected to mobility sensing is selected in one frame, and accordingly, the sensing on signal SEN_ON can be activated for only one scan signal output circuit 200 among the scan signal output circuits 200 in the scan driver 100. However, in FIG. 8, the subsequent connection signal L [m + 2] is shown as a connection signal output from the m + 2nd scan signal output circuit 200, but depending on the embodiment, the subsequent connection signal (L [m + 2]) may be a connection signal output from another scan signal output circuit. Meanwhile, for convenience of explanation, in FIG. 8 , transistors that are turned off when selecting a mobility sensing target scan line, which is a target of a mobility sensing operation, are indicated by dotted lines in a display period (DISPLAY PERIOD) of one frame of the display device.

9 is a timing diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a mobility sensing operation, and FIG. 10 is a circuit diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a mobility sensing operation.

Referring to FIGS. 9 and 10 , an example in which the scan signal output circuit 200 generates a scan signal SCAN[m] for a mobility sensing operation is illustrated. As described above, in the porch period PORCH PERIOD of one frame of the display device, the display on signal DIS_ON is deactivated and then activated, and the first clock signal CLK1, second clock signal CLK2, third clock signal CLK3, fourth clock signal CLK4, and sensing clock signal S_CLK can be activated in the inactive period of the display on signal DIS_ON in the porch period PORCH PERIOD of one frame. there is Specifically, in the porch period PORCH PERIOD of one frame of the display device, the 15th transistor T15 in the scan signal output circuit 200 in which the sampling node SN maintains the sampling voltage using the third capacitor C3 is turned on by the sampling voltage, and as the sensing clock signal S_CLK is activated, the first driving node Q1N can be charged with the activation voltage of the sensing clock signal S_CLK. Accordingly, the first driving signal Q1 applied to the first driving node Q1N may have an activation voltage of the sensing clock signal S_CLK. As a result, the first transistor T1 is turned on, and accordingly, a scan signal SCAN[m] having an activation voltage of the second clock signal CLK2, that is, a scan on signal, may be output through the scan signal output node ON. On the other hand, in the porch period PORCH PERIOD of one frame of the display device, since the fifteenth transistor T15 in the scan signal output circuit 200 that does not store the sampling voltage is not turned on, the scan signal output circuit 200 that does not store the sampling voltage cannot output the scan signal SCAN[m] having the activation voltage of the second clock signal CLK2, that is, the scan on signal. Then, in the porch period PORCH PERIOD of one frame of the display device, all scan signal output circuits 200 in the scan driver 100 may be reset as the sensing on signal SEN_ON is activated. In this way, only one scan signal output circuit 200 in the scan driver 100 can output a scan signal SCAN[m] having an activation voltage of the second clock signal CLK2, that is, a scan on signal, in the porch period PORCH PERIOD of one frame of the display device. Meanwhile, for convenience of explanation, in FIG. 10 , transistors that are turned off in generating the scan signal SCAN[m] for the mobility sensing operation in the porch period PORCH PERIOD of one frame of the display device are indicated by dotted lines.

11 is a timing diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a threshold voltage sensing operation, and FIG. 12 is a circuit diagram for explaining that the scan signal output circuit of FIG. 2 generates a scan signal for a threshold voltage sensing operation.

Referring to FIGS. 11 and 12 , an example in which the scan signal output circuit 200 generates a scan signal SCAN[m] for a threshold voltage sensing operation is illustrated. As described above, when the display device is in a power-off state, one frame includes a threshold voltage sensing period (VTH SENSING PERIOD), and the display device performs a threshold voltage sensing operation in the threshold voltage sensing period (VTH SENSING PERIOD). The frame may be performed a predetermined number of times (e.g., once). In the threshold voltage sensing period (VTH SENSING PERIOD) of one frame, the first to nth scan signal output circuits may sequentially apply the scan on signal to the first to nth scan lines in the same manner as the display period (DISPLAY PERIOD) of one frame. At this time, one horizontal period of the threshold voltage sensing period (VTH SENSING PERIOD) of one frame is longer than one horizontal period of the display period of one frame. This can be achieved by adjusting the widths of the first to fourth clock signals (CLK1, ..., CLK4). Similarly, although the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 are shown in FIG. 11, the scan signal output circuit 200 will be described on the assumption that the first clock signal CLK1 and the second clock signal CLK2 are received. That is, when the k-th scan signal output circuit 200 receives the first clock signal CLK1 and the second clock signal CLK2, the k+1-th scan signal output circuit 200 receives the third clock signal CLK3 and the fourth clock signal CLK4. Therefore, in the scan signal output circuit 200, the first clock signal CLK1 and the third clock signal CLK3 are signals performing the same role, and the second clock signal CLK2 and the fourth clock signal CLK4 are signals performing the same role. It is determined whether or not to enter

In the threshold voltage sensing period VTH SENSING PERIOD of one frame of the display device, the sensing clock signal S_CLK may remain active and the display on signal DIS_ON may also remain active. At this time, when the scan input signal (that is, indicated by SCAN[m-1]) is activated and the fourth transistor T4 is turned on, the first node N1 and the first driving node Q1N are charged with the on-level voltage VGH. Accordingly, the signal applied to the first node N1 and the first driving signal Q1 applied to the first driving node Q1N may have the on-level voltage VGH. However, in FIG. 12, the scan input signal is shown as the previous scan signal (SCAN[m-1]), but when the display on signal (DIS_ON) is activated, the scan signal (SCAN[m]) and the connection signal (L[m]) Since they have substantially the same waveform, the scan input signal can be replaced with the previous connection signal (L[m-1]). In addition, in the case of the first scan signal output circuit 200 in the scan driver 100, it is natural that the scan input signal is the scan start signal (STV). On the other hand, when the scan input signal is activated and the fourth transistor T4 is turned on, the second node N2 and the second drive node Q2N are discharged to the inactive voltage of the first clock signal CLK1 by the disabled first clock signal CLK1, and accordingly, the signal and the second driving node applied to the second node N2 and the second driving node. The second drive signal Q2 applied to (Q2N) may have an inactive voltage of the first clock signal CLK1. As a result, the first transistor T1 and the tenth transistor T10 may be turned on, and the second transistor T2 and the eleventh transistor T11 may be turned off. Accordingly, as the second clock signal CLK2 is activated, the scan signal SCAN[m] having the activation voltage of the second clock signal CLK2, that is, the scan on signal, may be output through the scan signal output node ON, and the connection signal L[m] having the activation voltage of the second clock signal CLK2 may be output through the connection node LN. Thereafter, as the second clock signal CLK2 is deactivated again, the scan signal SCAN[m] having the inactivation voltage of the second clock signal CLK2, that is, the scan off signal, may be output through the scan signal output node ON, and the connection signal L[m] having the inactivation voltage of the second clock signal CLK2 may be output through the connection node LN. That is, since the display on signal DIS_ON remains active, the scan signal SCAN[m] and the connection signal L[m] may have substantially the same waveform. In this way, the scan signal output circuits 200 sequentially connected to each other within the scan driver 100 can sequentially output the scan signal SCAN[m] having the activation voltage of the second clock signal CLK2, that is, the scan on signal, in the threshold voltage sensing period VTH SENSING PERIOD of one frame of the display device. Meanwhile, for convenience of description, in FIG. 12 , transistors that are turned off when generating a scan signal for a threshold voltage sensing operation in the threshold voltage sensing period (VTH SENSING PERIOD) of one frame of the display device are indicated by dotted lines.

13 is a block diagram illustrating a display device according to example embodiments.

Referring to FIG. 13 , the display device 500 may include a display panel 510 , a scan driver 520 , a data driver 530 and a timing controller 540 . Meanwhile, the display device 500 may be an organic light emitting display device or a liquid crystal display device, but the display device 500 is not limited thereto.

The display panel 510 may include a plurality of pixel circuits. The display panel 510 may be connected to the scan driver 520 through first to nth scan lines, and may be connected to the data driver 530 through first to kth data lines (where k is an integer greater than or equal to 2). The scan driver 520 may provide scan signals GS to the display panel 510 through the first to nth scan lines. The data driver 530 may provide the data signal DS to the display panel 510 through the first through kth data lines. The timing controller 540 may control the scan driver 520 and the data driver 530 by generating control signals CTL1 and CTL2 . Depending on the embodiment, the timing controller 540 may receive image data, perform predetermined data processing (eg, degradation compensation, image processing, etc.) and transmit the image data to the data driver 530 . Meanwhile, the scan driver 520 may have a simple internal structure that can be directly formed on the display panel 510 during a thin film transistor process for forming thin film transistors on the display panel 510, while the display device 500 selectively provides scan signals GS to the display panel 510 in a progressive scan method or a random scan method according to the display operation, the mobility sensing operation, and the threshold voltage sensing operation. That is, the scan driver 520 may not be an external scan driver bonded or externally mounted on the display panel 510 in the form of an integrated circuit, but may be a built-in scan driver directly formed on the display panel 510 during a thin film transistor process for forming thin film transistors on the display panel 510. To this end, the scan driver 520 may include first to n-th scan signal output circuits respectively connected to the first to n-th scan lines, and each of the first to n-th scan signal output circuits may include a driving circuit and a sampling-buffer circuit composed of oxide thin film transistors and operating.

Specifically, the driving circuit included in each of the first to nth scan signal output circuits may apply a first driving signal to a first driving node and a second driving signal to a second driving node based on a scan input signal corresponding to a scan start signal or a previous scan signal, a first clock signal, a display on signal, and an on level voltage. The sampling-buffer circuit included in each of the first to n-th scan signal output circuits may output a scan on signal or a scan off signal through a scan signal output node based on the second clock signal, off level voltage, first driving signal, and second driving signal, and may store a sampling voltage for providing a scan on signal to a scan line to be sensed for mobility based on the sensing on signal. When the display device 500 is in a power-on state, one frame includes a display period and a porch period, and the frame may be repeatedly performed. The display device 500 performs a display operation in a display period. For the display operation, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines. In addition, the display device 500 performs a mobility sensing operation in a porch section. For the mobility sensing operation, one of the first to nth scan signal output circuits may apply a scan on signal to a scan line subject to mobility sensing. In this case, the mobility sensing target scan line may be selected while the first to n th scan signal output circuits sequentially apply the scan on signal to the first to n th scan lines in the display period. That is, the mth scan signal output circuit connected to the scan line to be sensed for mobility may store the sampling voltage based on the sensing on signal. Meanwhile, when the display device 500 is in a power-off state, one frame includes a threshold voltage sensing period, and the frame may be performed a preset number of times (eg, once). The display device 500 performs a threshold voltage sensing operation in a threshold voltage sensing period. For the threshold voltage sensing operation, the first to n th scan signal output circuits may sequentially apply scan-on signals to the first to n th scan lines. In this case, one horizontal period of the threshold voltage sensing period may be longer than one horizontal period of the display period.

The driving circuit included in each of the first to n th scan signal output circuits may include third to thirteenth transistors and first and second capacitors to apply a first driving signal to the first driving node and a second driving signal to the second driving node based on a scan input signal corresponding to a scan initiation signal or a previous scan signal, a first clock signal, a display on signal, and an on level voltage, and the sampling-buffer circuit included in each of the first to n th scan signal output circuits may include a second clock signal and an off level voltage. First and second transistors, fourteenth to seventeenth transistors, and a third capacitor may be included to store a sampling voltage for outputting a scan on signal or a scan off signal through a scan signal output node based on the voltage, the first driving signal, and the second driving signal, and providing a scan on signal to a scan line to be sensed based on the sensing on signal. That is, each of the first to nth scan signal output circuits may have a 17T-3C structure. However, according to embodiments, each of the first to n th scan signal output circuits may further include additional capacitors in the sampling-buffer circuit in order to be more robust to a negative threshold voltage condition. However, since this has been described above, overlapping description thereof will be omitted. As described above, the display device 500 selectively provides the scan signal GS to the display panel in a progressive scan method or a random scan method according to the display operation, the mobility sensing operation, and the threshold voltage sensing operation performed by the display device 500, and includes the scan driver 520 having a simple internal structure that can be directly formed on the display panel 510 during a thin film transistor process of forming the thin film transistors in the display panel 510, so that it can be manufactured with low manufacturing cost and a simple manufacturing process. Meanwhile, in FIG. 13 , the display device 500 is illustrated as including a display panel 510, a scan driver 520, a data driver 530, and a timing controller 540, but according to embodiments, other components (e.g., a light emitting driver, etc.) may be further included in addition to the above components.

14 is a block diagram illustrating an electronic device according to embodiments of the present invention, and FIG. 15 is a diagram illustrating an example in which the electronic device of FIG. 14 is implemented as a smart phone.

14 and 15 , an electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input/output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may correspond to the display device 500 of FIG. 13 . In addition, the electronic device 1000 may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or with other systems. In one embodiment, as shown in FIG. 15 , the electronic device 1000 may be implemented as a smart phone. However, this is an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation device, a computer monitor, a laptop computer, a head mounted display (HMD), and the like.

Processor 1010 may perform certain calculations or tasks. According to embodiments, the processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), or the like. The processor 1010 may be connected to other components through an address bus, a control bus, and a data bus. According to embodiments, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. The memory device 1020 may store data necessary for the operation of the electronic device 1000 . For example, the memory device 1020 may include an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, It may include a non-volatile memory device such as a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and/or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device. The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, and the like. The input/output device 1040 may include an input means such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and an output means such as a speaker and a printer. The power supply 1050 may supply power necessary for the operation of the electronic device 1000 .

The display device 1060 may be connected to other components through the buses or other communication links. Depending on embodiments, the display device 1060 may be included in the input/output device 1040 . As described above, the display device 1060 may include a scan driver having a simple internal structure that can be directly formed on the display panel during a thin film transistor process for forming thin film transistors in the display panel while selectively providing scan signals to the display panel in a progressive scan method or a random scan method according to the display operation, the mobility sensing operation, and the threshold voltage sensing operation performed by the display device 1060. Accordingly, the display device 1060 may be manufactured with low manufacturing cost and a simple manufacturing process. To this end, the display device 1060 may include a display panel including pixel circuits, a data driver providing a data signal to the display panel, a scan driver providing a scan signal to the display panel, and a timing controller controlling the data driver and the scan driver. At this time, the scan driver includes first to n-th scan signal output circuits connected to the first to n-th scan lines, respectively, and each of the first to n-th scan signal output circuits includes a scan input signal corresponding to a scan start signal or a previous scan signal, a first clock signal, a display on signal, and a drive circuit that applies a first drive signal to a first drive node and a second drive signal to a second drive node based on a display on signal and an on-level voltage, and a second clock signal, an off-level voltage, a first drive signal, and a second drive signal A sampling-buffer circuit may be configured to output a scan on signal or a scan off signal through a scan signal output node and store a sampling voltage for providing a scan on signal to a scan line to be sensed based on the sensing on signal. When the display device 1060 is in a power-on state, one frame includes a display period and a porch period, the first to n th scan signal output circuits in the display period sequentially apply scan on signals to the first to n th scan lines, the m th scan signal output circuit among the first to n th scan signal output circuits stores the sampling voltage, and the m th scan signal output circuit in the porch period may apply the scan on signal to the m th scan line. When the display device 1060 is in a power off state, one frame includes a threshold voltage sensing period, and in the threshold voltage sensing period, the first to n th scan signal output circuits may sequentially apply the scan on signal to the first to n th scan lines. However, since this has been described above, overlapping description thereof will be omitted.

The present invention can be applied to a display device and an electronic device including the display device. For example, the present invention can be applied to mobile phones, smart phones, video phones, smart pads, smart watches, tablet PCs, vehicle navigation systems, televisions, computer monitors, notebooks, head mounted displays, MP3 players, and the like.

Although the above has been described with reference to exemplary embodiments of the present invention, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the present invention described in the claims below.

100: scan driver 200: scan signal output circuit
220 driving circuit 240 sampling-buffer circuit
500: display device 510: display panel
520: data driver 530: scan driver
540: timing controller 1000: electronic device
1010: processor 1020: memory device
1030: storage device 1040: input/output device
1050: power supply 1060: display device

Claims (20)

A scan driver including first to nth scan signal output circuits connected to first to nth scan lines (where n is an integer of 2 or greater), respectively;
Each of the first to nth scan signal output circuits
A driving circuit for applying a first driving signal to a first driving node and a second driving signal to a second driving node based on a scan start signal or a scan input signal corresponding to a previous scan signal, a first clock signal, a display on signal, and an on level voltage; and
A sampling-buffer circuit for outputting a scan on signal or a scan off signal through a scan signal output node based on a second clock signal, an off level voltage, the first driving signal, and the second driving signal, and storing a sampling voltage for providing the scan on signal to a scan line to be sensed based on the sensing on signal;
When the display device is in a power-on state, one frame includes a display period and a porch period, in the display period, the display device performs a display operation, and in the porch period, the display device performs a mobility sensing operation, and in the power-on state, the display device repeatedly performs the frame,
When the display device is in a power-off state, the frame includes a threshold voltage sensing period, the display device performs a threshold voltage sensing operation in the threshold voltage sensing period, and in the power-off state, the display device performs the frame a predetermined number of times. delete 2. The scan driver of claim 1 , wherein the first to n th scan signal output circuits sequentially apply the scan on signal to the first to n th scan lines in the display period, an m th scan signal output circuit among the first to n th scan signal output circuits stores the sampling voltage, and in the porch period, the m th scan signal output circuit applies the scan on signal to the m th scan line. delete The scan driver of claim 1 , wherein the first to n th scan signal output circuits sequentially apply the scan on signal to the first to n th scan lines in the threshold voltage sensing period. The scan driver of claim 5 , wherein one horizontal period of the threshold voltage sensing period is longer than one horizontal period of the display period. The method of claim 1, wherein the driving circuit
a third transistor including a first terminal receiving the first clock signal, a second terminal connected to a second node, and a gate terminal connected to the first node;
a fourth transistor including a first terminal connected to the on-level voltage, a second terminal connected to the first node, and a gate terminal receiving the scan input signal;
a fifth transistor including a first terminal connected to the second node, a second terminal connected to the on-level voltage, and a gate terminal receiving the first clock signal;
a sixth transistor including a first terminal connected to the second node, a second terminal connected to the on-level voltage, and a gate terminal connected to the second node;
a seventh transistor including a first terminal connected to the first node, a second terminal, and a gate terminal receiving the second clock signal;
an eighth transistor including a first terminal connected to the second terminal of the seventh transistor, a second terminal connected to a connection signal output node, and a gate terminal connected to the second node;
a ninth transistor including a first terminal connected to the first node, a second terminal connected to the connection signal output node, and a gate terminal receiving a subsequent connection signal;
a first capacitor including a first terminal connected to the first node and a second terminal connected to the connection signal output node;
a tenth transistor including a first terminal receiving the second clock signal, a second terminal connected to the connection signal output node, and a gate terminal connected to the first node;
an eleventh transistor including a first terminal connected to the connection signal output node, a second terminal connected to an auxiliary off-level voltage having a voltage level lower than the off-level voltage, and a gate terminal connected to the second node;
a second capacitor having a first terminal connected to the second node and a second terminal connected to the auxiliary off-level voltage;
a twelfth transistor including a first terminal connected to the first node, a second terminal connected to the first driving node, and a gate terminal receiving the display on signal; and
and a thirteenth transistor including a first terminal connected to the second node, a second terminal connected to the second driving node, and a gate terminal receiving the display-on signal. 8. The method of claim 7, wherein the sampling-buffer circuit
a fourteenth transistor including a first terminal receiving the subsequent connection signal, a second terminal connected to a sampling node, and a gate terminal receiving the sensing-on signal;
a third capacitor having a first terminal connected to the sampling node and a second terminal connected to the auxiliary off-level voltage;
a fifteenth transistor including a first terminal receiving a sensing clock signal, a second terminal connected to the first driving node, and a gate terminal connected to the sampling node;
a sixteenth transistor including a first terminal connected to the second driving node, a second terminal, and a gate terminal receiving the sensing clock signal;
a seventeenth transistor including a first terminal connected to the second terminal of the sixteenth transistor, a second terminal connected to the off-level voltage, and a gate terminal connected to the sampling node;
a first transistor including a first terminal receiving the second clock signal, a second terminal connected to the scan signal output node, and a gate terminal connected to the first driving node; and
and a second transistor including a first terminal connected to the scan signal output node, a second terminal connected to the off-level voltage, and a gate terminal connected to the second driving node. 9. The method of claim 8, wherein the sampling-buffer circuit
The scan driver of claim 1, further comprising a fourth capacitor including a first terminal receiving the sensing-on signal and a second terminal connected to the sampling node. 9. The method of claim 8, wherein the sampling-buffer circuit
The scan driver of claim 1, further comprising a fifth capacitor including a first terminal connected to the first driving node and a second terminal connected to the scan signal output node. 9. The method of claim 8, wherein the sampling-buffer circuit
The scan driver of claim 1, further comprising a sixth capacitor including a first terminal connected to the second driving node and a second terminal connected to the off-level voltage. 9. The scan driver of claim 8 , wherein a rising edge of the second clock signal is positioned adjacent to a falling edge of the first clock signal, a rising edge of the first clock signal is positioned adjacent to a falling edge of the second clock signal, and an active period of the first clock signal and an active period of the second clock signal do not overlap each other. 13. The scan driver of claim 12 , wherein when the display device is in a power-on state, one frame includes a display period and a porch period, wherein the display-on signal is activated and the sensing clock signal is deactivated in the display period, and the first clock signal, the second clock signal, and the sensing clock signal are activated during a deactivated period of the display-on signal in the porch period. 13. The scan driver of claim 12, wherein the sensing on signal is activated or deactivated in an activation period of the subsequent connection signal within the display period. 13. The scan driver of claim 12, wherein one frame includes a threshold voltage sensing period when the display device is in a power off state, and both the display on signal and the sensing clock signal are activated during the threshold voltage sensing period. a display panel including a plurality of pixel circuits;
a data driver providing data signals to the display panel;
a scan driver providing a scan signal to the display panel; and
A timing controller controlling the data driver and the scan driver;
The scan driver includes first to nth scan signal output circuits connected to first to nth scan lines, respectively;
Each of the first to nth scan signal output circuits
A driving circuit for applying a first driving signal to a first driving node and a second driving signal to a second driving node based on a scan start signal or a scan input signal corresponding to a previous scan signal, a first clock signal, a display on signal, and an on level voltage; and
A sampling-buffer circuit for outputting a scan on signal or a scan off signal through a scan signal output node based on a second clock signal, an off level voltage, the first driving signal, and the second driving signal, and storing a sampling voltage for providing the scan on signal to a scan line to be sensed based on the sensing on signal;
In the power-on state, one frame includes a display section and a porch section, performs a display operation in the display section, performs a mobility sensing operation in the porch section, and repeatedly performs the frame in the power-on state,
In a power off state, the frame includes a threshold voltage sensing section, a threshold voltage sensing operation is performed in the threshold voltage sensing section, and the frame is performed a predetermined number of times in the power off state. delete 17. The display device of claim 16 , wherein the first to n th scan signal output circuits sequentially apply the scan on signal to the first to n th scan lines in the display period, an m th (where m is an integer greater than or equal to 1 and less than or equal to n) scan signal output circuit stores the sampling voltage, and in the porch period, the m th scan signal output circuit applies the scan on signal to the m th scan line. delete 17. The display device of claim 16, wherein the first to nth scan signal output circuits sequentially apply the scan on signal to the first to nth scan lines in the threshold voltage sensing period.

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