KR102610247B1 - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

A semiconductor package of the present disclosure includes a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first side of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second side of the semiconductor chip; a conductive post disposed outside the semiconductor chip; A first redistribution structure on the first side of the semiconductor chip, comprising: a first redistribution insulating layer supporting the conductive studs and the conductive posts; a first redistribution line pattern extending in a horizontal direction within the first redistribution insulating layer; and a first redistribution via pattern extending in a vertical direction within the first redistribution insulating layer; A second redistribution structure on the second side of the semiconductor chip, comprising: a second redistribution insulating layer disposed on the adhesive layer; and a second redistribution line pattern extending in the horizontal direction within the second redistribution insulating layer. and a second redistribution via pattern extending vertically inside the second redistribution insulating layer; and a first molding layer disposed between the first redistribution structure and the second redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.

Description

Semiconductor package and manufacturing method thereof {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

The technical idea of the present disclosure relates to a semiconductor package and a manufacturing method thereof.

As the storage capacity of semiconductor chips increases, semiconductor packages containing semiconductor chips are required to become thinner and lighter. In addition, research is being conducted to include semiconductor chips with various functions in a semiconductor package and to drive the semiconductor chips quickly. In response to this trend, research is being conducted on a package-on-package (PoP) type semiconductor package in which an upper semiconductor package is stacked on a lower semiconductor package.

One of the problems that the technical idea of the present disclosure seeks to solve is to provide a thin and light semiconductor package.

Additionally, one of the problems to be solved by the technical idea of the present disclosure is to provide a semiconductor package having a redistribution line pattern formed in a fine size.

Additionally, one of the problems that the technical idea of the present disclosure seeks to solve is to provide a semiconductor package with improved structural reliability by reducing warpage.

Additionally, one of the problems that the technical idea of the present disclosure seeks to solve is to provide a semiconductor package with improved heat dissipation performance.

In order to achieve the above object, an exemplary embodiment of the present disclosure includes a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first side of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second side of the semiconductor chip; a conductive post disposed outside the semiconductor chip; A first redistribution structure on the first side of the semiconductor chip, comprising: a first redistribution insulating layer supporting the conductive studs and the conductive posts; a first redistribution line pattern extending in a horizontal direction within the first redistribution insulating layer; and a first redistribution via pattern extending in a vertical direction within the first redistribution insulating layer; A second redistribution structure on the second side of the semiconductor chip, comprising: a second redistribution insulating layer disposed on the adhesive layer; and a second redistribution line pattern extending in the horizontal direction within the second redistribution insulating layer. and a second redistribution via pattern extending vertically inside the second redistribution insulating layer; A first molding layer is disposed on the first redistribution structure and surrounds the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.

In an exemplary embodiment, the conductive post passes vertically through the first molding layer, and the second redistribution insulating layer of the second redistribution structure surrounds at least a portion of the conductive post. It is characterized by

In an exemplary embodiment, the number of layers formed by the first redistribution line pattern of the first redistribution structure in the horizontal direction may be determined by the number of layers formed by the second redistribution line pattern of the second redistribution structure in the horizontal direction. It is characterized by more than the number of layers.

In an exemplary embodiment, one side of the conductive post is in contact with the first redistribution via pattern of the first redistribution structure, and the other side of the conductive post opposite to the one side is in contact with the second redistribution via pattern. It is characterized in that it contacts the second redistribution line pattern of the line structure.

In an exemplary embodiment, the semiconductor package includes: a conductive pillar disposed on the second redistribution structure and connected to the second redistribution line pattern and the second redistribution via pattern of the second redistribution structure; and a second molding layer disposed on the second redistribution structure and surrounding a side of the conductive pillar.

In an exemplary embodiment, one side of the second molding layer and one side of the conductive pillar are on the same plane.

In an exemplary embodiment, the semiconductor package further includes a package connection pad disposed on the conductive pillar, the second molding layer surrounding a side of the package connection pad, and one of the second molding layers. The surface is characterized in that it is on the same plane as one surface of the package connection pad.

In an exemplary embodiment, the first vertex formed by meeting the top and side surfaces of the first redistribution structure is disposed inside the second vertex formed by meeting the top and side surfaces of the first redistribution structure.

In an exemplary embodiment, the sidewall of the second redistribution structure is wrapped by the first molding layer.

In an exemplary embodiment, the vertical length of the first molding portion of the molding layer disposed between the upper surface of the first redistribution structure and the lower surface of the second redistribution structure is the upper surface of the first redistribution structure. It is characterized in that it is smaller than the vertical length of the second molding portion disposed on the top and surrounding the side of the second redistribution structure.

In an exemplary embodiment, the display device may further include a passive element disposed on the first redistribution structure.

In an exemplary embodiment, the second redistribution structure is a printed circuit board (PCB).

In an exemplary embodiment of the present disclosure, the steps include: forming a first redistribution structure; forming a conductive post on the first redistribution structure; Mounting a semiconductor structure in which an adhesive layer, a semiconductor chip, and a conductive stud are sequentially stacked on the first redistribution structure; forming a first molding layer to surround the semiconductor structure; At least one of a portion of the first molding layer, a portion of the conductive post, and a portion of the conductive stud is exposed such that one side of the conductive post and one side of the conductive stud are exposed from the first molding layer. steps being removed; and forming a second redistribution structure connected to the conductive post and the conductive stud on the first molding layer.

In an exemplary embodiment, the method of manufacturing a semiconductor package includes forming a conductive pillar on a carrier substrate; forming a second molding layer on the carrier substrate; and removing at least one of a portion of the second molding layer and a portion of the conductive pillar so that one surface of the conductive pillar is exposed from the second molding layer. The forming of the structure may include forming the first redistribution structure to be connected to the conductive pillar on the second molding layer.

In an exemplary embodiment, the step of forming a package connection pad on the carrier substrate may further include forming the conductive pillar on the carrier substrate, wherein the conductive pillar is formed on one surface of the package connection pad. It is characterized in that it includes a forming step.

In an exemplary embodiment, the method of manufacturing a semiconductor package includes, after mounting the semiconductor structure on the first redistribution structure, a first redistribution structure comprising the first redistribution structure, the conductive post, and the semiconductor structure. individualizing the structure; and disposing the first structure on a carrier substrate, wherein forming a first molding layer to surround the semiconductor structure includes forming a first molding layer to surround the first structure on the carrier substrate. and forming a semiconductor package, wherein the semiconductor package manufacturing method further includes removing the carrier substrate after forming the first molding layer.

One side of the adhesive layer and one side of the conductive post of the semiconductor package according to the technical idea of the present disclosure may be on the same plane as one side of the molding layer, so that the semiconductor package can be thin and light.

Additionally, a semiconductor package according to an exemplary embodiment of the present disclosure may include a conductive stud and a conductive post connected to a redistribution line pattern, so that the redistribution line pattern may be formed in a fine size.

In addition, a semiconductor package according to an exemplary embodiment of the present disclosure may include a conductive pillar mounted on a redistribution structure and a molding layer surrounding the conductive pillar, so that warping of the semiconductor package is reduced and the semiconductor package is Structural reliability can be improved.

Additionally, the semiconductor package according to an exemplary embodiment of the present disclosure may include the conductive pillar, so heat dissipation performance of the semiconductor package may be improved.

1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
Figure 2 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
3 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
4 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
5 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
6A to 6K are diagrams showing each step of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
9A to 9I are diagrams showing each step of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
10A and 10B are diagrams showing some steps of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
11 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.
12A to 12D are diagrams showing each step of a method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.
13 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present disclosure.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the embodiments of the present disclosure may be modified in various other forms, and the scope of the concept of the present disclosure should not be construed as being limited to the embodiments described in detail below. The embodiments of the present disclosure are preferably interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. Identical symbols refer to identical elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative sizes or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and conversely, a second component may be named a first component without departing from the scope of the concept of the present disclosure.

The terminology used in this application is only used to describe specific embodiments and is not intended to limit the concept of the present disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, expressions such as “comprises” or “has” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features or It should be understood that this does not preclude the presence or addition of numbers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those skilled in the art in the technical field to which the concept of the present disclosure pertains. Additionally, commonly used terms, as defined in dictionaries, should be interpreted to have meanings consistent with what they mean in the context of the relevant technology, and should not be used in an overly formal sense unless explicitly defined herein. It will be understood that this is not to be interpreted.

Embodiments of the present disclosure will be described in detail with reference to the attached drawings.

1 is a cross-sectional view of a semiconductor package 10 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1 , the semiconductor package 10 according to an exemplary embodiment of the present disclosure may function as a lower semiconductor package in a package-on-package (PoP) type semiconductor package.

Additionally, the semiconductor package 10 may be a wafer level package (WLP). In an example embodiment, semiconductor package 10 may be a fan-out wafer level package. For example, at least one of the plurality of external connection terminals 250a included in the semiconductor package 10 may be disposed outside the semiconductor chip 100. However, the semiconductor package 10 is not limited to a wafer level package and may be a panel level package.

The semiconductor package 10 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 100, a first redistribution structure 110, a conductive post 120, a conductive stud 130, a molding layer 140, and an adhesive layer. It may include 150, a second redistribution structure 210, and an external connection terminal 250a.

In an exemplary embodiment, the semiconductor chip 100 may have a first side 100a and a second side 100b. For example, the first side 100a of the semiconductor chip 100 may be one side of the semiconductor chip 100 that contacts the conductive stud 130, and the second side 100b may be opposite to the first side 100a. It may be one side of the semiconductor chip 100 that is in contact with the adhesive layer 150.

Hereinafter, the horizontal direction will be defined as a direction parallel to the direction in which the first surface 100a and the second surface 100b of the semiconductor chip 100 extend (for example, the width direction of the semiconductor chip 100). The vertical direction may be defined as a direction perpendicular to the direction in which the first surface 100a and the second surface 100b of the semiconductor chip 100 extend (for example, the thickness direction of the semiconductor chip 100). You can.

In an exemplary embodiment, the semiconductor chip 100 may have an active layer in a portion adjacent to the first surface 100a. The active layer of the semiconductor chip 100 may include a plurality of various types of individual devices. For example, the plurality of individual devices may be connected to various microelectronic devices, such as a complementary metal-oxide semiconductor transistor (CMOS transistor), a metal-oxide-semiconductor filed effect transistor (MOSFET), or a system large scale LSI. integration), image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active devices, and passive devices.

In an exemplary embodiment, a chip pad (not shown) that is electrically connected to a plurality of individual devices in the active layer may be disposed on the first surface 100a of the semiconductor chip 100. Additionally, as will be described later, the chip pad of the semiconductor chip 100 may be connected to the conductive stud 130.

In an exemplary embodiment, the first redistribution structure 110 may be disposed below the semiconductor chip 100 . In other words, the first redistribution structure 110 may be disposed on the first surface 100a of the semiconductor chip 100.

In addition, the first redistribution structure 110 extends from the inside of the first redistribution insulating layer 117 and is electrically connected to the conductive post 120 and the conductive stud 130. It may include a first redistribution pattern 118 connected to .

The first redistribution line pattern 113 may extend in the horizontal direction within the first redistribution insulating layer 117, and the first redistribution via pattern 115 may extend in the horizontal direction of the first redistribution insulating layer 117. It may extend vertically inside.

In an exemplary embodiment, the number of layers formed by the first redistribution line pattern 113 extending in the horizontal direction within the first redistribution insulating layer 117 may be plural. For example, the number of layers formed by the first redistribution line pattern 113 may be 3 to 7. However, it is not limited to the above, and the layer formed by the first redistribution line pattern 113 may be a single layer.

In an exemplary embodiment, the first redistribution via pattern 115 interconnects a plurality of first redistribution line patterns 113 or connects the first redistribution line pattern 113 and the conductive post 120 to each other. The first redistribution line pattern 113 and the conductive stud 130 may be connected, or the first redistribution line pattern 113 and the first conductive pad 119 may be connected.

In an exemplary embodiment, the first redistribution insulating layer 117 may include an insulating material made of a photo imageable dielectric (PID) material capable of a photo lithography process. For example, the first redistribution insulating layer 117 may include photosensitive polyimide (PSPI). However, the present invention is not limited to this, and the first redistribution insulating layer 117 may include oxide or nitride. For example, the first redistribution insulating layer 117 may include silicon oxide or silicon nitride.

In an exemplary embodiment, the material of the first redistribution via pattern 115 and the first redistribution line pattern 113 may include copper (Cu). However, it is not limited to this, and the materials of the first redistribution via pattern 115 and the first redistribution line pattern 113 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), and tungsten ( W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium ( It may be a metal such as Be), gallium (Ga), ruthenium (Ru), or an alloy thereof.

In an exemplary embodiment, the first redistribution line pattern 113 and the first redistribution via pattern 115 may be electrically connected to the conductive post 120 and the conductive stud 130.

In an exemplary embodiment, the spacing between the plurality of first redistribution line patterns 113 may be about 10 micrometers or less. For example, the horizontal separation distance between the plurality of first redistribution line patterns 113 may be about 1 micrometer to about 3 micrometers. Additionally, the horizontal separation distance between the plurality of first redistribution line patterns 113 may be about 3 micrometers to about 5 micrometers. However, the spacing between the plurality of first redistribution line patterns 113 is not limited to the above.

In an exemplary embodiment, the first conductive pad 119 may contact the first redistribution via pattern 115 . Additionally, at least a portion of the side surface of the first conductive pad 119 may be surrounded by the first redistribution insulating layer 117 . However, without being limited to the above, the side of the first conductive pad 119 may not be surrounded by the first redistribution insulating layer 117.

In an exemplary embodiment, one side of the first conductive pad 119 may be in contact with the external connection terminal 250a, and the other side of the first conductive pad 119 opposite to the first side may be connected to the first redistribution terminal 250a. It may contact the via pattern 115. That is, the first conductive pad 119 may electrically connect the external connection terminal 250a, the first redistribution line pattern 113, and the first redistribution via pattern 115.

In an exemplary embodiment, the conductive post 120 may be a post of a conductive material that passes through the molding layer 140 in a vertical direction. For example, the conductive post 120 may be arranged to surround the side of the semiconductor chip 100.

In an exemplary embodiment, the vertical length of the conductive post 120 may be greater than the vertical length of the semiconductor chip 100. Additionally, the vertical length of the conductive post 120 may be greater than the vertical length of the molding layer 140.

In an exemplary embodiment, the lower surface of the conductive post 120 may contact the first redistribution via pattern 115 of the first redistribution structure 110. Additionally, the upper surface of the conductive post 120 may contact the second redistribution line pattern 113 of the second redistribution structure 210.

Additionally, at least a portion of the conductive post 120 may be surrounded by the second redistribution insulating layer 217 of the second redistribution structure 210 . Additionally, the lower surface of the conductive post 120 may be on the same plane as the upper surface of the first redistribution structure 110, and the upper surface of the conductive post 120 may be at a level higher than the lower surface of the second redistribution structure 210. may be in

In an exemplary embodiment, the conductive posts 120 may be arranged in a zig-zag shape on the first redistribution structure 110 . However, the arrangement structure of the conductive post 120 is not limited to the above.

Additionally, in an exemplary embodiment, the conductive post 120 may have a cylindrical shape or a polygonal pillar shape.

In an exemplary embodiment, the material of the conductive post 120 may include copper (Cu). However, it is not limited to this, and the materials of the conductive post 120 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium. (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. It may be a metal or an alloy thereof.

In an exemplary embodiment, the conductive stud 130 may be a conductive material disposed between the semiconductor chip 100 and the first redistribution structure 110 . For example, the conductive stud 130 may have a cylindrical shape or a polygonal pillar shape.

In an exemplary embodiment, the conductive stud 130 is disposed between the semiconductor chip 100 and the first redistribution structure 110 to connect a plurality of individual devices in the active layer of the semiconductor chip 100 to the first redistribution structure. It can be electrically connected to the line pattern 113 and the first redistribution via pattern 115.

In an exemplary embodiment, the conductive stud 130 may contact a chip pad (not shown) of the semiconductor chip 100. Additionally, the vertical length of the conductive stud 130 may be smaller than the vertical length of the conductive post 120.

Additionally, the material of the conductive stud 130 may include copper (Cu). However, it is not limited to this, and the materials of the conductive stud 130 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium. (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. It may be a metal or an alloy thereof.

In an exemplary embodiment, the second redistribution structure 210 may be disposed below the semiconductor chip 200 . For example, the second redistribution structure 210 may be disposed on the second surface 100b of the semiconductor chip 100.

In addition, the second redistribution structure 210 extends from the inside of the second redistribution insulating layer 217 and electrically connects the conductive post 120 and the conductive stud 130. It may include a second redistribution pattern 118 connected to .

The second redistribution line pattern 213 may extend in the horizontal direction within the second redistribution insulating layer 217, and the second redistribution via pattern 215 may extend in the horizontal direction of the second redistribution insulating layer 217. It may extend vertically inside.

In an exemplary embodiment, the number of layers formed by the second redistribution line pattern 213 extending in the horizontal direction within the second redistribution insulating layer 217 may be plural. For example, the number of layers formed by the second redistribution line pattern 213 may be 3 to 7. However, it is not limited to the above, and the layer formed by the second redistribution line pattern 213 may be a single layer.

In addition, the number of layers formed by the second redistribution line pattern 213 extending in the horizontal direction within the second redistribution insulating layer 217 is determined by the number of layers formed by the second redistribution line pattern 113. It may be smaller than the number of layers extending in the horizontal direction inside the insulating layer 117.

In an exemplary embodiment, a portion of the second redistribution line pattern 213 may contact the conductive post 120 . Additionally, the second redistribution via pattern 215 connects a plurality of second redistribution line patterns 213 to each other or connects the second redistribution line pattern 213 and the second conductive pad 219. You can.

In an exemplary embodiment, the second redistribution insulating layer 217 may include an insulating material made of a PID material capable of a photolithography process. For example, the second redistribution insulating layer 217 may include photosensitive polyimide (PSPI). However, the present invention is not limited to this, and the second redistribution insulating layer 217 may include oxide or nitride. For example, the second redistribution insulating layer 217 may include silicon oxide or silicon nitride.

In an exemplary embodiment, the material of the second redistribution via pattern 215 and the second redistribution line pattern 213 may include copper (Cu). However, it is not limited to this, and the materials of the second redistribution via pattern 215 and the second redistribution line pattern 213 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), and tungsten ( W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium ( It may be a metal such as Be), gallium (Ga), ruthenium (Ru), or an alloy thereof.

In an exemplary embodiment, the second redistribution line pattern 213 and the second redistribution via pattern 215 may be electrically connected to the conductive post 120 and the conductive stud 130.

In an exemplary embodiment, the spacing between the plurality of second redistribution line patterns 213 may be about 10 micrometers or less. For example, the horizontal separation distance between the plurality of second redistribution line patterns 213 may be about 1 micrometer to about 3 micrometers. Additionally, the horizontal separation distance between the plurality of second redistribution line patterns 213 may be about 3 micrometers to about 5 micrometers. However, the spacing between the plurality of second redistribution line patterns 213 is not limited to the above.

In an exemplary embodiment, the second conductive pad 219 may contact the second redistribution via pattern 215 . Additionally, at least a portion of the side surface of the second conductive pad 219 may be surrounded by the second redistribution insulating layer 217 . However, the present invention is not limited to the above, and the side surface of the second conductive pad 219 may not be surrounded by the second redistribution insulating layer 217 .

In an exemplary embodiment, one surface of the second conductive pad 219 may contact a package connection terminal (not shown) of a separate semiconductor package (not shown) mounted on the semiconductor package 10 of the present disclosure. , the other side of the second conductive pad 219 opposite to the one side may contact the second redistribution via pattern 215.

In an exemplary embodiment, the molding layer 140 is disposed between the first redistribution structure 110 and the second redistribution structure 210 and includes the semiconductor chip 100, the conductive post 120, and the conductive stud 130. ), and may surround the adhesive layer 150. For example, the molding layer 140 may be configured to secure the semiconductor chip 100, the conductive post 120, and the conductive stud 130 on the first redistribution structure 110.

In an example embodiment, the molding layer 140 may form the exterior of the semiconductor package 10 together with the first redistribution structure 110 and the second redistribution structure 210 . For example, the side of the molding layer 140, the side of the first redistribution structure 110, and the side of the second redistribution structure 210 may form the side of the semiconductor package 10. Additionally, the side surface of the first redistribution structure 110, the side surface of the second redistribution structure 210, and the side surface of the molding layer 140 may be on the same plane.

In an example embodiment, molding layer 140 may include a material of epoxy molding compound (EMC). However, the material of the molding layer 140 is not limited to the above-described epoxy molding compound, and may include various materials such as epoxy-based materials, thermosetting materials, thermoplastic materials, and UV-treated materials.

In an example embodiment, adhesive layer 150 may be attached to the top surface of semiconductor chip 100 . For example, the adhesive layer 150 may be a die attach film (DAF). However, the type of the adhesive layer 150 is not limited to the above.

In an example embodiment, one side of adhesive layer 150 may be coplanar with one side of molding layer 140 . For example, the lower surface of the adhesive layer 150 may contact the second surface 100b of the semiconductor chip 100, and the side surface of the adhesive layer 150 may be surrounded by the molding layer 140, The top surface of the adhesive layer 150 may be on the same plane as the top surface of the molding layer 140.

Additionally, the side surface of the adhesive layer 150 may be on the same plane as the side surface of the semiconductor chip 100.

In an example embodiment, the top surface of the adhesive layer 150, the top surface of the molding layer 140, and the bottom surface of the second redistribution structure 210 may be on the same plane.

In an exemplary embodiment, the color of adhesive layer 150 may be substantially the same as the color of molding layer 140. For example, the color of the adhesive layer 150 and the color of the molding layer 140 may be black. However, the color of the adhesive layer 150 and the color of the molding layer 140 are not limited to those described above.

For example, when the color of the adhesive layer 150 and the color of the molding layer 140 are the same, the boundary surface between the adhesive layer 150 and the molding layer 140 may not be observed.

In an exemplary embodiment, the adhesive layer 150 is marked on the upper surface including at least one of information of the type, number, performance, name and/or logo of the manufacturing company, manufacturing date, and serial number of the semiconductor chip 100. Can include areas. For example, an ink marking technique or a laser marking technique may be used to mark information on the semiconductor package 10.

In an exemplary embodiment, the external connection terminal 250a is attached to the lower surface of the redistribution structure 110 and may be a connection terminal for electrical connection between the semiconductor chip 100 and an external device.

In an exemplary embodiment, the external connection terminal 250a may be attached to the lower surface of the first conductive pad 119. Additionally, the external connection terminal 250a may be a solder ball made of a metal material containing at least one of tin (Sn), silver (Ag), copper (Cu), and aluminum (Al).

In an exemplary embodiment, at least one of the plurality of external connection terminals 250a may be disposed outside the side of the semiconductor chip 100. Accordingly, the semiconductor package 10 may be a semiconductor package with a fan-out structure.

The top surface of the adhesive layer 150 and the top surface of the molding layer 140 of the semiconductor package 10 according to an exemplary embodiment of the present disclosure may be on the same plane, so that the semiconductor package 10 can be thin and light. there is. In addition, the second redistribution insulating layer 217 of the second redistribution structure 210 of the semiconductor package 10 may surround at least a portion of the conductive post 120, so that the semiconductor package 10 may be thin and light. You can.

In addition, the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include a conductive stud 130 and a conductive post 120, so that the first redistribution line pattern of the first redistribution structure 110 ( 113) and the first redistribution via pattern 115, the second redistribution line pattern 213 and the second redistribution via pattern 215 of the second redistribution structure 210 may be provided in a fine size.

In addition, the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include an adhesive layer 150 disposed on the semiconductor chip 100, so that the structural reliability of the semiconductor package 10 can be improved. there is.

Figure 2 is a cross-sectional view of a semiconductor package 20 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 2, a semiconductor package 20 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 100, a first redistribution structure 110, a conductive post 120, a conductive stud 130, and a molding layer. It may include 140, an adhesive layer 150, a second redistribution structure 210, and an external connection terminal 250b.

Hereinafter, overlapping content between the semiconductor package 10 of FIG. 1 and the semiconductor package 20 of FIG. 2 will be omitted and the differences will be mainly explained.

The semiconductor package 20 of FIG. 2 may have a structure in which the semiconductor package 10 of FIG. 1 is rotated by 180 degrees. In other words, the semiconductor package 20 of FIG. 2 may have a structure in which the semiconductor package 10 of FIG. 1 is flipped upside down.

Specifically, in the semiconductor package 10 of FIG. 1, the first redistribution structure 110 is disposed on the lower part of the semiconductor chip 100, and the second redistribution structure 210 is disposed on the upper part of the semiconductor chip 100. It could be a structure that works. However, in the semiconductor package 20 of FIG. 2, the first redistribution structure 110 is disposed on the upper part of the semiconductor chip 100, and the second redistribution structure 210 is disposed on the lower part of the semiconductor chip 100. It could be a structure.

In an exemplary embodiment, the external connection terminal 250b may be mounted on the second conductive pad 219. That is, the external connection terminal 250b is electrically connected to the second redistribution line pattern 213 and the second redistribution via pattern 215 of the second redistribution structure 210 through the second conductive pad 219. You can.

Figure 3 is a cross-sectional view of a semiconductor package 1 according to an exemplary embodiment of the present disclosure.

The semiconductor package 1 of FIG. 3 may be a package-on-package (pop) type semiconductor package in which an upper semiconductor package 30 is mounted on a lower semiconductor package 10. Since the content related to the lower semiconductor package 10 overlaps with the content described with reference to FIG. 1, detailed information will be omitted.

The upper semiconductor package 30 may include a semiconductor chip 300, a wiring layer 310, a package connection terminal 320, and a molding layer 330.

In an exemplary embodiment, the semiconductor chip 300 of the upper semiconductor package 30 may be the same type of semiconductor chip as the semiconductor chip 100 of the lower semiconductor package 10. However, without being limited to the above, the semiconductor chip 300 of the upper semiconductor package 30 may be a different type of semiconductor chip than the semiconductor chip 100 of the lower semiconductor package 10.

In exemplary embodiments, the semiconductor package 1 is a system in package (SIP) in which different types of semiconductor chips 100 and 300 and various electronic components are electrically connected to each other and operate as one system. It can be.

In an exemplary embodiment, the wiring layer 310 includes a wiring pattern 318 electrically connected to a plurality of individual devices in the active layer of the semiconductor chip 300, and a wiring insulating layer 317 surrounding the wiring pattern 318. ) may include.

In an exemplary embodiment, the wiring layer 310 may be a redistribution structure that includes a redistribution pattern and a redistribution insulating layer surrounding the redistribution pattern. However, the wiring layer 310 is not limited to this, and may include a printed circuit board (PCB).

The package connection terminal 320 may be a terminal that connects the lower semiconductor package 10 and the upper semiconductor package 30. In an exemplary embodiment, the package connection terminal 320 may be interposed between the second redistribution structure 210 of the lower semiconductor package 10 and the wiring layer 310 of the upper semiconductor package 30.

The molding layer 330 may be mounted on top of the wiring layer 310 and surround the semiconductor chip 300. For example, molding layer 330 may include a material of epoxy molding compound (EMC). However, the material of the molding layer 330 is not limited to the above-described epoxy molding compound, and may include various materials such as epoxy-based materials, thermosetting materials, thermoplastic materials, and UV-treated materials.

Figure 4 is a cross-sectional view of a semiconductor package 2 according to an exemplary embodiment of the present disclosure.

The semiconductor package 2 in FIG. 4 may be a package-on-package (pop) type semiconductor package in which the upper semiconductor package 40 is mounted on the lower semiconductor package 10. Since the content related to the lower semiconductor package 10 overlaps with the content described with reference to FIG. 1, detailed information will be omitted.

The upper semiconductor package 40 may include a plurality of semiconductor chips 400a and 400b, a wiring layer 410, a package connection terminal 420, and a molding layer 430. Hereinafter, overlapping content between the upper semiconductor package 30 of FIG. 3 and the upper semiconductor package 40 of FIG. 4 will be omitted and the differences will be mainly explained.

A plurality of semiconductor chips 400a and 400b may be stacked in a vertical direction. For example, each of the plurality of semiconductor chips 400a and 400b may include an active layer including a plurality of individual devices.

Additionally, the plurality of semiconductor chips 400a and 400b may include a through electrode TSV that passes through at least a portion of the plurality of semiconductor chips 400a and 400b in the vertical direction. The active layers of each of the plurality of semiconductor chips 400a and 400b may be electrically connected to each other through a through electrode (TSV).

However, without being limited to the above, the plurality of semiconductor chips 400a and 400b may be electrically connected to each other through wire bonding.

Figure 5 is a cross-sectional view of a semiconductor package 3 according to an exemplary embodiment of the present disclosure.

The semiconductor package 3 in FIG. 5 may be a package-on-package (pop) type semiconductor package in which the upper semiconductor package 30 is mounted on the lower semiconductor package 20. Since the content related to the lower semiconductor package 20 overlaps with the content described with reference to FIG. 2 and the content related to the upper semiconductor package 30 overlaps with the content described with reference to FIG. 3, detailed information will be omitted.

In an exemplary embodiment, the package connection terminal 320 of the upper semiconductor package 30 is between the first redistribution structure 210 of the lower semiconductor package 20 and the wiring layer 310 of the upper semiconductor package 30. may be involved.

FIGS. 6A to 6K are diagrams showing each step of a method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure.

Hereinafter, a method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 6A to 6K. Specifically, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may be the method of manufacturing the semiconductor package 10 of FIG. 1 .

Referring to FIG. 6A, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include forming a second conductive pad 219 on the carrier substrate CS (S1100). there is.

In an exemplary embodiment, the carrier substrate CS may be provided as a variety of materials such as wafer, glass substrate, PCB, EMC, GFS, ceramic, epoxy, PI, basalt, etc. However, the material of the carrier substrate CS is not limited to the above.

In an exemplary embodiment, the shape of the carrier substrate CS may be circular or polygonal (eg, triangle, square, pentagon, hexagon, etc.). However, the shape of the carrier substrate CS is not limited to the above. For example, the carrier substrate CS may be a circular or polygonal plate with a width of 200 mm to 600 mm.

Referring to FIG. 6B, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure includes forming a second redistribution insulating layer 217 on a carrier substrate CS, and forming the second redistribution insulating layer 217 on a carrier substrate CS. It may include patterning the insulating layer 217 (S1200).

In an exemplary embodiment, forming the second redistribution insulating layer 217 may be performed through a spin coating process, and patterning the second redistribution insulating layer 217 may be performed through a photo lithography process and an etching process. It can be performed through processes, etc.

In an exemplary embodiment, in step S1200, the second redistribution insulating layer 217 may expose at least a portion of the second conductive pad 218.

Referring to FIG. 6C, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure includes forming a second redistribution line pattern 213 and a second redistribution via pattern 215 (S1300). ) may include.

In an exemplary embodiment, the step of forming the second redistribution line pattern 213 and the second redistribution via pattern 215 (S1300) includes forming a seed layer (not shown) and using the seed layer. It may include forming a second redistribution line pattern 213 and a second redistribution via pattern 215 through a plating process.

Referring to FIGS. 6D and 6E together, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure includes forming a second redistribution insulating layer 217 (S1400), and second growing. It may further include forming a line pattern 213 and a second redistribution via pattern 215 (S1500).

In an exemplary embodiment, when steps S1400 and S1500 are performed, the second redistribution line pattern 213 of the second redistribution structure 210 may form a plurality of layers extending in the horizontal direction.

However, when the manufacturing method of the semiconductor package 10 of the present disclosure omits steps S1400 and S1500, the second redistribution line pattern 213 of the second redistribution structure 210 is a single layer extending in the horizontal direction. may form.

Additionally, in step S1500, the second redistribution insulating layer 217 may expose at least a portion of the second redistribution line pattern 213. A portion of the second redistribution line pattern 213 exposed by the second redistribution insulating layer 217 may be connected to a conductive post 120 to be described later.

Referring to FIG. 6F, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include forming a conductive post 120 on the second redistribution structure 210 (S1600). You can.

In an exemplary embodiment, the conductive post 120 may contact a portion of the second redistribution line pattern 213 of the second redistribution structure 210 . Additionally, at least a portion of the conductive post 120 may be surrounded by the second redistribution insulating layer 217 of the second redistribution structure 210 . Accordingly, the structural reliability of the conductive post 120 can be improved.

Referring to FIG. 6G, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure includes a semiconductor structure in which an adhesive layer 150, a semiconductor chip 100, and a conductive stud 130 are sequentially stacked. It may include mounting (ST1) on the second redistribution structure 210 (S1700).

In an exemplary embodiment, in step S1700, the first semiconductor structure ST1 may be firmly attached to the upper surface of the second redistribution structure 210 by the adhesive layer 150.

After performing step S1700, at least a portion of the carrier substrate CS may be removed so that the carrier substrate CS has a predetermined vertical length. For example, at least a portion of the carrier substrate CS may be ground.

Additionally, after at least a portion of the carrier substrate CS is ground, the structure in step S1700 may be individualized. Additionally, before performing step S1800, the individualized structure of step S1700 may be placed on a separate carrier substrate (not shown). Additionally, due to the performance of step S1800, the individualized structure of step S1700 disposed on the separate carrier substrate (not shown) may be molded by the molding layer 140.

Referring to FIG. 6H, the manufacturing method of the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include forming a molding layer 140 on the second redistribution structure 210 (S1800). You can.

In an exemplary embodiment, the molding layer 140 may surround the first semiconductor structure ST1 and the conductive post 120 on the second redistribution structure 210 . For example, the material of molding layer 140 may include epoxy molding compound (EMC). However, it is not limited to the above, and the material of the molding layer 140 may include an epoxy-based material, a thermosetting material, a thermoplastic material, a UV-treated material, etc.

Referring to FIG. 6I, in the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure, one surface of the conductive post 120 and the conductive stud 130 of the first semiconductor structure ST1 are formed by forming a molding layer. Removing at least one of a portion of the molding layer 140, a portion of the conductive post 120, and a portion of the conductive stud 130 until exposed from 140 (S1900) It can be included.

In an example embodiment, molding layer 140 may be removed by a grinding process. For example, at least a portion of the molding layer 140 until one side of the molding layer 140, one side of the conductive post 120, and one side of the conductive stud 130 are on the same plane. This can be removed.

Referring to FIG. 6J , the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include forming the first redistribution structure 110 (S2000).

In an exemplary embodiment, forming the first redistribution structure 110 (S2000) includes forming a first redistribution insulating layer 117 on the molding layer 140, the first redistribution insulating layer It may include forming a first redistribution line pattern 113 and a first redistribution via pattern 115 on (117).

Since the step of forming the first redistribution structure 110 overlaps with the step of forming the second redistribution structure 210 described with reference to FIGS. 6B to 6E, detailed information will be omitted.

Additionally, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include forming a first conductive pad 119 on the first redistribution structure 110 .

Additionally, after performing step S2000, forming an external connection terminal 250a on the first conductive pad 119 may be performed. The external connection terminal 250a may be attached to one side of the first conductive pad 119.

In an exemplary embodiment, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may further include forming a passive element on the first redistribution structure 110 . For example, forming the passive element may be performed simultaneously with forming the external connection terminal 250a. However, without being limited to the above, the step of forming the passive element may be performed before the step of forming the external connection terminal 250a, or may be performed after the step of forming the external connection terminal 250a.

Referring to FIG. 6K, the method of manufacturing the semiconductor package 10 according to an exemplary embodiment of the present disclosure may include removing the carrier substrate CS (S2100).

Due to performing the steps of FIGS. 6A to 6K , manufacturing of the semiconductor package 10 according to an exemplary embodiment of the present disclosure may be completed.

Figure 7 is a cross-sectional view of a semiconductor package 70 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 7, a semiconductor package 70 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 1000, a conductive post 1200, a conductive stud 1300, a first molding layer 1400, and an adhesive layer ( 1500), a first redistribution structure 1500, a second redistribution structure 1600, and a conductive pillar 1700. It may include a second molding layer 1800 and an external connection terminal 1900.

In an exemplary embodiment, the first redistribution structure 1500 includes a first redistribution insulating layer 1510 disposed on the first side 1000a of the semiconductor chip 1000, and the first redistribution insulating layer 1510 ) may include a first redistribution line pattern 1520 and a first redistribution via pattern 1530 extending inside the conductive post 1200 and the conductive stud 1300.

In addition, the second redistribution structure 1600 includes a second redistribution insulating layer 1610 disposed on the second surface 1000b of the semiconductor chip 1000, and an inside of the second redistribution insulating layer 1610. It may include a second redistribution line pattern 1620 and a second redistribution via pattern 1630 that are extended and electrically connected to the conductive post 1200.

Hereinafter, overlapping content between the semiconductor package 70 of FIG. 7 and the semiconductor package 10 of FIG. 1 will be omitted and the differences will be mainly explained.

The conductive pillar 1700 may be disposed on the second redistribution structure 1600. Additionally, the conductive pillar 1700 may be electrically connected to the second redistribution line pattern 1620 and the second redistribution via pattern 1630. For example, the conductive pillar 1700 may contact a portion of the second redistribution line pattern 1620.

In an exemplary embodiment, the vertical length of the conductive pillar 1700 may be smaller than the vertical length of the conductive post 1200. Additionally, the vertical length of the conductive pillar 1700 may be greater than the vertical length of the conductive stud 1300.

In an exemplary embodiment, the vertical length of the conductive pillar 1700 may be greater than the length of the plurality of second redistribution line patterns 1620 in the vertical direction. Accordingly, resistance can be reduced and the electrical characteristics of the semiconductor package 70 can be improved.

In an exemplary embodiment, the material of the conductive pillar 1700 may include copper (Cu). However, it is not limited to this, and the materials of the conductive pillar 1700 include nickel (Ni), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), and indium. (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. It may be a metal or an alloy thereof.

The second molding layer 1800 may be disposed on the second redistribution structure 1600 and cover the side surface of the conductive pillar 1700. Additionally, the second molding layer 1800 may expose one side of the conductive pillar 1700 to the outside. For example, one side of the second molding layer 1800 and one side of the conductive pillar 1700 may be on the same plane.

In an example embodiment, the second molding layer 1800 may include a material of epoxy molding compound (EMC). However, the material of the molding layer 140 is not limited to the above-described epoxy molding compound, and may include various materials such as epoxy-based materials, thermosetting materials, thermoplastic materials, and UV-treated materials.

In an example embodiment, the material of the second molding layer 1800 may be substantially the same as the material of the first molding layer 1400. Since the materials of the first molding layer 1400 and the second molding layer 1800 may be substantially the same, warpage of the semiconductor package due to a difference in coefficient of thermal expansion (CTE) can be improved. However, it is not limited to the above, and the material of the second molding layer 1800 may be different from the material of the first molding layer 1400.

The semiconductor package 70 according to an exemplary embodiment of the present disclosure may include a conductive pillar 1700 disposed on the second redistribution structure 1600, so that the semiconductor package 70 and the semiconductor package 70 ) Electrical connection between separate semiconductor packages (not shown) mounted on the device can be facilitated. For example, even when a separate semiconductor package has a redistribution pattern formed at a fine size, the semiconductor package 70 of the present disclosure may include a conductive pillar 1700, so that the semiconductor package 70 and the separate Electrical connection between semiconductor packages can be easy.

In addition, the semiconductor package 70 according to an exemplary embodiment of the present disclosure may include a second molding layer 1800 disposed on the second redistribution structure 1600 and surrounding the conductive pillar 1700, The warpage phenomenon of the semiconductor package 70 can be reduced.

In addition, the number of layers formed in the horizontal direction by the first redistribution line pattern 1520 of the semiconductor package 70 according to an exemplary embodiment of the present disclosure is the same as the number of layers formed by the second redistribution line pattern 1620 in the horizontal direction. Since the number of layers may be greater than that of the semiconductor package 70, the signal integrity (SI) of the semiconductor package 70 may be improved.

Additionally, the semiconductor package 70 according to an exemplary embodiment of the present disclosure may include a conductive pillar 1700, so heat dissipation performance of the semiconductor package 70 may be improved.

Figure 8 is a cross-sectional view of a semiconductor package 80 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 8, the semiconductor package 80 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 1000, a conductive post 1200, a conductive stud 1300, a first molding layer 1400, and an adhesive layer ( 1500), a first redistribution structure 1500, a second redistribution structure 1600, and a conductive pillar 1700. It may include a second molding layer 1800, an external connection terminal 1900, and a package connection pad 1950.

Hereinafter, overlapping content between the semiconductor package 80 of FIG. 8 and the semiconductor package 70 of FIG. 7 will be omitted and the differences will be mainly explained.

The package connection pad 1950 is mounted on one side of the conductive pillar 1700 and electrically connects the semiconductor package 80 of the present disclosure and a separate semiconductor package (not shown) mounted on the semiconductor package 80. It may be a pad configured to do so.

In an example embodiment, the sides of the package connection pad 1950 may be surrounded by the second molding layer 1800. Additionally, one side of the package connection pad 1950 may be exposed from the second molding layer 1800. For example, one side of the package connection pad 1950 may be on the same plane as one side of the second molding layer 1800.

In an exemplary embodiment, the horizontal length of the package connection pad 1950 may be greater than the horizontal length of the conductive pillar 1700.

9A to 9I are diagrams showing each step of a method of manufacturing a semiconductor package 70 according to an exemplary embodiment of the present disclosure. Hereinafter, a method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure will be described in detail with reference to FIGS. 9A to 9I.

Referring to FIG. 9A , the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure may include forming a conductive pillar 1700 on the carrier substrate CS (S3100).

In an exemplary embodiment, the carrier substrate CS may be provided as a variety of materials such as wafer, glass substrate, PCB, EMC, GFS, ceramic, epoxy, PI, basalt, etc. However, the material of the carrier substrate CS is not limited to the above.

In an exemplary embodiment, the shape of the carrier substrate CS may be circular or polygonal (eg, triangle, square, pentagon, hexagon, etc.). However, the shape of the carrier substrate CS is not limited to the above. For example, the carrier substrate CS may be a circular or polygonal plate with a width of 200 mm to 600 mm.

In an exemplary embodiment, the conductive pillar 1700 may be formed on the carrier substrate CS through a photolithography process, an etching process, a plating process, etc. For example, the conductive pillar 1700 may be formed through a metal plating method.

However, the present invention is not limited to this, and the conductive pillar 1700 may be formed using a wire bonding method. For example, the conductive pillar 1700 may be formed through a process of standing a wire of a conductive material in a vertical direction on the carrier substrate CS.

However, the method of forming the conductive pillar 1700 is not limited to the above description, and may be formed by various methods.

Referring to FIG. 9B, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure may include forming a second molding layer 1800 on the carrier substrate CS (S3200). .

In an exemplary embodiment, the second molding layer 1800 may cover the side and top surfaces of the conductive pillar 1700 on the carrier substrate CS.

Referring to FIG. 9C, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure includes removing at least a portion of the second molding layer 1800 until one side of the conductive pillar 1700 is exposed. It may include a step (S3300).

Referring to FIG. 9D, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure includes forming a second redistribution structure 1600 on the second molding layer 1800 (S3400). can do.

In an exemplary embodiment, step S3400 includes forming a second redistribution insulating layer 1610 on the second molding layer 1800, and forming a second redistribution line on the second redistribution insulating layer 1610. It may include forming a pattern 1620 and a second redistribution via pattern 1630.

In an exemplary embodiment, forming the second redistribution line pattern 1620 and the second redistribution via pattern 1630 on the second redistribution insulating layer 1610 includes a photo lithography process, an etching process, and It can be performed through a plating process, etc.

In an exemplary embodiment, a portion of the second redistribution line pattern 1620 may contact the conductive pillar 1700. Accordingly, the conductive pillar 1700 may be electrically connected to the second redistribution line pattern 1620 and the second redistribution via pattern 1630 of the second redistribution structure 1600.

Referring to FIG. 9E , a method of manufacturing a semiconductor package 70 according to an exemplary embodiment of the present disclosure may include forming a conductive post 1200 on the second redistribution structure 1600 .

In an exemplary embodiment, the conductive post 1200 may be electrically connected to the second redistribution line pattern 1620 and the second redistribution via pattern 1630. Additionally, at least a portion of the conductive post 1200 may be surrounded by the second redistribution insulating layer 1610.

Referring to FIG. 9F, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure includes a structure in which an adhesive layer 1500, a semiconductor chip 1000, and a conductive stud 1300 are sequentially stacked. 1 may include mounting the semiconductor structure ST1 on the second redistribution structure 1600 (S3600).

In an example embodiment, the semiconductor chip 1000 may be attached to the upper redistribution structure 1600 through an adhesive layer 1400 . Additionally, the first semiconductor structure ST1 may be disposed between the conductive posts 1200.

In an exemplary embodiment, after performing step S3600, at least a portion of the carrier substrate CS may be removed so that the carrier substrate CS has a predetermined vertical length. For example, at least a portion of the carrier substrate CS may be ground.

Additionally, after at least a portion of the carrier substrate CS is ground, the structure in step S3600 may be individualized. Additionally, before performing step S3700, the individualized structure of step S3600 may be placed on a separate carrier substrate (not shown). In addition, due to the performance of step S3700, which will be described later, the individualized structure of step S3600 disposed on the separate carrier substrate (not shown) may be molded by the molding layer 1400.

Referring to FIG. 9G, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure includes forming a first molding layer 1400 on the second redistribution structure 1600 (S3700). can do.

In an exemplary embodiment, step S3700 includes forming a first molding layer 1400 on the second redistribution structure 1600 to surround the conductive post 1200 and the first semiconductor structure ST1, and forming a conductive layer 1400 on the second redistribution structure 1600. It may include removing at least a portion of the first molding layer 1400 so that one side of the post 1200 and one side of the conductive stud 1300 of the first semiconductor structure ST1 are on the same plane. .

Referring to FIG. 9H, the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure includes forming a first redistribution structure 1500 on the first molding layer 1400 (S3800). can do.

In an exemplary embodiment, step S3800 includes forming a first redistribution insulating layer 1510 on the first molding layer 1400, and forming a first redistribution line on the first redistribution insulating layer 1510. It may include forming a pattern 1520 and a first redistribution via pattern 1530.

In an exemplary embodiment, forming the first redistribution line pattern 1520 and the first redistribution via pattern 1530 on the first redistribution insulating layer 1510 includes a photo lithography process, an etching process, and It can be performed through a plating process, etc.

In an exemplary embodiment, after performing step S3800, a step of forming an external connection terminal 1900 on the first redistribution structure 1500 may be additionally performed. For example, the external connection terminal 1900 may be electrically connected to the first redistribution line pattern 1520 and the first redistribution via pattern 1530 of the first redistribution structure 1500.

In an exemplary embodiment, the method of manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure may further include forming a passive element on the first redistribution structure 1500 . For example, forming the passive element may be performed simultaneously with forming the external connection terminal 1900. However, without being limited to the above, the step of forming the passive element may be performed before the step of forming the external connection terminal 1900, or may be performed after the step of forming the external connection terminal 1900.

Referring to FIG. 9I , the method of manufacturing the semiconductor package 70 according to an exemplary embodiment of the present disclosure may include removing the carrier substrate CS (S3900).

In an exemplary embodiment, when the carrier substrate CS is removed, one side of the second molding layer 1800 and one side of the conductive pillar 1700 may be disposed on the same plane.

10A and 10B are diagrams showing some steps of a method of manufacturing a semiconductor package 80 according to an exemplary embodiment of the present disclosure. Specifically, the manufacturing method of the semiconductor package 80 according to an exemplary embodiment of the present disclosure may be the manufacturing method of the semiconductor package 80 described with reference to FIG. 8 .

Referring to FIG. 10A , the method of manufacturing the semiconductor package 80 according to an exemplary embodiment of the present disclosure may include forming a package connection pad 1950 on the carrier substrate CS (S4100).

Referring to FIG. 10B , the method of manufacturing the semiconductor package 80 according to an exemplary embodiment of the present disclosure may include forming a conductive pillar 1700 on the package connection pad 1950 (S4200).

In an exemplary embodiment, after performing step S4200, the steps described above with reference to FIGS. 9B to 9I may be performed. Accordingly, manufacturing of the semiconductor package 80 described with reference to FIG. 8 can be completed.

Figure 11 is a cross-sectional view of a semiconductor package 11 according to an exemplary embodiment of the present disclosure.

The semiconductor package 11 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 100, a redistribution structure 110 including a redistribution insulating layer 117 and a redistribution pattern 118, and a conductive post 120. , it may include a conductive stud 130, a molding layer 140, and a wiring board (DS).

Hereinafter, overlapping content between the semiconductor package 10 of FIG. 1 and the semiconductor package 11 of FIG. 11 will be omitted and the differences will be mainly explained.

In an exemplary embodiment, the wiring board DS may be disposed on the second side 100b of the semiconductor chip 100. Specifically, the wiring board DS may be disposed on top of the adhesive layer 150 and the molding layer 140 .

In an example embodiment, the wiring board DS may include a printed circuit board (PCB). Specifically, the wiring board DS may be a printed circuit board including a circuit pattern DS_p and a wiring insulating layer DS_d surrounding the circuit pattern DS_p.

In an exemplary embodiment, the wiring board DS may contact the conductive post 120 . Specifically, the circuit pattern DS_p of the wiring board DS may be in contact with the conductive post 120 and electrically connected to the conductive post 120 .

In an exemplary embodiment, one side of the wiring board DS may be on the same plane as one side of the conductive post 120, one side of the adhesive layer 150, and one side of the molding layer 140. .

The semiconductor package 80 according to an exemplary embodiment of the present disclosure may include a wiring board DS disposed on the second side 100b of the semiconductor chip 100 and connected to the conductive post 120, Electrical connection between the semiconductor package 80 of the disclosure and a separate semiconductor package (not shown) mounted on the semiconductor package 80 may be facilitated.

12A to 12D are diagrams showing each step of the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure.

Hereinafter, a method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure will be described with reference to FIGS. 12A to 12D. Specifically, the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure may be the method of manufacturing the semiconductor package 11 of FIG. 11 .

Referring to FIG. 12A , the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure may include forming a conductive post 120 on the wiring board DS (S5100).

Before performing step S5100, the support substrate SS may be attached to the lower portion of the wiring substrate DS. For example, the support substrate SS may include a silicon substrate or a glass fiber substrate. However, step S5100 may be performed with the support substrate SS omitted.

In an exemplary embodiment, the conductive post 120 may be mounted on the wiring board DS and electrically connected to the circuit pattern DS_p.

Referring to FIG. 12B, the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure includes a structure in which an adhesive layer 150, a semiconductor chip 100, and a conductive stud 130 are sequentially stacked. 1 It may include mounting the semiconductor structure ST1 on the wiring board DS (S3500).

In an exemplary embodiment, the semiconductor chip 100 may be attached to the wiring board DS through an adhesive layer 150 . Additionally, the first semiconductor structure ST1 may be disposed between the conductive posts 120 .

Referring to FIG. 12C , the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure may include forming a molding layer 140 on the wiring board DS (S5300).

In an exemplary embodiment, step S5300 includes forming a molding layer 140 on the wiring substrate DS to surround the conductive post 120 and the first semiconductor structure ST1, and forming the molding layer 140 on the conductive post 120. It may include removing at least a portion of the molding layer 140 so that one side of the conductive stud 130 of the first semiconductor structure ST1 is on the same plane.

Referring to FIG. 12D , the method of manufacturing the semiconductor package 11 according to an exemplary embodiment of the present disclosure may include forming the redistribution structure 110 on the molding layer 140 (S5400).

In an exemplary embodiment, step S5400 includes forming a redistribution insulating layer 117 on the molding layer 140, and forming a redistribution pattern 118 on the redistribution insulating layer 117. It can be included.

In an exemplary embodiment, forming the redistribution pattern 118 on the redistribution insulating layer 117 may be performed through a photolithography process, an etching process, a plating process, etc.

In an exemplary embodiment, after forming the redistribution structure 110, a step of forming an external connection terminal 160 on the redistribution structure 110 may be additionally performed. For example, the external connection terminal 160 may be electrically connected to the redistribution pattern 118 of the redistribution structure 110.

Additionally, after performing step S5400, a step of removing the carrier substrate CS may be performed. Through the steps described above with reference to FIGS. 12A to 12D , manufacturing of the semiconductor package 11 according to an exemplary embodiment of the present disclosure can be completed.

Figure 13 is a cross-sectional view of the semiconductor package 13_I according to an exemplary embodiment of the present disclosure.

Referring to FIG. 13, the semiconductor package 13 according to an exemplary embodiment of the present disclosure includes a semiconductor chip 1000_I, a first redistribution structure 1100_I, a conductive post 1200_I, a conductive stud 1300_I, and a molding layer. It may include (1400_I), an adhesive layer (1500_I), a second redistribution structure (2100_I), an external connection terminal (2500_I), and a passive element (3000_I).

Hereinafter, overlapping content between the semiconductor package 10 of FIG. 1 and the semiconductor package 13_I of FIG. 13 will be omitted and the differences will be mainly described.

The passive element 3000_I may be disposed below the first redistribution structure 1100_I. For example, the passive element 3000_I may be mounted on the first conductive pad 1190_I and electrically connected to the first redistribution line pattern 1130_I and the first redistribution via pattern 1150_I.

In an exemplary embodiment, the passive element 3000_I may be electrically connected to the semiconductor chip 1000_I. Additionally, the passive element 3000_I may perform at least one of the functions of a capacitor, an inductor, and a resist.

In an exemplary embodiment, the sidewall of the first redistribution structure 1100_I may be formed to be inclined with respect to the sidewall of the molding layer 1400_I. That is, the sidewall of the first redistribution structure 1100_I may not be disposed on the same plane as the sidewall of the molding layer 1400_I.

For example, the first redistribution structure 1100_I may have a tapered structure in which the cross-sectional area in the horizontal direction becomes smaller as it approaches the external connection terminal 2500_I. That is, the first redistribution structure 1100_I may have a tapered structure in which the cross-sectional area in the horizontal direction becomes smaller as the vertical distance from the semiconductor chip 1000_I increases.

For example, in the individualization process (eg, sawing process) of the semiconductor package 13, a portion of the first redistribution structure 1100_I is removed, so that the shape of the first redistribution structure 1100_I is changed to the shape described above. It can be formed into a tapered structure.

In an exemplary embodiment, when looking at a cross section of the first redistribution structure 1100_I, the first vertex formed by meeting the top and side surfaces of the first redistribution structure 1100_I is the top surface of the first redistribution structure 1100_I. And it may be disposed inside the second vertex formed by meeting the side surfaces.

The upper surface of the first redistribution structure 1100_I may be one side of the first redistribution structure 1100_I adjacent to the molding layer 1400_I, and the lower surface of the first redistribution structure 1100_I may be an external connection terminal 2500_I. ) may be one side of the first redistribution structure 1100_I adjacent to the redistribution structure 1100_I.

In an example embodiment, the sidewall of the first redistribution structure 1100_I and the sidewall of the molding layer 1400_I may be on the same plane.

In an example embodiment, the molding layer 1400_I may wrap the sides of the second redistribution structure 2100_I. That is, the sidewall of the second redistribution structure 2100_I may be closer to the semiconductor chip 1000_I than the sidewall of the molding layer 1400_I. Additionally, the sidewall of the second redistribution structure 2100_I may not be exposed to the outside.

In an exemplary embodiment, the vertical length of the first molding portion of the molding layer 1400_I disposed between the upper surface of the first redistribution structure 1100_I and the lower surface of the second redistribution structure 2100_I is, It may be smaller than the vertical length of the second molding portion disposed on the upper surface of the redistribution structure 1100_I and surrounding the side of the second redistribution structure 2100_I.

In an exemplary embodiment, the semiconductor package 13 of FIG. 13 may be manufactured using the structure shown in FIG. 6G.

In an example embodiment, the second redistribution structure 210 of FIG. 6G may correspond to the second redistribution structure 2100_I of FIG. 13 . A plurality of the structures of FIG. 6G may be provided, and the plurality of structures of FIG. 6G may be disposed on a carrier substrate (not shown).

The carrier substrate may be provided in various materials such as wafer, glass substrate, PCB, EMC, GFS, Ceramic, epoxy, PI, Basalt, etc. However, the material of the carrier substrate is not limited to the above. In an exemplary embodiment, the shape of the carrier substrate may be a circular or polygonal (eg, triangle, square, pentagon, hexagon, etc.) shaped substrate. However, the shape of the carrier substrate is not limited to the above. For example, the carrier substrate may be a circular or polygonal plate with a width of 200 mm to 600 mm.

In an example embodiment, after the structures of FIG. 6G are disposed on a carrier substrate (not shown), at least a portion of the carrier substrate may be ground to have a predetermined thickness. However, the grinding process of the carrier substrate described above may be omitted.

With the structures of FIG. 6G disposed on a carrier substrate, the molding layer 1300_I of FIG. 13 may surround the structures of FIG. 6G on the carrier substrate. In this case, the molding layer 1300_I may surround the side of the second redistribution structure 2100_I. The technical idea of the present disclosure described above is not limited to the above-described embodiments and the attached drawings. In addition, it will be clear to those skilled in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present disclosure.

Claims (16)

a semiconductor chip having a first side adjacent to the active layer and a second side opposite the first side;
a conductive stud disposed on the first side of the semiconductor chip and connected to the active layer;
an adhesive layer disposed on the second side of the semiconductor chip;
a conductive post disposed outside the semiconductor chip;
A first redistribution structure on the first side of the semiconductor chip, comprising: a first redistribution insulating layer supporting the conductive studs and the conductive posts; a first redistribution line pattern extending in a horizontal direction within the first redistribution insulating layer; and a first redistribution via pattern extending in a vertical direction within the first redistribution insulating layer;
A second redistribution structure on the second side of the semiconductor chip, comprising: a second redistribution insulating layer disposed on the adhesive layer; and a second redistribution line pattern extending in the horizontal direction within the second redistribution insulating layer. and a second redistribution via pattern extending vertically inside the second redistribution insulating layer;
a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post;
Including,
The top surface of the adhesive layer is flat,
the first molding layer is in direct contact with the conductive stud,
a conductive pillar disposed on the second redistribution structure and connected to the second redistribution line pattern and the second redistribution via pattern of the second redistribution structure; and
a second molding layer disposed on the second redistribution structure and surrounding a side of the conductive pillar;
A semiconductor package further comprising: According to claim 1,
The conductive post is,
Passing through the first molding layer in a vertical direction,
The second redistribution insulating layer of the second redistribution structure is:
A semiconductor package surrounding at least a portion of the conductive post. According to claim 1,
The number of layers formed by the first redistribution line pattern of the first redistribution structure in the horizontal direction is,
A semiconductor package, wherein the second redistribution line pattern of the second redistribution structure is greater than the number of layers formed in the horizontal direction. According to claim 1,
One side of the conductive post is,
Contacting the first redistribution via pattern of the first redistribution structure,
The other side of the conductive post opposite to the one side is,
A semiconductor package, characterized in that it contacts the second redistribution line pattern of the second redistribution structure. delete According to claim 1,
A semiconductor package, wherein one side of the second molding layer and one side of the conductive pillar are on the same plane. According to claim 1,
The semiconductor package is,
A semiconductor package, wherein one side of the second molding layer is on the same plane as one side of the package connection pad. According to claim 1,
A semiconductor package, wherein a first vertex formed by meeting the top and side surfaces of the first redistribution structure is disposed inside a second vertex formed by meeting the top and side surfaces of the first redistribution structure. According to claim 1,
The side walls of the second redistribution structure are,
A semiconductor package, characterized in that it is surrounded by the first molding layer. According to clause 9,
The vertical length of the first molding portion of the molding layer disposed between the upper surface of the first redistribution structure and the lower surface of the second redistribution structure is:
A semiconductor package, characterized in that it is smaller than the vertical length of the second molding portion disposed on the upper surface of the first redistribution structure and surrounding a side of the second redistribution structure. According to claim 1,
a passive element disposed on the first redistribution structure;
A semiconductor package further comprising: According to claim 1,
The second redistribution structure is,
A semiconductor package characterized as a printed circuit board (PCB). forming a first redistribution structure;
forming a conductive post on the first redistribution structure;
Mounting a semiconductor structure in which an adhesive layer, a semiconductor chip, and a conductive stud are sequentially stacked on the first redistribution structure;
forming a first molding layer to surround the semiconductor structure;
At least one of a portion of the first molding layer, a portion of the conductive post, and a portion of the conductive stud is exposed such that one side of the conductive post and one side of the conductive stud are exposed from the first molding layer. steps being removed; and
forming a second redistribution structure connected to the conductive post and the conductive stud on the first molding layer;
Including,
The top surface of the adhesive layer is flat,
the first molding layer is in direct contact with the conductive stud,
forming a package connection pad on a carrier substrate;
forming a conductive pillar on the package connection pad;
forming a second molding layer on the carrier substrate; and
removing at least one of a portion of the second molding layer and a portion of the conductive pillar so that one surface of the conductive pillar is exposed from the second molding layer;
It further includes,
A semiconductor package manufacturing method, characterized in that the conductive line pattern and the conductive via pattern of the second redistribution structure are connected to the conductive pillar. According to claim 13,
The step of forming the first redistribution structure includes:
forming the first redistribution structure on the second molding layer to be connected to the conductive pillar;
A semiconductor package manufacturing method comprising: delete According to claim 13,
The semiconductor package manufacturing method is,
After mounting the semiconductor structure on the first redistribution structure, individualizing a first structure composed of the first redistribution structure, the conductive post, and the semiconductor structure; and
disposing the first structure on a carrier substrate;
It further includes,
Forming a first molding layer to surround the semiconductor structure,
forming a first molding layer to surround the first structure on the carrier substrate,
The semiconductor package manufacturing method is,
A semiconductor package manufacturing method further comprising removing the carrier substrate after forming the first molding layer.

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