KR102623007B1 - 3-Level DC-DC Converter Including multi-phase - Google Patents

Abstract

This is a technology related to 3-level DC-DC converter. The 3-level DC-DC converter includes a capacitor, a first converting unit including a plurality of switches for charging and discharging the capacitor, connected to an output node of the first converting unit, an inductor, and the first converting unit using the inductor. It may include a second converting unit including a switching unit that selectively supplies or discharges a negative output voltage, and an output unit connected to the second converting unit. The first converting unit consists of a single unit, and the second converting unit consists of a plurality of units, so that the 3-level DC-DC converter may include one capacitor.

Description

3-Level DC-DC Converter Including multi-phase}

The present invention relates to power conversion systems, and more specifically to a three-level DC-DC converter with multiple phases.

A DC-DC converter is a device that converts a direct current (DC) voltage source from one voltage level to another voltage level. As the integration density of semiconductor devices decreases, such DC-DC converters can be mainly used to convert the power supply voltage to a relatively low operating voltage. As described above, the DC-DC converter is a buck DC-DC converter that generates a low output voltage for a high input voltage, as well as a boost DC-DC converter that generates a high output voltage compared to the input voltage. It may include a converter and/or a buck-boost DC-DC converter that produces a high or low output voltage relative to the input voltage.

General DC-DC converters have the disadvantage of lowering power efficiency when the ratio of output voltage to input voltage is high. Accordingly, a 3-level DC-DC converter was proposed. A 3-level DC-DC converter may be composed of a phase including a plurality of power switches, flying capacitors, and inductors. However, for the voltage conversion operation, as the plurality of power switches are driven, conduction loss and switching loss may occur. Additionally, in the process of inputting the power voltage to the phase, , output voltage abnormalities such as overshoot/undershoot and output voltage ripple problems may occur. Accordingly, a 3-level DC-DC converter structure using a plurality of the above phases was proposed to provide high-quality output voltage.

However, in the case of a multi-phase 3-level DC-DC converter, a capacitor is provided for each phase, so not only does the area of the 3-level DC-DC converter increase, but also a mismatch in the charge amount of the capacitor causes , there is a problem that a difference in the output current of the inductor occurs. This difference in the output current of the inductor causes a decrease in the power efficiency of the DC-DC converter.

The present invention provides a 3-level DC-DC converter that can improve area and power efficiency.

A 3-level DC-DC converter according to an embodiment of the present invention includes a first converting unit including a capacitor and a plurality of switches for charging and discharging the capacitor, and is connected to an output node of the first converting unit, A second converting unit including an inductor and a switching unit that selectively supplies or discharges the output voltage of the first converting unit to the inductor, and an output unit connected to the second converting unit, wherein the first converting unit consists of a single unit. And, the second converting unit is composed of a plurality of units.

In addition, a 3-level DC-DC converter according to another embodiment of the present invention includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor sequentially connected in series between the input power and the ground power. , and a first converting unit including a flying capacitor connected in parallel with the first NMOS transistor and the second PMOS transistor; a plurality of second converting units connected in parallel to the output node of the first converting unit and including an inductor and a switching unit that selectively supplies the output voltage of the first converting unit to the inductor; an output unit connected to the second converting unit to provide a load; and a control circuit block that controls the transistors of the first converting unit and the switching unit of the second converting unit, and the plurality of second converting units are sequentially driven with a phase difference.

According to this embodiment, the first converting unit including a flying capacitor occupying a relatively large area is implemented as a single phase, and the second converting unit including an inductor is implemented as a plurality of phases. Accordingly, the occupied area of the converter can be reduced, conduction loss can be reduced, and power efficiency can be improved.

Additionally, the voltage swing level can be reduced by alternately connecting PMOS transistors and NMOS transistors for charging and discharging the flying capacitor in series between the input power and the ground power.

1 is a circuit diagram showing a 3-level DC-DC converter according to an embodiment of the present invention.
Figure 2 is a block diagram showing the control circuit block of a 3-level DC-DC converter according to an embodiment of the present invention.
Figure 3 is a diagram showing output waveforms of modulation signals according to an embodiment of the present invention.
Figure 4 is a circuit diagram for explaining the operation of the first converting unit according to an embodiment of the present invention.
Figure 5 is a circuit diagram showing a general 3-level DC-DC converter structure.
Figures 6a to 6c are timing diagrams of output voltages for each phase of a 3-level DC-DC converter.
Figure 7 is a table showing the effective resistance in charging mode and discharging mode according to the duty ratio for each phase.
Figure 8 is a table showing average resistance according to each duty ratio according to an embodiment of the present invention.

The advantages and features of the present invention and methods for achieving them will become clear by referring to the embodiments described in detail below along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and will be implemented in various different forms. The present embodiments only serve to ensure that the disclosure of the present invention is complete and that common knowledge in the technical field to which the present invention pertains is not limited. It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. The sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of explanation. Like reference numerals refer to like elements throughout the specification.

1 is a circuit diagram showing a DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 1, the DC-DC converter 100 may include a first converting unit 110, a second converting unit 120, and an output unit 130.

The first converting unit 110 may include switches connected in series between the input power source Vin and the ground power source. For example, the first converting unit 110 includes a first PMOS transistor (M1), a first NMOS transistor (M2), a second PMOS transistor (M3) sequentially connected between the input power supply (Vin) and the ground power supply. It may include a second NMOS transistor (M4). The first PMOS transistor (M1), the first NMOS transistor (M2), the second PMOS transistor (M3), and the second NMOS transistor (M4) are controlled by the first to fourth control signals (Gsc1, Gsc2, Gsc3, and Gsc4). Turns on selectively. The first to fourth control signals (Gsc1, Gsc2, Gsc3, Gsc4) may be provided from control circuit blocks that will be described below.

The first PMOS transistor (M1), the first NMOS transistor (M2), the second PMOS transistor (M3), and the second NMOS transistor (M4) may have the same mobility characteristics. ) and the second PMOS transistor M3 may each be formed to have an area of 4N, and the first NMOS transistor M2 and the second NMOS transistor M4 may each be formed to have an area of 2N. At this time, the first and second PMOS transistors (M1, M3) with an area of 4N and the first and second NMOS transistors (M2, M4) with an area of 2N may each have a resistance corresponding to R. At this time, R and N may be positive rational numbers.

Additionally, the first converting unit 110 may include a flying capacitor (Cfly). The flying capacitor (Cfly) can be charged by a voltage equal to 0.5 times the input voltage (Vin). Here, the flying capacitor Cfly may be connected between the connection node of the first PMOS transistor M1 and the first NMOS transistor M2 and the connection node of the second PMOS transistor M3 and the second NMOS transistor M4. . In this embodiment, the first converting unit 110 is provided as a single unit. Therefore, only one flying capacitor (Cfly) is provided in the 3-level DC-DC converter 100, thereby reducing the area of the 3-level DC-DC converter 100.

As described above, the first converting unit 110 of this embodiment includes a first PMOS transistor (M1), a first NMOS transistor (M2), and a second PMOS transistor (M3) between the input power supply (Vin) and the ground power supply. and the second NMOS transistor M4 are alternately connected in series. Accordingly, the output node of the first converting unit 110 may correspond to the connection node of the first NMOS transistor M2 and the second PMOS transistor M3.

The switches of the first converting unit 110 have PMOS transistors and NMOS transistors alternately connected between the input power Vin and the ground power supply. Accordingly, the control signals (Gsc1, Gsc2) for driving the first PMOS transistor and the first NMOS transistor (M1, M2) swing in the range Vin ~ Vin/2, and the second PMOS transistor and the second NMOS transistor ( The control signals (Gsc3, Gsc4) for driving M3, M4) can swing from Vin/2 to Vss. In addition, the first converting unit 110 selectively converts the first and second PMOS transistors M1 and M3 so that the flying capacitor Cfly preserves a certain charge and provides a constant output voltage Vsc. or the first and second NMOS transistors (M2, M4) can be selectively driven. Therefore, because the first PMOS transistor (M1), first NMOS transistor (M2), second PMOS transistor (M3), and second NMOS transistor (M4) constituting the first converting unit 110 do not operate simultaneously. , no shoot through occurs from the input voltage (Vin) to the ground voltage (Vss). As will be described again below, the first converting unit 110 is responsible for selective operation of the first PMOS transistor (M1), the first NMOS transistor (M2), the second PMOS transistor (M3), and the second NMOS transistor (M4). As a result, the voltage (Vin-Vf) or the capacitor voltage (Vf) obtained by subtracting the capacitor voltage (Vf) from the input power (Vin) can be repeatedly output. At this time, because the capacitor voltage (Vf) corresponds to 0.5 times the input voltage, the first converting unit 110 can continuously output a voltage corresponding to 0.5 times the input power (Vin).

The second converting unit 120 may be connected between the output node of the first converting unit 110 and the output unit 130. The second converting unit 120 is configured to include an inductor (L) and may be composed of a plurality of inductors (L). The plurality of second converting units 120 may be operated in multiple phases (PH1, PH2, PH3, PH4) to reduce conduction loss and switching loss. The second converting unit 120 driven in multiple phases may be connected in parallel to the output node of the first converting unit 110. The plurality of second converting units 120 may be driven to have four phase differences, for example, 0°, 45°, 90°, and 135°. In addition, the second converting unit 120 is connected between the output node of the first converting unit 110 and the inductor (L) in order to switch and discharge the output voltage (Vsc) of the first converting unit 110, It may include a switching unit (SW). The switching unit (SW) of the second converting unit 120 may include a third PMOS transistor (Mp1) and a third NMOS transistor (Mn1). The third PMOS transistor Mp1 may include a drain connected to the output node of the first converting unit 110, a gate receiving the fifth control signal Gp1, and a drain connected to the third NMOS transistor Mn1. You can. The third NMOS transistor Mn1 may include a drain connected to the drain of the third PMOS transistor Mp1, a gate receiving the sixth control signal Gn1, and a source connected to a ground power source. In the drawing, Vx indicates a node to which the drain of the third PMOS transistor (Mp1), the drain of the third NMOS transistor (Mn1), and the inductor (L) are connected.

The third PMOS transistor Mp1 and the third NMOS transistor Mn1 may be turned on simultaneously or selectively by the fifth control signal Gp1 and the sixth control signal Gn1. Accordingly, the output voltage (Vsc) of the first converting unit 110 may be switched directly to the inductor (L), or the ground voltage may be transmitted to the inductor (L). The fifth and sixth control signals (Gp1, Gn1) can be generated in the control circuit block like the first to fourth control signals (Gsc1 to Gsc4).

The third PMOS transistor Mp1 of the second converting unit 120 may be formed to have an area of 2N and have a resistance corresponding to 2R, and the third NMOS transistor Mn1 may have an area of N to have a resistance corresponding to 2R. can be formed.

The output unit 130 may be a load including an output capacitor (Co), an output resistance (R), and a current source (Ic). The output capacitor (Co) and the output resistor (R) may be connected in series between the output node of the output unit 130 and the ground power source. A current source (Ic) may also be connected between the output node and the ground supply.

The voltage of the output node of the output unit 130 (Vout, hereinafter referred to as the output voltage of the DC-DC converter) can be calculated by the following equation.

<Equation 1>

Vout=Duty*Vin*0.5

Accordingly, the duty ratio of the output signal of the 3-level DC-DC converter can be obtained as D=Vout/Vin * 200.

Figure 2 is a block diagram showing the control circuit block of a 3-level DC-DC converter according to an embodiment of the present invention. Figure 3 is a diagram showing output waveforms of modulation signals according to an embodiment of the present invention. Figure 4 is a circuit diagram for explaining the operation of the first converting unit according to an embodiment of the present invention.

Referring to FIG. 2, the circuit block 200 that controls the 3-level DC-DC converter 100 includes the phase control unit 140 that controls the operation of the second converting unit 120 and the first converting unit 110. It may include a switching control unit 150 that controls the operation of the switches.

The phase control unit 140 may include a signal generator 142 and a driver 144.

The signal generator 142 may be a time-based proportional integral derivative (PID) device. The PID may include a regulator that varies the output voltage (Vout) according to changes in the load current (Iload) of the output unit. Additionally, the signal generator 142 may receive an output voltage (Vout) and a reference voltage (Vref) and generate an output clock (CKout) and a reference clock (CKref). The signal generator 142 may divide the reference clock (CKref) based on the output clock (CKout) to generate a plurality of modulation signals (PWMs).

Referring to FIG. 3, the signal generator 142 generates 4 divided modulation signals (PWM 0°, PWM 45°, PWM 90°, PWM 135°) that are synchronized with the output clock (CKout) and the reference clock (CKref). can be created. The modulation signals (PWM 0°, PWM 45, PWM 90°, and PWM 135°) each have a phase difference of 45° and can be enabled sequentially. For example, it may be the gate signal (Gp1) of the third PMOS transistor (Mp1) input to each phase (PH1 to PH4). In addition, the signal generator 142 inverts the gate signal (Gp1) of the third PMOS transistor (Mp1) to generate the gate signal (Gn1) of the third NMOS transistor (Mn1) of each phase (PH1 to PH4). You can.

The driver 144 buffers the modulation signals (PWMs) output from the signal generator 142 to a level suitable for driving the MOS transistor. The driver 144 may provide the buffered modulation signals to each phase (PH1 to PH4), that is, to the plurality of second converting units 120. Accordingly, the switches of the plurality of second converting units 120 may be sequentially turned on by the buffered modulation signals (PWMs).

The switching control unit 150 may include a dividing unit 152, a preliminary control signal generating unit 154, and a control signal generating unit 156.

The dividing circuit unit 152 may receive the output clock CKout provided from the signal generating unit 142 and divide the output clock CKout by 4 to generate the control clock Fsc (see FIG. 3).

The selection circuit unit 154 may receive the control clock (Fsc), modulate the control clock (Fsc), and generate a preliminary control signal (pre_S). The preliminary control signal pre_S may include, for example, signals for driving a PMOS transistor and signals for driving an NMOS transistor.

The control signal generator 156 receives the preliminary control signal (pre_S) and level shifts the preliminary control signal (pre_S) to the range Vin~Vin/2 and Vin/2~Vss. The control signal generator 156 may output the level-shifted preliminary control signal (pre_S) and its inverted signal as the first to fourth control signals (Gsc1, Gsc2, Gsc3, and Gsc4).

For example, as shown in FIGS. 3 and 4, when the control clock (Fsc) is in the high section (①), the preliminary control signal generator 154 and the control signal generator 156 generate the first and second signals. 2 PMOS transistors (M1, M3) are turned on, and the first to fourth control signals (Gsc1, Gsc2, Gsc3, Gsc4) can be generated so that the first and second NMOS transistors (M2, M4) are turned off. .

As described above, when the first and second PMOS transistors (M1, M3) are turned on and the first and second NMOS transistors (M2, M4) are turned off, the first converting unit (110) outputs the capacitor voltage (Vf) from the input voltage (Vin) and the limiting voltage (Vin-Vf) as the output voltage (Vsc). Since the capacitor voltage (Vf) is 0.5 times the input voltage (Vin), the first converting unit 110 can substantially output the capacitor voltage (Vf).

Meanwhile, when the control clock (Fsc) is in the low section (②), the preliminary control signal generator 154 and the control signal generator 156 turn off the first and second PMOS transistors (M1 and M3), The first to fourth control signals (Gsc1, Gsc2, Gsc3, Gsc4) can be generated to turn on the first and second NMOS transistors (M2, M4). Accordingly, the first converting unit 1110 converts the capacitor voltage Vf because the first and second PMOS transistors M1 and M3 are turned off and the first and second NMOS transistors M2 and M4 are turned on. is output as the output voltage (Vsc).

As a result, the first converting unit 110 converts the capacitor voltage (Vf) of the flying capacitor (Cfly), that is, 0.5 times the input power (Vin), in both the high section (①) and low section (②) of the control clock (Fsc). By outputting a voltage corresponding to , auto balancing can be maintained.

Figure 5 is a circuit diagram showing a general 3-level DC-DC converter structure.

Referring to FIG. 5, a typical 3-level DC-DC converter 10 includes a plurality of converting units (M11, M12, M13, M14), a flying capacitor (Cfly), and an inductor (L). 20) and an output unit 30 connected to a plurality of converting units 20. The plurality of converting units 20 are driven with different phase differences and may be referred to as a plurality of phases.

The power switch is connected to the first PMOS transistor (M11), the second PMOS transistor (M12), the first NMOS transistor (M13), and the second NMOS transistor (M14) sequentially connected between the input power supply (Vin) and the ground power supply. It may apply. The first and second PMOS transistors M11 and M12 may be formed to have a resistance of 2R and an area of 2N. The first and second NMOS transistors M13 and M14 may be formed to have an area of N and have a resistance corresponding to 2R.

Table 1 below shows the effective resistance in charging mode and discharging mode of the 3-level DC-DC converter 100 according to an embodiment of the present invention (FIG. 1), and the typical 3-level DC-DC shown in FIG. 5. This is a table comparing the effective resistance of the converter 10 in charging mode and discharging mode.

Effective resistance when charging Cfly1 in Figure 5 Effective resistance when discharging Cfly1 in Figure 5 Effective resistance when charging Cfly in Figure 1 Effective resistance during Cfly discharge in Figure 1 Single phase selection 4R 4R 4R 2R 2 phase selection 2R 2R 3R R 3 phase selection 4R/3 4R/3 8R/3 2R/3

Referring to Table 1, in order for the flying capacitor Cfly1 to be charged while one of the converting units 20 of FIG. 5 is driven, the first and second PMOS transistors M11 of the DC-DC converter 10 of FIG. 5 ,M12) must be turned on. Accordingly, the 3-level DC-DC converter 10 of FIG. 5 has an effective resistance of 4R (2R+2R).

Meanwhile, one of the second converting units 120 of the 3-level DC-DC converter 100 of FIG. 1 according to an embodiment of the present invention is selected and driven, and the flying capacitor (Cfly) of the first converting unit 110 To be charged, all of the first and second PMOS transistors M1 and M3 of the first converting unit 110 and the selected third PMOS transistor Mp1 of the second converting unit 10 must be turned on. Accordingly, the DC-DC converter 100 according to this embodiment has an effective resistance of 4R (R+R+2R).

In addition, if one of the converting units 20 of the 3-level DC-DC converter 10 of FIG. 5 is selected and driven and the flying capacitor (Cfly1) is discharged, the 3-level DC-DC converter 10 of FIG. 5 The first and second NMOS transistors (M13, M14) must be turned on. At this time, the 3-level DC-DC converter 10 of FIG. 5 has an effective resistance of 4R (2R+2R).

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 in this embodiment, one of the second converting units 120 is selected and driven, and the flying capacitor of the first converting unit 110 is discharged, in other words, When the 3-level DC-DC converter 100 must output a voltage of the ground power level, regardless of the driving of the first converting unit 110, the third NMOS transistor (Mn1) of the selected second converting unit 120 ) just needs to be turned on. Accordingly, the 3-level DC-DC converter 100 of FIG. 1 has an effective resistance of substantially 2R (effective resistance of the third NMOS transistor).

In addition, in the 3-level DC-DC converter 10 of FIG. 5, if the two converting units 20 are selected with a phase difference and the flying capacitor Cfly1 is charged, the first and Because the second PMOS transistors (M11 and M12) are driven simultaneously, they have an effective resistance of 2R (4R/2, parallel resistance value).

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 according to this embodiment, two second converting units 120 connected in parallel are selected simultaneously with a phase difference, and the flying of the first converting unit 110 When the capacitor Cfly needs to be charged, the first and second PMOS transistors M1 and M3 of the first converting unit 110 are driven, and the third PMOS transistors of the two second converting units 120 ( Mp1) runs simultaneously. Accordingly, the 3-level DC-DC converter 100 of this embodiment has an effective resistance (R+R+(2R/2)) corresponding to 3R.

In the 3-level DC-DC converter 10 of FIG. 5, the two converting units 20 are selected with a phase difference, and if the flying capacitor Cfly1 is to be discharged, the first of the two converting units 20 connected in parallel and the second NMOS transistors (M13 and M14) are driven, respectively, so they have an effective resistance (4R/2) of 2R.

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 according to this embodiment, two second converting units 120 connected in parallel are selected simultaneously with a phase difference, and the flying of the first converting unit 110 For the capacitor Cfly to be discharged, the third NMOS transistor Mn1 of the two selected second converting units 120 are respectively driven, so that the DC-DC converter 100 has an effective resistance of R (2R/2). .

When three of the converting units 20 of the 3-level DC-DC converter 10 of FIG. 5 are selected with a phase difference and the flying capacitor (Cfly1) needs to be charged, the three converting units 20 in parallel Because the first and second PMOS transistors M11 and M12 are driven, respectively, the DC-DC converter 10 has an effective resistance of 4R/3.

Meanwhile, in the 3-level DC-DC converter 100 of FIG. 1 according to this embodiment, three second converting units 120 connected in parallel are selected simultaneously, and the flying capacitor (Cfly) of the first converting unit 110 is selected at the same time. ), the first and second PMOS transistors (M1, M3) of the first converting unit 110 and the third PMOS transistor (Mp1) of the three second converting units 120 connected in parallel are simultaneously charged. It turns on. Accordingly, the 3-level DC-DC converter 100 of FIG. 1 has an effective resistance (R+R+(2R/3)) corresponding to 8R/3.

When three of the converting units 20 of the DC-DC converter 10 of FIG. 5 are selected simultaneously with a phase difference and the flying capacitor (Cfly1) needs to be discharged, the DC-DC converter 10 of FIG. 5 is operated in parallel. Since the first and second NMOS transistors M13 and M14 of the three connected converting units 20 are driven simultaneously, they have an effective resistance of 4R/3.

Meanwhile, in the DC-DC converter 100 of FIG. 1 according to this embodiment, three second converting units 120 connected in parallel are selected simultaneously, and the flying capacitor Cfly of the first converting unit 110 is discharged. When required, the third NMOS transistors Mn1 of the three second converting units 120 connected in parallel are driven simultaneously. Accordingly, the DC-DC converter 100 of FIG. 1 according to this embodiment has an effective resistance of 2R/3.

Figures 6a to 6c are timing diagrams of output voltages for each phase of the DC-DC converter. Figure 7 is a table showing the effective resistance in charging mode and discharging mode according to the duty ratio for each phase.

Figure 6a shows that when the duty ratio of the output voltage is 25% or less, the first second converting unit (PH1: 0°, hereinafter, first phase), the second second converting unit (PH2: 45°, hereinafter, second phase), This is a timing diagram showing the output voltage (Vout) of the third second converting unit (PH3: 90°, hereinafter, third phase) and the fourth second converting unit (PH4: 135°, hereinafter, fourth phase).

Referring to Figure 6a, when the dubby ratio (D) of the output voltage (Vout) is 25% or less, the first phase (PH1) is enabled at a high level, so it corresponds to the charging mode (C) of the flying capacitor (Cfly) , Since the remaining second to fourth phases (PH2 to PH4) are disabled at low level, they correspond to the discharge mode (DI) of the flying capacitor (Cfly).

Referring to FIG. 7, when the duty ratio (D) of the output voltage (Vout) is 25% or less, the charging mode of the 3-level DC-DC converter 10 of FIG. 5 and the DC-DC converter 100 of FIG. 1 The effective resistances in (C) are each selected as a single phase, as shown in Table 1 above, and may correspond to 4R, which is the effective resistance when the flying capacitor Cfly is charged.

In addition, when the duty ratio (D) of the output voltage (Vout) is 25% or less, the discharge mode ( Each of the effective resistances of DI) has an effective resistance of 4R/3 and 2R/3, which is the effective resistance when three phases are simultaneously selected and the flying capacitor (Cfly) is discharged (see Table 1).

Figure 6b shows that when the duty ratio of the output voltage is more than 25% and less than 50%, the first phase (PH1: 0°), the second phase (PH2: 45°), the third phase (90°: PH3), and the fourth phase ( This is a timing diagram showing the output voltage (Vout) of PH4:135°).

Referring to Figure 6b, when the output voltage (Vout) has a duty ratio (D) of more than 25% and less than 50%, the first phase (PH1) and the second phase (PH2) are enabled high, so charging It corresponds to mode (C), and since the third phase (PH3) and fourth phase (PH4) are disabled to low, it corresponds to discharge mode (DI).

Accordingly, referring to FIG. 7, when the duty ratio (D) of the output voltage (Vout) is greater than 25% and less than 50%, the 3-level DC-DC converter 10 of FIG. 5 and the DC-DC converter of FIG. 1 The effective resistance of the charging mode (C) of (100) corresponds to 2R and 3R, which are the effective resistance values of (C) when the flying capacitor (Cfly) is charged while the two phases in Table 1 are selected simultaneously.

When the duty ratio (D) of the output voltage (Vout) is greater than 25% and less than 50%, the discharge mode of the 3-level DC-DC converter 10 in FIG. 5 and the 3-level DC-DC converter 100 in FIG. 1 The effective resistance of (DI) corresponds to 2R and R, which are the effective resistance values when the flying capacitor is discharged while the two phases in Table 1 are selected simultaneously.

Figure 6c shows the first phase (PH1: 0°), the second phase (PH2: 45°), the third phase (PH3: 90°), and the third phase (PH3: 90°) when the duty ratio of the output voltage (Vout) is more than 50% and less than 75%. This is a timing diagram showing the output voltage of 4 phases (PH4:135°).

Referring to FIG. 6C, when the output voltage (Vout) has a duty ratio (D) of more than 50% and less than 75%, the first phase (PH1) to the third phase (PH3) are enabled high, so charging It corresponds to mode (C), and since the fourth phase (PH4) is disabled to low, it corresponds to discharge mode (DI).

Referring to FIG. 7, when the duty ratio (D) of the output voltage (Vout) is greater than 50% and less than 75%, the 3-level DC-DC converter 10 of FIG. 5 and the 3-level DC-DC converter of FIG. 1 The effective resistance of the charging mode (C) of (100) corresponds to 4R/3 and 8R/3, which are the effective resistances when the flying capacitor (Cfly) is charged while three phases are selected simultaneously, as shown in Table 1. .

On the other hand, when the duty ratio (D) of the output voltage (Vout) is greater than 50% and less than 75%, the 3-level DC-DC converter 10 in FIG. 5 and the 3-level DC- in FIG. 1 The effective resistances in the discharge mode (DI) of the DC converter 100 have effective resistances of 4R and 2R, which are the effective resistance values when the flying capacitor (Cfly) is discharged while a single phase is driven (see Table 1).

Figure 8 is a table showing average resistance according to each duty ratio according to an embodiment of the present invention.

Referring to FIG. 8, in the case of a duty ratio of 25% or less, the average resistance of the 3-level DC-DC converter 10 of FIG. 5 is 4R, which is the effective resistance value in charging mode, and 4R/3, which is the effective resistance value in discharging mode. Corresponds to the parallel resistance value (4R∥4R/3), and the 3-level DC-DC converter 100 according to this embodiment has 4R, which is the effective resistance value in charging mode, and 2R/3, which is the effective resistance value in discharging mode. It has a parallel resistance value (4R∥4R/3). Accordingly, compared to the general 3-level DC-DC converter 10, the average resistance of the 3-level DC-DC converter 100 of this embodiment is reduced by about 40% in the duty ratio section of 25% or less. .

In the case of a duty ratio of more than 25% and less than 50%, the average resistance of the 3-level DC-DC converter 10 of FIG. 5 is the parallel resistance value of 2R, which is the effective resistance value in charging mode, and 2R, which is the effective resistance value in discharging mode ( Corresponds to 2R∥2R), and the 3-level DC-DC converter 100 according to this embodiment has a parallel resistance value of 3R, which is the effective resistance value in charging mode, and R, which is the effective resistance value in discharging mode (3R∥R) corresponds to Accordingly, compared to the general 3-level DC-DC converter 10, the 3-level DC-DC converter 100 of this embodiment has an average resistance of about 25% in the dubby ratio range of more than 25% and less than 50%. This is reduced.

Meanwhile, in the case of a duty ratio of more than 50% and less than 75%, the average resistance of the DC-DC converter 10 in FIG. 5 is the parallel resistance value of 4R/3, which is the effective resistance value in charging mode, and 4R, which is the effective resistance value in discharging mode. Corresponds to (4R/3∥4R), and the DC-DC converter 100 of FIG. 1 according to this embodiment has a parallel resistance value of 8R/3, which is the effective resistance value in charging mode, and 2R, which is the effective resistance value in discharging mode. Corresponds to (8R/3∥2R). Accordingly, compared to the general DC-DC converter 10, the average resistance of the DC-DC converter 100 of this embodiment can be increased by about 12% in the duty ratio range of more than 50% and less than 75%. .

At this time, the conduction loss of the 3-level DC-DC converter can be expressed as the following equation.

<Equation 2>

Conduction loss = I ₀ ² * average resistance (I ₀ is the output current)

Accordingly, when implementing the 3-level DC-DC converter 100 as in the embodiment of the present invention, the effective resistance value is reduced by more than 25% in the duty ratio section of 50% or less, so conduction loss can be reduced. .

According to this embodiment, the first converting unit including a flying capacitor occupying a relatively large area is implemented as a single phase, and the second converting unit including an inductor is implemented as a plurality of phases. Accordingly, the occupied area of the converter can be reduced, conduction loss can be reduced, and power efficiency can be improved.

Additionally, the voltage swing level can be reduced by alternately connecting PMOS transistors and NMOS transistors for charging and discharging the flying capacitor in series between the input power and the ground power.

Although the present invention has been described in detail with preferred embodiments above, the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. do.

100: 3-level DC-DC converter 110: first converting unit
120: second converting unit 130: output unit

Claims (18)

A capacitor and a first converting unit including a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor sequentially connected between an input power source and a ground power source to selectively charge and discharge the capacitor;
a second converting unit connected to the output node of the first converting unit and including an inductor and a switching unit that selectively supplies or discharges the output voltage of the first converting unit to the inductor; and
It includes an output unit connected to the second converting unit,
The first converting unit is composed of a single unit,
A 3-level DC-DC converter consisting of a plurality of second converting units. According to claim 1,
The capacitor is connected between a connection node of the first PMOS transistor and the first NMOS transistor and a connection node of the second PMOS transistor and the second NMOS transistor,
The first and second PMOS transistors are turned on by a voltage that swings from a voltage corresponding to 0.5 times the input voltage provided from the input power source to the voltage level of the capacitor,
A three-level DC-DC converter wherein the first and second NMOS transistors are turned on by a voltage swinging from the voltage level of the capacitor to the ground power level. According to claim 1,
The first and second PMOS transistors are formed with an area of 4N to have a resistance corresponding to R (where R and N are positive rational numbers).
The first and second NMOS transistors are formed to have an area of 2N and have a resistance corresponding to R, a 3-level DC-DC converter. According to claim 1,
A 3-level DC-DC converter in which the first and second PMOS transistors and the first and second NMOS transistors are selectively turned on so that the first converting unit continuously outputs a constant voltage. According to claim 2,
A 3-level DC-DC converter where the voltage level of the capacitor is a voltage corresponding to 0.5 times the input voltage. According to claim 4,
A 3-level DC-DC converter further comprising a switching control unit that generates first to fourth control signals for driving the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor. . According to claim 6,
The switching control unit,
a dividing unit that generates a control clock by dividing the output clock generated based on the output voltage of the output unit;
a selection circuit unit that modulates the control clock to generate a preliminary control signal for selecting the first and second PMOS transistors and a preliminary control signal for selecting the first and second NMOS transistors; and
By adjusting the operation levels of the preliminary control signals, the first control signal for driving the first PMOS transistor, the second control signal for driving the second PMOS transistor, and the third control signal for driving the first NMOS transistor and a control signal generator that generates a fourth control signal for driving the second NMOS transistor. According to claim 1,
The switching unit of the second converting unit,
A third PMOS transistor connected to the output node of the first converting unit; and
A 3-level DC-DC converter including a third NMOS transistor connected between the connection node of the third PMOS transistor and the inductor and the ground power supply. According to claim 8,
A 3-level DC-DC converter in which the switching units of the plurality of second converting units are each sequentially driven with a predetermined phase difference. According to clause 9,
A 3-level DC-DC converter in which each switching unit of the plurality of second converting units is sequentially driven with a phase difference of 45°. According to claim 8,
The third PMOS transistor is formed with an area of 2N to have a resistance corresponding to 2R,
The third NMOS transistor is a 3-level DC-DC converter formed with an area of N to have a resistance corresponding to 2R. According to claim 8,
A 3-level DC-DC converter further comprising a phase control unit generating fifth and sixth control signals for driving the third PMOS transistor and the third NMOS transistor. According to claim 12,
Generates a signal that receives the output voltage and reference voltage of the output unit, generates an output clock and a reference clock, and divides the output clock and the reference clock to generate a plurality of modulation signals that are sequentially enabled with a phase difference. wealth; and
A 3-level DC-DC converter including a driving unit that buffers the modulation signals and provides the buffered signals to the plurality of second converting units. According to claim 1,
The output unit includes a capacitor connected to the output node of the second converting unit, a resistor connected between the capacitor of the output unit and the ground power supply, and a current source connected between the output node of the second converting unit and the ground power supply. 3-level DC-DC converter. A first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor sequentially connected in series between the input power and the ground power, and connected in parallel with the first NMOS transistor and the second PMOS transistor A first converting unit including a flying capacitor;
a plurality of second converting units connected in parallel to the output node of the first converting unit and including an inductor and a switching unit that selectively supplies the output voltage of the first converting unit to the inductor;
an output unit connected to the second converting unit to provide a load; and
It includes a control circuit block that controls the transistors of the first converting unit and the switching unit of the second converting unit,
A 3-level DC-DC converter in which the plurality of second converting units are sequentially driven with a phase difference. According to claim 15,
The switching unit of the second converting unit,
A third PMOS transistor connected to the output node of the first converting unit; and
A 3-level DC-DC converter including a third NMOS transistor connected between the connection node of the third PMOS transistor and the inductor and the ground power supply. According to claim 15,
The control circuit block is,
a switching control block that generates first to fourth control signals to selectively operate the first and second PMOS transistors or to selectively operate the first and second NMOS transistors; and
A 3-level DC-DC converter including a phase control block that generates a control signal so that the switching units of the plurality of second converting units are sequentially turned on with a phase difference. According to claim 17,
The switching control block and the phase control block are configured to generate the first to fourth control signals and the control signal based on the output voltage of the output unit.