KR102676329B1 - Level shifter, and semiconductor device including the same - Google Patents

Abstract

A level shifter and a semiconductor device including the same are disclosed. A level shifter according to the technical idea of the present disclosure includes a first driving circuit connected between a line to which a driving voltage is applied and a first node, a second driving circuit connected between a line to which a driving voltage is applied and a second node, It includes a third driving circuit connected between the first node and the output node, and a level shifting circuit that supplies the output signal with the level of the input signal shifted to the second node.

Description

Level shifter and semiconductor device including the same {LEVEL SHIFTER, AND SEMICONDUCTOR DEVICE INCLUDING THE SAME}

The technical idea of the present disclosure relates to electronic devices, a level shifter for converting the level of a signal at high speed with low power, and a semiconductor device including the same.

A level shifter is a device that shifts the swing size of an input signal and outputs it as an output signal. These level shifters can serve as an interface between circuits that use power supply voltages of different voltage levels. Therefore, a semiconductor device or electronic device composed of circuits that use power voltages of different voltage levels requires a level shifter to shift from one power voltage level to another power voltage level or to a specific voltage level. At this time, research on level shifters that operate at low power while shifting at high speed from one power supply voltage level to another power voltage level or a specific voltage level is increasing.

Korean Patent Publication No. 10-2022-0021638 (Title of invention: High-speed level shifter, Publication date: 2022.02.22)

The technical idea of the present disclosure provides a level shifter for high-speed conversion of a signal level with low power by designing a circuit to shorten pull-up or pull-down time, and a semiconductor device including the same.

However, the problems to be solved by this disclosure are not limited to the problems mentioned above, and other problems not mentioned can be clearly understood based on the description below.

A level shifter according to the technical idea of the present disclosure includes: a first driving circuit connected between a line to which a driving voltage is applied and a first node and including a plurality of transistors that transmit the driving voltage to the first node; a second driving circuit connected between a line to which a driving voltage is applied and a second node and including a plurality of transistors that transmit the driving voltage to the second node; It is connected to the second node and outputs an inverted output signal in which the first output signal is inverted to the first driving circuit, outputs a second output signal in which the inverted output signal is inverted to the second driving circuit, and outputs a second output signal corresponding to the first output signal. a third driving circuit including a plurality of inverters that output three output signals; and receiving an input signal, outputting a first inverted input signal in which the input signal is inverted and a second inverted input signal in which the first inverted input signal is inverted to the first driving circuit and the second driving circuit, and the level of the input signal is and a level shifting circuit configured to output the shifted signal as a first output signal to the second node.

Alternatively, the first driving circuit may include a first transistor connected between the first node and the third node and including a gate electrode through which a first inverted input signal is input; A second transistor connected between the line to which the driving voltage is applied and the third node, and including a gate electrode through which the inverted output signal is input, and connected between the first node and the third node, and where the second inverted input signal is input. It may include a third transistor including a gate electrode.

Alternatively, the first transistor may be a transistor of a different type from the type of the second transistor and the third transistor, and the second transistor and the third transistor may be of the same type.

Alternatively, the second driving circuit is connected between the second node and the fourth node, and includes a first transistor including a gate electrode through which the second inverted input signal is input, the second node and the fourth node. A second transistor connected between and including a gate electrode through which the first inverted input signal is input, and a gate electrode connected between the line to which the driving voltage is applied and the fourth node and through which the second output signal is input. It may include a third transistor including.

Alternatively, the first transistor may be a transistor of a different type from the type of the second transistor and the third transistor, and the second transistor and the third transistor may be of the same type.

Alternatively, the third driving circuit may include a first inverter that receives the first output signal and outputs the inverted output signal; And it may include a second inverter connected in series with the first inverter, receiving the inverted output signal and outputting the second output signal.

Alternatively, the third driving circuit may include a third inverter connected in series with the second inverter, receiving the second output signal and outputting an inverted signal of the third output signal; And it may further include a fourth inverter connected in series with the third inverter, receiving the signal inverted with the third output signal and outputting the third output signal.

Alternatively, the level shifting circuit is connected between a line to which a first voltage is applied and the first node, and includes a first transistor including a gate electrode to which the second inverted input signal is input, and to which the first voltage is applied. A second transistor connected between the line and the second node and including a gate electrode to which the first inverted input signal is input, a line to which a second voltage having a voltage level higher than the voltage level of the first voltage is applied and a third transistor connected between the first node and including a gate electrode connected to the second node, a gate connected between the line to which the second voltage is applied and the second node, and connected to the first node. A fourth transistor including an electrode, a first inverter that receives the input signal and outputs the first inverted input signal, and a second inverter that receives the first inverted input signal and outputs the second inverted input signal. may include. The driving voltage may be one of the second voltage and a third voltage having a voltage level higher than the voltage level of the first voltage and lower than the voltage level of the second voltage.

In addition, the level shifter according to the technical idea of the present disclosure includes a first inverted input signal in which the input signal is inverted, a second inverted input signal in which the first inverted input signal is inverted, and an input signal based on the input signal and the driving voltage. a level shifting circuit configured to respectively output first output signals of which the level of is shifted; and transmitting a driving voltage to the level shifting circuit based on the first inverted input signal and the second inverted input signal, and generating a second output signal, an inverted output signal of the second output signal, and a first output based on the first output signal. and a shifting time reduction circuit configured to generate third output signals respectively corresponding to the signals.

Alternatively, in the first period during which the level shifter operates, the level of the input signal, the level of the second inverted input signal, the level of the first output signal, the level of the second output signal, and the third The level of the output signal is a first level, and in the first period, the level of the inverted output signal is a second level higher than the first level, and in the first period, the level of the first inverted input signal is may be a third level that is lower than the second level and higher than the first level.

Alternatively, in a second period following the first period, the level of the first inverted input signal, the level of the second output signal, and the level of the third output signal are the first level and the level of the third output signal. In period 2, the level of the inverted output signal is the second level, and in the second period, the level of the input signal and the level of the second inverted input signal are the third level, and in the second period , the level of the first output signal increases from the first level to the reference level, and the reference level is lower than the second level.

Alternatively, in a third period after the second period, the level of the first inverted input signal and the level of the inverted output signal are the first level, and in the third period, the level of the second output signal is the first level. The level and the level of the third output signal are the second level, and in the third period, the level of the input signal and the level of the second inverted input signal are the third level, and in the third period , the level of the first output signal increases from the reference level to the second level.

Alternatively, in a fourth period following the third period, the level of the first inverted input signal is the first level, and in the fourth period, the level of the first output signal is the level of the second output signal. The level and the level of the third output signal are the second level, and in the fourth period, the level of the input signal and the level of the second inverted input signal are the third level.

Alternatively, in the first period in which the level shifter operates, the level of the first inverted input signal is the first level, and in the first period, the level of the first output signal and the level of the second output signal , and the level of the third output signal is a second level higher than the first level, and in the first period, the level of the input signal and the level of the second inverted input signal are lower than the second level. It is characterized in that it is a third level higher than the first level.

Alternatively, in a second period after the first period, the level of the input signal, the level of the second inverted input signal, and the level of the inverted output signal are the first level, and in the second period , the level of the second output signal and the level of the third output signal are the second level, and in the second period, the level of the first inverted input signal is the third level, and in the second period , the level of the first output signal decreases from the second level to the reference level, and the reference level is higher than the first level.

Alternatively, in a third period following the second period, the level of the input signal, the level of the second inverted input signal, the level of the second output signal, and the level of the third output signal are: 1 level, and in the third period, the level of the inverted output signal is the second level, and in the third period, the level of the first inverted input signal is the third level, and in the third period, The level of the first output signal is characterized in that it decreases from the reference level to the first level.

Alternatively, in a fourth period following the third period, the level of the input signal, the level of the second inverted input signal, the level of the first output signal, the level of the second output signal, and the third The level of the output signal is the first level, in the fourth period, the level of the inverted output signal is the second level, and in the fourth period, the level of the first inverted input signal is the third level. It is characterized by being.

Additionally, a semiconductor device according to the technical idea of the present disclosure includes a first integrated circuit configured to transmit a first signal; a level shifter configured to receive a first signal and output a second signal in which the level of the first signal is shifted; and a second integrated circuit configured to receive a second signal. The level shifter includes, based on the first signal and the driving voltage, a first inverted input signal in which the first signal is inverted, a second inverted input signal in which the first inverted input signal is inverted, and a second inverted input signal in which the level of the first signal is shifted. 1 level shifting circuit configured to output each output signal; and transmitting a driving voltage to the level shifting circuit based on the first inverted input signal and the second inverted input signal, and generating a second output signal, an inverted output signal of the second output signal, and a first output based on the first output signal. and a shifting time reduction circuit configured to generate second signals corresponding to each signal.

Alternatively, the shifting time shortening circuit is configured to transfer the driving voltage to the level shifting circuit based on the inverted output signal of the first inverted input signal, the second inverted input signal, and the second output signal. 1 driving circuit, a second driving circuit configured to transfer the driving voltage to the level shifting circuit based on the first inverting input signal, the second inverting input signal, and the second output signal, and the first output signal Based on , the second output signal, the inverted output signal, and a third driving circuit configured to output the second signal, respectively.

Alternatively, the first driving circuit may include a first transistor including a gate electrode through which the second inversion input signal is input, a second transistor including a gate electrode through which the first inversion input signal is input, and the inversion output. A third transistor including a gate electrode through which a signal is input, and the second driving circuit includes a fourth transistor including a gate electrode through which the first inverted input signal is input, and a fourth transistor through which the second inverted input signal is input. A fifth transistor including a gate electrode, and a sixth transistor including a gate electrode through which the second output signal is input, wherein the third driving circuit receives the first output signal and generates the inverted output signal. A first inverter for outputting, a second inverter for receiving the inverted output signal and outputting the second output signal, a third inverter for receiving the second output signal and outputting an inverted signal of the second output signal, and The second output signal may include a fourth inverter that receives the inverted signal and outputs the second signal.

According to the technical idea of the present disclosure, by designing a circuit to shorten the pull-up time or pull-down time, the operation speed and performance of the level shifter and the semiconductor device including the same can be improved.

In addition, according to the technical idea of the present disclosure, by designing a circuit that shortens the pull-up or pull-down time, it is possible to implement a level shifter suitable for a high-speed interface and a semiconductor device including the same.

Additionally, according to the technical idea of the present disclosure, by designing a circuit to shorten the pull-up or pull-down time, there is an effect of reducing power consumed in the level shifter and the semiconductor device including the same.

The effects that can be obtained from the embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned can be explained to those skilled in the art from the following description. Can be clearly derived and understood. That is, unintended effects resulting from implementing the embodiments of the present disclosure may also be derived by a person skilled in the art from the embodiments of the present disclosure.

1 is a schematic block diagram of a level shifter according to an embodiment of the present disclosure.
Figure 2 is a circuit diagram of a level shifter according to an embodiment of the present disclosure.
Figure 3 is a timing diagram of a pull-up operation of a level shifter according to an embodiment of the present disclosure.
FIG. 4 is a circuit diagram of a level shifter operating in the first period shown in FIG. 3.
FIG. 5 is a circuit diagram of a level shifter operating in the second period shown in FIG. 3.
FIG. 6 is a circuit diagram of a level shifter operating in the third period shown in FIG. 3.
FIG. 7 is a circuit diagram of a level shifter operating in the fourth period shown in FIG. 3.
Figure 8 is a timing diagram of a pull-down operation of a level shifter according to an embodiment of the present disclosure.
FIG. 9 is a circuit diagram of a level shifter operating in the first period shown in FIG. 8.
FIG. 10 is a circuit diagram of a level shifter operating in the second period shown in FIG. 8.
FIG. 11 is a circuit diagram of a level shifter operating in the third period shown in FIG. 8.
FIG. 12 is a circuit diagram of a level shifter operating in the fourth period shown in FIG. 8.
13 is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

Below, with reference to the attached drawings, embodiments of the present disclosure are described in detail so that those skilled in the art (hereinafter referred to as skilled in the art) can easily practice the present disclosure. The embodiments presented in this disclosure are provided to enable any person skilled in the art to use or practice the subject matter of this disclosure. Accordingly, various modifications to the embodiments of the present disclosure will be apparent to those skilled in the art. That is, the present disclosure can be implemented in various different forms and is not limited to the following embodiments.

The same or similar reference numerals refer to the same or similar elements throughout the specification of this disclosure. Additionally, in order to clearly describe the present disclosure, reference numerals of parts in the drawings that are not related to the description of the present disclosure may be omitted.

As used in this disclosure, the term “or” is intended to mean an inclusive “or” and not an exclusive “or.” That is, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” should be understood to mean one of natural implicit substitutions. For example, unless otherwise specified in the present disclosure or the meaning is not clear from the context, “X uses A or B” means that It can be interpreted as one of the cases where all B is used.

The term “and/or” as used in this disclosure should be understood to refer to and include all possible combinations of one or more of the listed related concepts.

The terms “comprise” and/or “comprising” as used in this disclosure should be understood to mean that certain features and/or elements are present. However, the terms "comprise" and/or "including" should be understood as not excluding the presence or addition of one or more other features, other components, and/or combinations thereof.

Unless otherwise specified in this disclosure or the context is clear to indicate a singular form, the singular should generally be construed to include “one or more.”

The term “Nth (N is a natural number)” used in the present disclosure can be understood as an expression used to distinguish the components of the present disclosure according to a predetermined standard such as a functional perspective, a structural perspective, or explanatory convenience. there is. For example, in the present disclosure, components performing different functional roles may be distinguished as first components or second components. However, components that are substantially the same within the technical spirit of the present disclosure but must be distinguished for convenience of explanation may also be distinguished as first components or second components.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the attached drawings.

Figure 1 is a schematic block diagram of a level shifter 100 according to an embodiment of the present disclosure.

Referring to FIG. 1, the level shifter 100 can shift the level of a signal between circuits with different signal levels. In some embodiments, the level shifter 100 may be a level shifter to provide a high speed interface. In this case, the level shifter 100 may be equipped with high-speed driving capability to transmit data in Gbps units.

The level shifter 100 includes a level shifting circuit (110), a first driving circuit (120), a second driving circuit (130), and a third driving circuit (140, third). Driving Circuit) may be included.

The level shifting circuit 110 may receive an input signal IN from the outside. The level shifting circuit 110 may receive a driving voltage (VDD) from the first driving circuit 120 or a driving voltage (VDD) from the second driving circuit 130. That is, the level shifting circuit 110 can selectively receive the driving voltage VDD from the first driving circuit 120 or the second driving circuit 130.

The level shifting circuit 110 outputs a first inverted input signal (IN_b), a second inverted input signal (IN_bb), and a first output signal (OUT1) based on the input signal (IN) and the driving voltage (VDD). You can. The first inverted input signal IN_b may be an inverted signal of the input signal IN. The second inverted input signal IN_bb may be an inverted signal of the first inverted input signal IN_b. In some embodiments, the second inverted input signal IN_bb may correspond to the input signal IN. The first output signal OUT1 may be a signal having a level transitioned from the input signal IN. Here, the state in which the level of the input signal IN transitions may be, for example, pull-up or pull-down. At this time, the pull-up may be a transition state from a relatively low signal level to a relatively high signal level. Pulldown may be a state in which there is a transition from a relatively high signal level to a relatively low signal level.

The first inverted input signal IN_b and the second inverted input signal IN_bb may be provided to the first driving circuit 120 and the second driving circuit 130. The first output signal OUT1 may be provided to the third driving circuit 140.

The first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 according to embodiments of the present disclosure may be circuits that shorten the time for a signal to be pulled up or pulled down.

The first driving circuit 120 adjusts the driving voltage VDD to the level shifting circuit 110 based on the first inverted input signal IN_b, the second inverted input signal IN_bb, and the second inverted output signal OUT2_b. ) can be passed on. The second inverted output signal OUT2_b may be a signal obtained by inverting the second output signal OUT2 by the third driving circuit 140 .

The second driving circuit 130 adjusts the driving voltage VDD to the level shifting circuit 110 based on the first inverted input signal IN_b, the second inverted input signal IN_bb, and the second output signal OUT2. It can be delivered to .

In some embodiments, the second inverted output signal OUT2_b of the second output signal OUT2 is input to the first driving circuit 120, and the second output signal OUT2 is input to the second driving circuit 130. Since it is input, the first driving circuit 120 and the second driving circuit 130 can selectively transmit the driving voltage (VDD) to the level shifting circuit 110.

In some embodiments, the driving voltage VDD may be a voltage supplied from the outside to the first driving circuit 120 and the second driving circuit 130.

In some embodiments, the first driving circuit 120 and the second driving circuit 130 may be implemented as a circuit with a latch structure.

The third driving circuit 140 may receive the first output signal OU1 from the level shifting circuit 110. The third driving circuit 140 may output a second output signal OUT2, a second inverted output signal OUT2_b, and a third output signal OUT3, respectively, based on the first output signal OU1. . In some embodiments, the second output signal OUT2 may correspond to the first output signal OU1. The third output signal OUT3 may be a signal output through the output terminal of the level shifter 100. The third output signal OUT3 may be provided as an input to an element such as a load or circuit connected to the output terminal of the level shifter 100. In some embodiments, the third output signal OUT3 may be a signal corresponding to the first output signal. In some embodiments, the level of the third output signal OUT3 may be the same as the level of the second inverted output signal OUT2_b.

In Figure 1, the first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 are shown as being implemented as separate circuits, but are not limited to this and may be implemented depending on the implementation method. The first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 may be implemented as one circuit. In some embodiments, the first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 may be included in a shifting time shortening circuit for shortening the pull-up time or pull-down time.

According to the above, the first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 are included in the level shifter 100, thereby implementing a level shifter 100 suitable for a high-speed interface. There is an advantage to being able to do this.

In addition, according to the above-mentioned, the first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 are included in the level shifter 100, thereby increasing the operating speed of the level shifter 100 and It has the advantage of improving performance.

In addition, according to the above-mentioned, the first driving circuit 120, the second driving circuit 130, and the third driving circuit 140 are included in the level shifter 100, thereby reducing the low power performed by the level shifter 100. It has the advantage of being able to perform high-speed operations.

Figure 2 is a circuit diagram of a level shifter 200 according to an embodiment of the present disclosure.

Referring to FIG. 2 , the level shifter 200 may include a level shifting circuit 210, a first driving circuit 220, a second driving circuit 230, and a third driving circuit 240.

The level shifting circuit 210 may change the level of the input signal IN to output the first output signal OUT1 and the first inverted output signal OUT1_b. In some embodiments, the level shifting circuit 210 may change the level of the input signal IN to a relatively high level. The level shifting circuit 210 may be connected between the first node N1 and the second node N2.

In one embodiment, level shifting circuit 210 may be implemented as a latch-type level shifter. Specifically, the level shifting circuit 210 may include a plurality of transistors (MP1, MP2, MN1, MN2) and a plurality of inverters (INV1, INV2).

The transistor MN1 may be connected between the line to which the first voltage is applied and the first node N1. For example, the first electrode (e.g., source) of the transistor (MN1) is connected to the line to which the first voltage is applied, and the second electrode (e.g., drain) of the transistor (MN1) is connected to the first node (N1). can be connected The transistor MN1 may include a gate electrode through which the second inverted input signal IN_bb is input. Here, the first voltage may be, for example, a ground voltage (GND), but is not limited thereto. The first voltage may be referred to as the first supply voltage.

The transistor MN2 may be connected between a line to which a first voltage (eg, ground voltage GND) is applied and the second node N2. For example, the first electrode of the transistor MN2 may be connected to a line to which the first voltage is applied, and the second electrode of the transistor MN2 may be connected to the second node N2. The transistor MN2 may include a gate electrode to which the first inverted input signal IN_b is input. The gate electrode of the transistor MN2 may be connected to the fifth node N5.

The transistor MP1 may be connected between the line to which the second voltage VDDH is applied and the first node N1. For example, the first electrode (eg, source) of the transistor MP1 is connected to the line to which the second voltage VDDH is applied, and the second electrode (eg, drain) of the transistor MP1 is connected to the first node (eg, drain). It can be connected to N1). The transistor MP1 may include a gate electrode connected to the second node N2. The voltage level of the second voltage VDDH may be higher than the voltage level of the above-described first voltage (eg, ground voltage GND). In some embodiments, the voltage level of the second voltage VDDH may be higher than the voltage level of the threshold voltage of the n-type transistor. The second voltage (VDDH) may be referred to as a second supply voltage.

The transistor MP2 may be connected between the line to which the second voltage VDDH is applied and the second node N2. For example, the first electrode of the transistor MP2 may be connected to a line to which the second voltage VDDH is applied, and the second electrode of the transistor MP2 may be connected to the second node N2. The transistor MP2 may include a gate electrode connected to the first node N1.

In some embodiments, transistor MP1 and transistor MP2 are transistors of the same type, transistor MN1 and transistor MN2 are transistors of the same type, and transistor MP1 and transistor MP2 are transistors ( It may be a different type of transistor from the transistor (MN1) and transistor (MN2). Referring to FIG. 2 , for example, transistor MP1 and transistor MP2 may be a p-type transistor or PMOS, and transistor MN1 and transistor MN2 may be an n-type transistor or NMOS. However, it is not limited to this.

In one embodiment, the transistor MP1, MP2, MN1, and MN2 may have a latch structure. In this case, the transistor MP1 and transistor MP2 may be pull-up P-channel transistors. Additionally, the transistor MN1 and MN2 may be pull-down N-channel transistors.

The inverter (INV1) can receive the input signal (IN), invert the input signal (IN), and output the inverted signal. At this time, the signal in which the input signal IN is inverted may be the first inverted input signal IN_b.

The inverter INV2 may receive the first inverted input signal IN_b, invert the first inverted input signal IN_b, and output the inverted signal. At this time, the signal obtained by inverting the first inverted input signal IN_b may be the second inverted input signal IN_bb. In one embodiment, the second inverted input signal IN_bb may correspond to the input signal IN.

Each of the plurality of inverters INV1 and INV2 may be supplied with a first voltage (eg, ground voltage (GND)) and a third voltage (VDDL). The voltage level of the third voltage VDDL may be higher than the voltage level of the first voltage and lower than the voltage level of the second voltage VDDH. In some embodiments, the voltage level of the third voltage VDDL may be higher than the voltage level of the threshold voltage of the n-type transistor. The third voltage VDDL may be referred to as a third supply voltage.

The first driving circuit 220, the second driving circuit 230, and the third driving circuit 240 can shorten the pull-up time (or pull-down time) of the level shifting circuit 210.

The first driving circuit 220 includes a plurality of transistors (MN3) connected between the line to which the driving voltage (VDD) is applied and the first node (N1) and transmitting the driving voltage (VDD) to the first node (N1). , MP3, MP4).

The transistor MN3 may be connected between the first node N1 and the third node N3. For example, the first electrode (eg, source) of the transistor (MN3) is connected to the first node (N1), and the second electrode (eg, drain) of the transistor (MN3) is connected to the third node (N3). You can. The transistor MN3 may include a gate electrode to which the first inverted input signal IN_b is input.

The transistor MP3 may be connected between the line to which the driving voltage VDD is applied and the third node N3. For example, the first electrode (eg, source) of the transistor MP3 is connected to the line to which the driving voltage (VDD) is applied, and the second electrode (eg, drain) of the transistor (MP3) is connected to the third node (N3). ) can be connected to. The transistor MP3 may include a gate electrode through which the second inverted output signal OUT2_b is input.

The transistor MP4 may be connected between the third node N3 and the first node N1. For example, the first electrode (eg, source) of the transistor MP4 may be connected to the third node (N3), and the second electrode (eg, drain) of the transistor (MP4) may be connected to the first node (N1). You can. The transistor MP4 may include a gate electrode into which the second inverted input signal IN_bb is input.

In some embodiments, transistor MN3 may be a different type of transistor from transistor MP3 and transistor MP4, and transistor MP3 and transistor MP4 may be the same type of transistor. For example, transistor MN3 may be an n-type transistor, and transistors MP3 and MP4 may be p-type transistors. However, it is not limited to this.

In some embodiments, transistor MN3, which is an n-type transistor, and transistor MP4, which is a p-type transistor, are pull-up P-channel transistors (e.g., transistor MP1 and transistor MP2) included in the level shifting circuit 210. It may be a transistor that increases the pull-up speed (or pull-down speed) of . Transistor MP3, which is a p-type transistor, may be a transistor that reduces power consumption (or power consumption) of the level shifter 200.

The second driving circuit 230 includes a plurality of transistors (MN4) connected between a line to which the driving voltage (VDD) is applied and the second node (N2) and transmitting the driving voltage (VDD) to the second node (N2). , MP5, MP6).

The transistor MN4 may be connected between the second node N2 and the fourth node N4. For example, the first electrode (eg, source) of the transistor (MN4) is connected to the second node (N2), and the second electrode (eg, drain) of the transistor (MN3) is connected to the fourth node (N4). You can. The transistor MN4 may include a gate electrode through which the second inverted input signal IN_bb is input.

The transistor MP5 may be connected between the fourth node N4 and the second node N2. For example, the first electrode of the transistor MP5 may be connected to the fourth node N4, and the second electrode (eg, drain) of the transistor MP5 may be connected to the second node N2. The transistor MP5 may include a gate electrode to which the first inverted input signal IN_b is input.

The transistor MP6 may be connected between the line to which the driving voltage VDD is applied and the fourth node N4. For example, the first electrode (eg, source) of the transistor MP6 is connected to the line to which the driving voltage (VDD) is applied, and the second electrode (eg, drain) of the transistor (MP6) is connected to the fourth node (N4). ) can be connected to. The transistor MP6 may include a gate electrode through which the second output signal OUT2 is input.

In some embodiments, transistor MN4 may be a different type of transistor from transistor MP5 and transistor MP6, and transistor MP5 and transistor MP6 may be the same type of transistor. For example, transistor MN4 may be an n-type transistor and transistors MP5 and MP6 may be p-type transistors. However, it is not limited to this.

In some embodiments, transistor MN4, which is an n-type transistor, and transistor MP5, which is a p-type transistor, are pull-up P-channel transistors (e.g., transistor MP1 and transistor MP2) included in the level shifting circuit 210. It may be a transistor that increases the pull-up speed (or pull-down speed) of . Transistor MP6, which is a p-type transistor, may be a transistor that reduces power consumption (or power consumption) of the level shifter 200.

In one embodiment, the transistors MP3 and MP4 included in the first driving circuit 220 and the transistors MP5 and MP6 included in the second driving circuit 230 are PMOS, and the first The transistor MN3 included in the driving circuit 220 and the transistor MN4 included in the second driving circuit 230 may be NMOS.

The third driving circuit 240 is connected to the second node N2 and includes a second inverted output signal OUT2_b, a second output signal OUT2, a third inverted output signal OUT3_b, and a third output signal ( It may include a plurality of inverters (INV3, INV4, INV5, INV6) that output OUT3). The second inverted output signal OUT2_b is output to the first driving circuit 220, the second output signal OUT2 is output to the second driving circuit 230, and the third output signal OUT3 is output to the level shifter ( 200) can be output outside.

The inverter INV3 may receive the first output signal OUT1, invert the first output signal OUT1, and output the inverted signal. At this time, the inverted signal of the first output signal OUT1 may be the second inverted output signal OUT2_b.

The inverter INV4 may receive the second inverted output signal OUT2_b, invert the second inverted output signal OUT2_b, and output the inverted signal. At this time, the signal obtained by inverting the second inverted output signal OUT2_b may be the second output signal OUT2.

In some embodiments, the inverters INV3 and INV4 may be inverters for controlling the logic of each of the first driving circuit 220 and the second driving circuit 230. Specifically, for example, the inverters INV3 and INV4 may invert the input signal when the level of the input signal increases above the reference level. Specifically, as another example, the inverters INV3 and INV4 may invert the input signal when the level of the input signal decreases below the reference level. Here, the reference level may be a reference level for each inverter to start the operation of inverting the signal. Since the inverter INV3 and the inverter INV4 are included in the third driving circuit 240, the impedances of the second inverted output signal OUT2_b and the second output signal OUT2 may be the same. According to this, there is an effect of preventing the influence of impedance due to the circuit receiving the third output signal OUT3 being input to the output terminal of the level shifter 200.

The inverter INV5 may receive the second output signal OUT2, invert the second output signal OUT2, and output the inverted signal. At this time, the inverted signal of the second output signal OUT2 may be the third inverted output signal OUT3_b.

The inverter INV6 may receive the third inverted output signal OUT3_b, invert the third inverted output signal OUT3_b, and output the inverted signal. At this time, the signal inverted from the third inverted output signal OUT3_b may be the third output signal OUT3.

In some embodiments, the inverter INV5 and the inverter INV6 may invert the input signal when the level of the input signal increases above the reference level or the level of the input signal decreases below the reference level. there is.

Each of the plurality of inverters (INV3, INV4, INV5, INV6) may be supplied with a first voltage (eg, ground voltage (GND)) and a second voltage (VDDH).

In some embodiments, a plurality of inverters (INV3, INV4, INV5, INV6) may be connected in series.

In some embodiments, the driving voltage VDD may be one of the second voltage VDDH and the third voltage VDDL. For example, the driving voltage (VDD) may be the second voltage (VDDH). For another example, the driving voltage VDD may be the third voltage VDDL. The voltage level of the third voltage VDDL may be higher than the voltage level of the first voltage (eg, ground voltage GND) and lower than the voltage level of the second voltage VDDH.

In Figure 2, n-type transistors and p-type transistors are shown separately, but the embodiments are not limited thereto. Depending on the implementation status of the signals shown in FIG. 2, the types of transistors may also be modified differently.

According to the above, there is an advantage in achieving high-speed operation and low power consumption of the level shifter 200 by shortening the propagation delay time of the level shifter 200.

Figure 3 is a pull-up operation timing diagram of the level shifter 200 according to an embodiment of the present disclosure. FIG. 4 is a circuit diagram of the level shifter 200 operating in the first period P1 shown in FIG. 3 . FIG. 5 is a circuit diagram of the level shifter 200 operating in the second period P2 shown in FIG. 3. FIG. 6 is a circuit diagram of the level shifter 200 operating in the third period P3 shown in FIG. 3. FIG. 7 is a circuit diagram of the level shifter 200 operating in the fourth period P4 shown in FIG. 3.

In the circuit diagrams shown in FIGS. 4 to 7, it is assumed that the transistor indicated by a dotted line is turned off, and the transistor indicated by a solid line is assumed to be turned on. And, in the circuit diagrams shown in FIGS. 4 to 7, it is assumed that the transistors MP1 to MP6 are p-type transistors and the transistors MN1 to MN4 are n-type transistors.

Referring to FIG. 3 , in some embodiments, a period during which a pull-up operation of the level shifter 200 is performed may include first to fourth periods P1, P2, P3, and P4.

The first period (P1) may include the time from t0 to t1. In the first period P1, the level of the input signal IN may be the first level. Here, the first level may correspond to the voltage level of the ground voltage (GND) described above with reference to FIG. 2. The level of the second inverted input signal IN_bb, the level of the first output signal OUT1, and the level of the third output signal OUT3 may also be the first level.

In the first period P1, the level of the first inverted output signal OUT1_b may be a second level higher than the first level. The second level may correspond to the voltage level of the second voltage VDDH described above with reference to FIG. 2.

In the first period P1, the level of the first inverted input signal IN_b may be the third level. The third level may correspond to the voltage level of the third voltage VDDL described above with reference to FIG. 2.

Referring to FIG. 4, in the first period P1, some of the n-type transistors MN1 to MN4 (MN1, MN4) may be turned off and the remaining transistors (MN2, MN3) may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP2, MP3, and MP5) may be turned off and the remaining transistors (MP1, MP4, and MP6) may be turned on. When the transistor MN2 is turned on, the voltage level of the voltage generated at the second node N2 may be the same as the voltage level of the first voltage. Accordingly, the level of the first output signal OUT1 may be the first level. The level of the second inverted output signal OUT2_b may be the second level. The level of the second output signal OUT2 may be the same as the first level of the first output signal OUT1. The level of the third inverted output signal OUT3_b may be the second level. Meanwhile, when the transistor MP1 is turned on, the voltage level of the voltage generated at the first node N1 may be at the second level. Accordingly, the level of the first inverted output signal OUT1_b may be the second level.

Referring to FIG. 3, when a period elapses from the first period P1 to the second period P2, the level of the input signal IN may transition from the first level to the third level. The second period (P2) may include the time from t1 to t2.

In the second period (P2) after the first period (P1), the level of the first inverted input signal (IN_b) and the level of the third output signal (OUT3) may be the first level.

In the second period P2, the level of the first inverted output signal OUT1_b may be the second level.

In the second period P2, the level of the second inverted input signal IN_bb may be the third level.

In the second period P2, the level of the first output signal OUT1 may increase from the first level to the reference level Vth. Here, the reference level (Vth) may be a reference level for each inverter included in the third driving circuit 240 to start the operation of inverting the signal. In some embodiments, the reference level (Vth) may be lower than the second level (eg, the voltage level of the second voltage (VDDH)).

Referring to FIG. 5 , in the second period P2, some transistors MN2 and MN3 among the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN1 and MN4 may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP2, MP3, and MP4) may be turned off and the remaining transistors (MP1, MP5, and MP6) may be turned on. When the transistors MP5 and MP6 are turned on, the driving voltage VDD may be applied to the second node N2. In this case, the voltage level of the voltage generated at the second node N2 (eg, the level of the first output signal OUT1) may rapidly increase. However, when the voltage level at the second node N2 is lower than the reference level Vth, the plurality of inverters INV3, INV4, INV5, and INV6 may not operate and may standby. At this time, the level of the second inverted output signal OUT2_b may be the second level. And, the level of the second output signal OUT2 may be the first level. Meanwhile, the level of the third inverted output signal OUT3_b may be the second level.

Referring to FIG. 3, in the third period (P3) after the second period (P2), the level of the first inverted input signal (IN_b) may be the first level. The third period (P3) may include the time from t2 to t3.

In the third period P3, the level of the third output signal OUT3 may be the second level.

In the third period P3, the level of the input signal IN and the level of the second inverted input signal IN_bb may be the third level.

In the third period P3, the level of the first output signal OUT1 may increase from the reference level Vth to the second level.

Referring to FIG. 6, in the third period P3, some transistors MN2 and MN3 among the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN1 and MN4 may be turned on. Among the p-type transistors MP1 to MP6, some transistors MP4 and MP6 may be turned off and the remaining transistors MP1, MP2, MP3, and MP5 may be turned on. When the transistor MP2 is turned on, the second voltage VDDH may be applied to the second node N2. In this case, the voltage level of the voltage generated at the second node N2 (eg, the level of the first output signal OUT1) may further increase. When the voltage level at the second node N2 is higher than the reference level Vth, a plurality of inverters INV3, INV4, INV5, and INV6 may operate. Accordingly, the level of the second inverted output signal OUT2_b may be the first level. And, the level of the second output signal OUT2 may be the second level. The level of the third inverted output signal OUT3_b may be the first level.

Referring to FIG. 3, in the fourth period (P4) after the third period (P3), the transition to the level of the signal may be completed. The fourth period (P4) may include the time from t3 to t4.

In the fourth period P4, the level of the first inverted input signal IN_b and the level of the first inverted output signal OUT1_b may be the first level.

In the fourth period P4, the level of the first output signal OUT1, the level of the second output signal OUT2, and the level of the third output signal OUT3 may be the second level.

In the fourth period P4, the level of the input signal IN and the level of the second inverted input signal IN_bb may be the third level.

Referring to FIG. 7 , in the fourth period P4, some transistors MN2 and MN3 among the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN1 and MN4 may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP1, MP4, and MP6) may be turned off and the remaining transistors (MP2, MP3, and MP5) may be turned on. As the transistor MP2 is turned on, the voltage level of the voltage generated at the second node N2 (i.e., the level of the first output signal OUT1) can reach the voltage level of the second voltage VDDH. there is. At this time, the level of the second inverted output signal OUT2_b may be the first level. And, the level of the second output signal OUT2 may be the second level. The level of the third inverted output signal OUT3_b may be the first level. Meanwhile, static current that may flow from the second voltage VDDH to the third voltage VDDL can be prevented.

Figure 8 is a pull-down operation timing diagram of the level shifter 200 according to an embodiment of the present disclosure. FIG. 9 is a circuit diagram of the level shifter 200 operating in the first period P1 shown in FIG. 8. FIG. 10 is a circuit diagram of the level shifter 200 operating in the second period P2 shown in FIG. 8. FIG. 11 is a circuit diagram of the level shifter 200 operating in the third period P3 shown in FIG. 8. FIG. 12 is a circuit diagram of the level shifter 200 operating in the fourth period P4 shown in FIG. 8.

In the circuit diagrams shown in FIGS. 9 to 12, it is assumed that the transistor indicated by a dotted line is turned off, and the transistor indicated by a solid line is assumed to be turned on. And, in the circuit diagrams shown in FIGS. 9 to 12, it is assumed that the transistors MP1 to MP6 are p-type transistors and the transistors MN1 to MN4 are n-type transistors.

Referring to FIG. 8 , in some embodiments, a period during which the pull-down operation of the level shifter 200 is performed may include first to fourth periods P1, P2, P3, and P4.

In the first period P1, the level of the input signal IN may be the third level. Accordingly, the level of the second inverted input signal IN_bb may also be the third level. Here, the third level may correspond to the voltage level of the above-described third voltage VDDL.

In the first period P1, the level of the first inverted input signal IN_b and the level of the first inverted output signal OUT1_b may be the first level. The first level may correspond to the voltage level of the above-described ground voltage (GND).

In the first period P1, the level of the first output signal OUT1 and the level of the third output signal OUT3 may be the second level. The second level may correspond to the voltage level of the above-described second voltage VDDH.

In one embodiment, the third level may be lower than the second level and higher than the first level.

Referring to FIG. 9 , in the first period P1, some transistors MN2 and MN3 among the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN1 and MN4 may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP1, MP4, and MP6) may be turned off and the remaining transistors (MP2, MP3, and MP5) may be turned on. When the transistor MN1 is turned on, the voltage level of the voltage generated at the first node N1 may be the same as the voltage level of the first voltage. Meanwhile, when the transistor MP2 is turned on, the voltage level of the voltage generated at the second node N2 may be the same as the voltage level of the second voltage VDDH. Accordingly, the level of the first output signal OUT1 may be the second level. The level of the second inverted output signal OUT2_b may be the first level. The level of the second output signal OUT2 may be the same as the level of the first output signal OUT1. The level of the third inverted output signal OUT3_b may be the first level.

Referring to FIG. 8 , when a period elapses from the first period P1 to the second period P2, the level of the input signal IN may transition from the second level to the first level.

In the second period (P2) after the first period (P1), the level of the second inverted input signal (IN_bb) may be the first level.

In the second period P2, the level of the third output signal OUT3 may be the second level.

In the second period P2, the level of the first inverted input signal IN_b may be the third level.

In the second period P2, the level of the first output signal OUT1 may decrease from the second level to the reference level Vth. In some embodiments, the reference level Vth may be lower than the second level (eg, the voltage level of the second voltage VDDH) and higher than the first level.

Referring to FIG. 10 , in the second period P2, some of the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN2 and MN3 may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP1, MP5, and MP6) may be turned off and the remaining transistors (MP2, MP3, and MP4) may be turned on. When the transistors MP3 and MP4 are turned on, the driving voltage VDD may be applied to the first node N1. In this case, the voltage level of the voltage generated at the first node N1 (eg, the level of the first inverted output signal OUT1_b) may rapidly increase. Meanwhile, the voltage level of the voltage generated at the second node N2 (eg, the level of the first output signal OUT1) may rapidly decrease. Multiple inverters (INV3, INV4, INV5, INV6) may not operate and standby. The level of the second inverted output signal OUT2_b may be the first level. The level of the second output signal OUT2 may be the second level. Meanwhile, the level of the third inverted output signal OUT3_b may be the first level.

Referring to FIG. 8, in the third period (P3) after the second period (P2), the level of the input signal (IN), the level of the second inverted input signal (IN_bb), and the third output signal (OUT3) The level may be the first level.

In the third period P3, the level of the first inverted input signal IN_b may be the third level.

In the third period P3, the level of the first output signal OUT1 may decrease from the reference level Vth to the first level.

Referring to FIG. 11 , in the third period P3, some of the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN2 and MN3 may be turned on. Among the p-type transistors MP1 to MP6, some transistors MP3 and MP5 may be turned off and the remaining transistors MP1, MP2, MP4, and MP6 may be turned on. When the transistor MP1 is turned on, the second voltage VDDH may be applied to the first node N1. In this case, the voltage level of the voltage generated at the first node N1 (eg, the level of the first inverted output signal OUT1_b) may further increase. Meanwhile, as the transistor MN2 is turned on, the voltage level of the voltage generated at the second node N2 (eg, the level of the first output signal OUT1) may further decrease. When the voltage level of the voltage generated at the second node N2 decreases below the reference level Vth, a plurality of inverters INV3, INV4, INV5, and INV6 may operate. Accordingly, the level of the second inverted output signal OUT2_b may be the second level. And, the level of the second output signal OUT2 may be the first level. The level of the third inverted output signal OUT3_b may be the second level.

Referring to FIG. 8, in the fourth period (P4) after the third period (P3), the level of the input signal (IN), the level of the second inverted input signal (IN_bb), and the level of the first output signal (OUT1) , and the level of the third output signal OUT3 may be the first level.

In the fourth period P4, the level of the first inverted output signal OUT1_b may be the second level.

In the fourth period P4, the level of the first inverted input signal IN_b may be the third level.

Referring to FIG. 12 , in the fourth period P4, some of the n-type transistors MN1 to MN4 may be turned off and the remaining transistors MN2 and MN3 may be turned on. Among the p-type transistors (MP1 to MP6), some transistors (MP2, MP3, and MP5) may be turned off and the remaining transistors (MP1, MP4, and MP6) may be turned on. As the transistor MP1 is turned on, the voltage level of the voltage generated at the first node N1 (i.e., the level of the first inverted output signal OUT1_b) is maintained at the voltage level of the second voltage VDDH. You can. Meanwhile, as the transistor MN2 is turned on, the voltage level of the voltage generated at the second node N2 (i.e., the level of the first output signal OUT1) can be maintained at the voltage level of the first voltage. there is. At this time, the level of the second inverted output signal OUT2_b may be the second level. And, the level of the second output signal OUT2 may be the first level. The level of the third inverted output signal OUT3_b may be the second level.

13 is a schematic block diagram of a semiconductor device according to an embodiment of the present disclosure.

Referring to FIG. 13, the semiconductor device 300 may include a first integrated circuit (310), a level shifter (320), and a second integrated circuit (330). .

The first integrated circuit 310 may generate the first signal SIG1 by performing a series of processing operations. The first integrated circuit 310 may transmit the first signal SIG1 to the level shifter 320.

The level shifter 320 corresponds to the level shifter (eg, 100 or 200) described above with reference to FIGS. 1 to 12 and can perform the operations described above.

The level shifter 320 may receive the first signal SIG1 and output a second signal SIG2 in which the level of the first signal SIG1 is shifted. The first signal (SIG1) is input to the level shifter 320 as the above-described input signal (IN), and the second signal (SIG2) is input to the second integrated circuit 330 as the above-described third output signal (OUT3). It can be.

In some embodiments, the level shifter 320 may include a level shifting circuit and a shifting time reduction circuit.

The level shifting circuit is based on the first signal (SIG1) and the driving voltage (e.g., VDD), a first inverted input signal (e.g., IN_b) in which the first signal (SIG1) is inverted, and a first inverted input signal (e.g., , IN_b) may be configured to output a second inverted input signal (eg, IN_bb) inverted, and a first output signal (eg, OUT1) where the level of the first signal (SIG1) is shifted. The level shifting circuit may be the same as described above with reference to FIGS. 1 to 12.

The shifting time reduction circuit may transfer a driving voltage (eg, VDD) to the level shifting circuit based on the first inverted input signal (eg, IN_b) and the second inverted input signal (eg, IN_bb). In addition, the shifting time reduction circuit is based on the first output signal (e.g., OUT1), a second output signal (e.g., OUT2), an inverted output signal (e.g., OUT2_b) of the second output signal (e.g., OUT2), and a first output signal (e.g., OUT1). 1 A second signal (SIG2) corresponding to an output signal (eg, OUT1) may be generated.

In some embodiments, the shifting time reduction circuit may include first to third driving circuits.

The first driving circuit is based on an inverted output signal (e.g., OUT2_b) of the first inverted input signal (e.g., IN_b), the second inverted input signal (e.g., IN_bb), and the second output signal (e.g., OUT2), It may be configured to deliver a driving voltage (eg, VDD) to the level shifting circuit. The first driving circuit may be the same as described above with reference to FIGS. 1 to 12.

In one embodiment, the first driving circuit includes a first transistor (e.g., MP4) including a gate electrode through which a second inverted input signal (e.g., IN_bb) is input, and a first inverting input signal (e.g., IN_b) is input. It may include a second transistor (eg, MN3) including a gate electrode into which an inverted output signal (eg, OUT2_b) is input, and a third transistor (eg, MP3) including a gate electrode into which an inverted output signal (eg, OUT2_b) is input.

The second driving circuit levels the driving voltage (e.g., VDD) based on the first inverting input signal (e.g., IN_b), the second inverting input signal (e.g., IN_bb), and the second output signal (e.g., OUT2). It may be configured to transmit to a shifting circuit. The second driving circuit may be the same as described above with reference to FIGS. 1 to 12.

In one embodiment, the second driving circuit includes a fourth transistor (e.g., MP5) including a gate electrode through which a first inverted input signal (e.g., IN_b) is input, and a second inverted input signal (e.g., IN_bb) is input. It may include a fifth transistor (eg, MN4) including a gate electrode through which a second output signal (eg, OUT2) is input, and a sixth transistor (eg, MP6) including a gate electrode into which the second output signal (eg, OUT2) is input.

The third driving circuit will be configured to output a second output signal (e.g., OUT2), an inverted output signal (e.g., OUT2_b), and a second signal (SIG2) based on the first output signal (e.g., OUT1), respectively. You can. The third driving circuit may be the same as described above with reference to FIGS. 1 to 12.

In one embodiment, the third driving circuit includes a first inverter (e.g., INV3) that receives a first output signal (e.g., OUT1) and outputs an inverted output signal (e.g., OUT2_b), and an inverter output signal (e.g., OUT2_b). ), a second inverter (e.g., INV4) that receives the input and outputs a second output signal (e.g., OUT2), and a second inverter (e.g., INV4) that receives the second output signal (e.g., OUT2) and the second output signal (e.g., OUT2) is inverted. It may include a third inverter (e.g., INV5) that outputs, and a fourth inverter (e.g., INV6) that receives the inverted signal of the second output signal (e.g., OUT2) and outputs the second signal (SIG2). there is.

The second integrated circuit 330 may receive the second signal SIG2 from the level shifter 320. The second integrated circuit 330 may process the second signal SIG2.

The various embodiments of the present disclosure described above may be combined with additional embodiments and may be changed within the scope understandable to those skilled in the art in light of the above detailed description. The embodiments of the present disclosure should be understood in all respects as illustrative and not restrictive. For example, each component described as unitary may be implemented in a distributed manner, and similarly, components described as distributed may also be implemented in a combined form. Accordingly, all changes or modified forms derived from the meaning and scope of the claims of the present disclosure and their equivalent concepts should be construed as being included in the scope of the present disclosure.

Claims (20)

a first driving circuit connected between a line to which a driving voltage is applied and a first node and including a plurality of transistors that transmit the driving voltage to the first node;
a second driving circuit connected between a line to which the driving voltage is applied and a second node and including a plurality of transistors that transmit the driving voltage to the second node;
It is connected to the second node and outputs an inverted output signal in which the first output signal is inverted to the first driving circuit, outputs a second output signal in which the inverted output signal is inverted to the second driving circuit, and the first output signal is connected to the second node. a third driving circuit including a plurality of inverters that output a third output signal corresponding to the signal; and
Receives an input signal, outputs a first inverted input signal obtained by inverting the input signal and a second inverted input signal obtained by inverting the first inverted input signal to the first driving circuit and the second driving circuit, and the input A level shifter comprising a level shifting circuit configured to output a level-shifted signal as the first output signal to the second node. According to claim 1,
The first driving circuit is,
a first transistor connected between the first node and the third node and including a gate electrode to which the first inverted input signal is input;
a second transistor connected between the line to which the driving voltage is applied and the third node, and including a gate electrode through which the inverted output signal is input; and
A level shifter comprising a third transistor connected between the first node and the third node and including a gate electrode through which the second inverted input signal is input. According to clause 2,
The first transistor is a transistor of a type different from that of the second transistor and the third transistor,
A level shifter, characterized in that the second transistor and the third transistor are transistors of the same type. According to claim 1,
The second driving circuit is,
a first transistor connected between the second node and the fourth node and including a gate electrode to which the second inverted input signal is input;
a second transistor connected between the second node and the fourth node and including a gate electrode to which the first inverted input signal is input; and
A level shifter, characterized in that it includes a third transistor connected between the line to which the driving voltage is applied and the fourth node, and including a gate electrode through which the second output signal is input. According to clause 4,
The first transistor is a transistor of a type different from that of the second transistor and the third transistor,
A level shifter, characterized in that the second transistor and the third transistor are transistors of the same type. According to claim 1,
The third driving circuit is,
a first inverter that receives the first output signal and outputs the inverted output signal; and
A level shifter comprising a second inverter connected in series with the first inverter and receiving the inverted output signal and outputting the second output signal. According to clause 6,
The third driving circuit is,
a third inverter connected in series with the second inverter, receiving the second output signal and outputting an inverted signal of the third output signal; and
The level shifter is connected in series with the third inverter, and further includes a fourth inverter that receives the signal inverted with the third output signal and outputs the third output signal. According to claim 1,
The level shifting circuit is,
a first transistor connected between a line to which a first voltage is applied and the first node, and including a gate electrode to which the second inverted input signal is input;
a second transistor connected between the line to which the first voltage is applied and the second node, and including a gate electrode to which the first inverted input signal is input;
a third transistor connected between the first node and a line to which a second voltage having a voltage level higher than the voltage level of the first voltage is applied, and including a gate electrode connected to the second node;
a fourth transistor connected between the line to which the second voltage is applied and the second node, and including a gate electrode connected to the first node;
a first inverter that receives the input signal and outputs the first inverted input signal; and
A second inverter that receives the first inverted input signal and outputs the second inverted input signal,
The driving voltage is,
A level shifter, characterized in that one of the second voltage and a third voltage having a voltage level higher than the voltage level of the first voltage and lower than the voltage level of the second voltage. Based on the input signal and the driving voltage, a first inverted input signal in which the input signal is inverted, a second inverted input signal in which the first inverted input signal is inverted, and a first output signal in which the level of the input signal is shifted. Level shifting circuits configured to output each; and
The driving voltage is transmitted to the level shifting circuit based on the first inverted input signal and the second inverted input signal, and a second output signal is provided based on the first output signal and an inverted output signal of the second output signal. , and a shifting time reduction circuit configured to respectively generate a third output signal corresponding to the first output signal,
In a first period in which the level shifting circuit operates, the level of the input signal, the level of the second inverted input signal, the level of the first output signal, the level of the second output signal, and the third output signal The level is the first level,
In the first period, the level of the inverted output signal is a second level higher than the first level,
In the first period, the level of the first inverted input signal is a third level that is lower than the second level and higher than the first level.
delete According to clause 9,
In a second period after the first period, the level of the first inverted input signal, the level of the second output signal, and the level of the third output signal are the first level,
In the second period, the level of the inverted output signal is the second level,
In the second period, the level of the input signal and the level of the second inverted input signal are the third level,
In the second period, the level of the first output signal increases from the first level to the reference level,
Level shifter, characterized in that the reference level is lower than the second level. According to claim 11,
In a third period after the second period, the level of the first inverted input signal and the level of the inverted output signal are the first level,
In the third period, the level of the second output signal and the level of the third output signal are the second level,
In the third period, the level of the input signal and the level of the second inverted input signal are the third level,
In the third period, the level of the first output signal increases from the reference level to the second level. According to claim 12,
In the fourth period after the third period, the level of the first inverted input signal is the first level,
In the fourth period, the level of the first output signal, the level of the second output signal, and the level of the third output signal are the second level,
In the fourth period, the level of the input signal and the level of the second inverted input signal are the third level. According to clause 9,
In the first period in which the level shifter operates, the level of the first inverted input signal is the first level,
In the first period, the level of the first output signal, the level of the second output signal, and the level of the third output signal are a second level higher than the first level,
In the first period, the level of the input signal and the level of the second inverted input signal are a third level lower than the second level and higher than the first level. According to claim 14,
In a second period after the first period, the level of the input signal, the level of the second inverted input signal, and the level of the inverted output signal are the first level,
In the second period, the level of the second output signal and the level of the third output signal are the second level,
In the second period, the level of the first inverted input signal is the third level,
In the second period, the level of the first output signal decreases from the second level to the reference level,
Level shifter, characterized in that the reference level is higher than the first level. According to claim 15,
In a third period after the second period, the level of the input signal, the level of the second inverted input signal, the level of the second output signal, and the level of the third output signal are the first level,
In the third period, the level of the inverted output signal is the second level,
In the third period, the level of the first inverted input signal is the third level,
In the third period, the level of the first output signal decreases from the reference level to the first level. According to claim 16,
In a fourth period after the third period, the level of the input signal, the level of the second inverted input signal, the level of the first output signal, the level of the second output signal, and the level of the third output signal. is the first level,
In the fourth period, the level of the inverted output signal is the second level,
In the fourth period, the level of the first inverted input signal is the third level. a first integrated circuit configured to transmit a first signal;
a level shifter configured to receive the first signal and output a second signal in which the level of the first signal is shifted; and
a second integrated circuit configured to receive the second signal;
The level shifter is,
Based on the first signal and the driving voltage, a first inverted input signal in which the first signal is inverted, a second inverted input signal in which the first inverted input signal is inverted, and a second inverted input signal in which the level of the first signal is shifted. 1 level shifting circuit configured to output each output signal; and
The driving voltage is transmitted to the level shifting circuit based on the first inverted input signal and the second inverted input signal, and a second output signal is provided based on the first output signal and an inverted output signal of the second output signal. , and a shifting time reduction circuit configured to respectively generate the second signal corresponding to the first output signal,
The shifting time reduction circuit,
a first driving circuit configured to transfer the driving voltage to the level shifting circuit based on an inverted output signal of the first inverted input signal, the second inverted input signal, and the second output signal;
a second driving circuit configured to transfer the driving voltage to the level shifting circuit based on the first inverted input signal, the second inverted input signal, and the second output signal; and
A semiconductor device comprising a third driving circuit configured to output the second output signal, the inverted output signal, and the second signal, respectively, based on the first output signal.
delete According to clause 18,
The first driving circuit is,
A first transistor including a gate electrode to which the second inverted input signal is input, a second transistor including a gate electrode to which the first inverted input signal is input, and a gate electrode to which the inverted output signal is input. Contains 3 transistors,
The second driving circuit is,
A fourth transistor including a gate electrode to which the first inverted input signal is input, a fifth transistor including a gate electrode to which the second inverted input signal is input, and a gate electrode to which the second output signal is input. Includes a sixth transistor,
The third driving circuit is,
A first inverter that receives the first output signal and outputs the inverted output signal, a second inverter that receives the inverted output signal and outputs the second output signal, and receives the second output signal and outputs the second output signal. A semiconductor device comprising a third inverter that outputs an inverted signal, and a fourth inverter that receives the inverted second output signal and outputs the second signal.

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