KR102686807B1 - Display Device - Google Patents

Abstract

A display device according to the present invention includes a pixel array and a gate driver. In the pixel array, pixels connected to gate lines are arranged. The gate driver sequentially applies scan signals to the gate lines using a plurality of stages that are dependently connected. The stage includes a pull-up transistor that charges the output terminal with the scan clock in response to the Q node voltage, and a pull-down transistor that discharges the output terminal to a low potential voltage in response to the voltage of the QB node, which is in phase opposite to the Q node voltage. It includes an inverter that controls the QA node by phase, a QB node control unit that charges the QB node in response to the QA node voltage, and a charging auxiliary unit that compensates for a decrease in the amount of charge charged to the QB node due to a change in the threshold voltage of the QB node control transistor. do.

Description

Display Device {Display Device}

The present invention relates to a display device.

In the display device, data lines and gate lines are arranged at right angles, and pixels are arranged in a matrix form. The video data voltage to be displayed is supplied to the data lines, and the scan signal is sequentially supplied to the gate lines. Video data voltage is supplied to the pixels of the display line to which the scan signal is supplied, and all display lines are sequentially scanned by the scan signal to display video data.

The gate driver that generates the scan signal in the display device is sometimes implemented in the form of a gate-in-panel (GIP) made up of a combination of thin film transistors in the bezel area, a non-display area of the display panel. The GIP-type gate driver has stages corresponding to the number of gate lines, and each stage outputs a scan signal to the corresponding gate line on a one-to-one basis. A number of transistors included in each stage deteriorate over time, causing the voltage-current characteristic curve to shift toward the (+) direction of voltage. When the voltage-current characteristic curve is shifted, the amount of driving current decreases even if the same voltage is applied to the gate electrode of the transistor.

In particular, when the transistor charging the QB node deteriorates and the voltage level of the voltage charged to the QB node decreases, a problem occurs in which a number of transistors connected to the QB node malfunction.

The present invention is intended to provide a display device that solves problems caused by deterioration of transistors in the stage of a shift register.

In particular, the present invention is intended to provide a display device to improve the reduction in the charging amount of the QB node due to the deterioration of the transistor of the stage.

As a means of solving the above-described problem, the display device according to the present invention includes a pixel array and a gate driver. In the pixel array, pixels connected to gate lines are arranged. The gate driver sequentially applies scan signals to the gate lines using a plurality of stages that are dependently connected. The stage includes a pull-up transistor that charges the output terminal with the scan clock in response to the Q node voltage, and a pull-down transistor that discharges the output terminal to a low potential voltage in response to the voltage of the QB node, which is in phase opposite to the Q node voltage. It includes an inverter that controls the QA node by phase, a QB node control unit that charges the QB node in response to the QA node voltage, and a charging auxiliary unit that compensates for a decrease in the amount of charge charged to the QB node due to a change in the threshold voltage of the QB node control transistor. do.

The present invention can compensate for a decrease in the charging amount of the QB node due to deterioration of the transistor.

1 is a diagram showing a display device according to the present invention.
Figure 2 is a diagram showing an example of a pixel.
Figure 3 is a diagram showing a shift register according to the present invention.
Figure 4 is a diagram showing a stage according to the first embodiment.
Figure 5 is a timing diagram showing the driving signal of the stage and the voltage change of the main node.
Figure 6 is a diagram showing the gate-source voltage change of the fourth transistor in the first embodiment.
Figure 7 is a diagram showing a stage according to the second embodiment.
Figure 8 is a diagram showing a change in gate voltage of the fourth transistor in the second embodiment.
Figure 9 is a diagram showing a stage according to the third embodiment.
Figure 10 is a diagram showing the voltage change of the QB node in the third embodiment.

Hereinafter, preferred embodiments according to the present invention will be described in detail, focusing on the liquid crystal display device, with reference to the attached drawings. Like reference numerals refer to substantially the same elements throughout the specification. In the following description, if it is determined that a detailed description of a known function or configuration related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description will be omitted. The names of the components used in the following description were selected in consideration of the ease of writing specifications and may be different from the names of the actual product.

In the shift register of the present invention, the switch elements may be implemented as transistors with an n-type or p-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure. Although an n-type transistor is illustrated in the following examples, it should be noted that the present invention is not limited thereto. A transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode through which carriers exit the transistor. That is, the flow of carriers in the MOSFET flows from the source to the drain. In the case of an n-type MOSFET (NMOS), because the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type MOSFET, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carrier is a hole, the source voltage is higher than the drain voltage to allow holes to flow from the source to the drain. In a p-type MOSFET, current flows from the source to the drain because holes flow from the source to the drain. It should be noted that the source and drain of the MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. The invention should not be limited by the source and drain of the transistor in the following embodiments.

Additionally, in this specification, the gate-on voltage refers to the operating voltage of the transistor. Since this specification describes an n-type transistor as an example, the gate high voltage is defined as the gate-on voltage.

Figure 2 is a diagram showing a display device according to an embodiment of the present invention.

Referring to FIG. 2, the display device of the present invention includes a display panel 100, a timing controller 110, a data driver 120, and gate drivers 130 and 140.

The display panel 100 includes a pixel array 100A in which data lines DL1 to DLn and gate lines GL are defined and pixels P are arranged, and various signal lines, pads, etc. are formed outside the pixel array 100A. It includes a non-display area 100B formed. The display panel 100 may use a liquid crystal display (LCD), organic light emitting diode display (OLED), or electrophoretic display (EPD).

Pixels P are formed in an area where data lines DL and gate lines GL, which are orthogonal to each other, intersect. Each pixel (P) operates in response to a scan signal supplied through a switching element (SW) connected to the gate line (GL) and the data line (DL), and expresses gradation with brightness corresponding to the data voltage. The pixel circuit (PC) and switching element (SW) of the pixels (P) may be implemented in different forms depending on the type of display panel.

The timing controller 110 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (DE), and a dot clock (DLCK) through an LVDS or TMDS interface reception circuit connected to the video board. receives input. The timing controller 110 generates a data timing control signal for controlling the operation timing of the data driver 120 and a gate timing control signal for controlling the operation timing of the gate drivers 130 and 140 based on the input timing signal.

The data timing control signal includes a source start pulse (Source Start Pulse, SSP), source sampling clock (SSC), and source output enable signal (Source Output Enable, SOE). The source start pulse (SSP) controls the shift start timing of the data driver 120. The source sampling clock (SSC) is a clock signal that controls the sampling timing of data within the data driver 120 based on the rising or falling edge.

The scan timing control signal includes a start signal (VST), carry clock (CRCLK), and scan clock (SCCLK). The start signal (VST) is input to the first stage (STG1) of the shift register 140 to control the shift start timing. The carry clock (CRCLK) and scan clock (SCCLK) are level shifted through the level shifter 130 and then input to the shift register 140.

The data driver 120 receives digital video data (RGB) and a data timing control signal from the timing controller 110. The data driver 120 generates a data voltage by converting digital video data (RGB) into a gamma voltage in response to a data timing control signal, and transmits the data voltage to the data lines DL1 to DLn of the display panel 100. supplied through

The gate drivers 130 and 140 include a level shifter 130 and a shift register 140. The level shifter 130 is formed on a printed circuit board (not shown) connected to the display panel 100 in the form of an IC. The level shifter 130 levels-shifts the start signal (VST), carry clock (CRCLK), and scan clock (SCCLK) and then supplies them to the shift register 140. Shift register 140 includes multiple stages that are dependently connected.

Figure 3 is a diagram showing a shift register according to the present invention.

Referring to FIG. 3, the shift register 140 is formed by combining a plurality of thin film transistors using the GIP method in the non-display area 100B of the display panel 100, and sequentially outputs scan signals. For this purpose, the shift register 140 includes a plurality of stages (STGs) that are dependently connected to each other.

In the following description, “front stage” refers to something located above the standard stage. For example, based on the kth stage (k is a natural number), the previous stage indicates one of the first stage to the k-1th stage. “Rear stage” refers to something located below the standard stage. For example, based on the kth stage, the subsequent stage indicates one of the k+1th stage to the last stage.

The nth (n is a natural number greater than 3) stage (STG(n)) responds to the previous carry signal (CARRY(n-3)) and outputs the nth scan signal (SCAN), which is synchronized with the output timing of the scan clock (SCCLK). (n)) is output, and the nth carry signal (CARRY(n)), which is synchronized with the output timing of the carry clock (CRCLK), is output. The front-end carry signal (CARRY(n-3)) may vary depending on the timing of the carry clock (CRCLK), and in the present invention, the nth stage (STGn) receives the (n-3)th carry signal (CARRY(n-3)). ) will be described based on an embodiment using.

The first to third stages operate by receiving a start signal (VST) instead of a carry signal.

Figure 4 is a diagram showing the nth stage according to the first embodiment.

Referring to Figures 3 and 4, the n-th stage (STG(n)) according to the present invention includes a start control unit (T1, T1A), a Q node discharge control unit (T3n, T3nA), a 3q transistor (3q), and a third Transistor (T3), 3A transistor (T3A), inverter (T4A, T4q), QB charging control transistor (T4, hereinafter referred to as the 4th transistor), charging auxiliary unit (C1), 5q transistor (T5q), carry pull-up transistor (Tpu1) , a first pull-up transistor hereinafter), a carry pull-down transistor (Tpd1, hereinafter a first pull-down transistor), a pull-up transistor (Tpu2, a second pull-up transistor), and a pull-down transistor (Tpd2, hereinafter a second pull-down transistor).

The start control unit (T1, T1A) includes a first transistor (T1) and a 1A transistor (T1A). The gate electrode and drain electrode of the first transistor (T1) are connected to the input terminal that supplies the previous carry signal (CARRY(n-3)), and the source electrode is connected to the Qh node. The gate electrode of the 1A transistor T1A is connected to the input terminal that supplies the previous carry signal CARRY(n-3), the drain electrode is connected to the Qh node, and the source electrode is connected to the Q node. The start control unit (T1, T1A) charges the Q node with a high potential voltage using the previous carry signal (CARRY(n-3)).

The Q node discharge control unit (T3N, T3NA) includes a 3n transistor (T3n) and a 3nA transistor (T3nA). The 3n transistor T3n includes a gate electrode connected to the input terminal that supplies the downstream signal CARRY(n+3), a drain electrode connected to the Q node, and a source electrode connected to the Qh node. The 3nA transistor (T3nA) has a drain electrode connected to the gate electrode Qh node connected to the input terminal that supplies the downstream signal (CARRY(n+3)) and an input terminal that supplies the second low potential driving voltage (GVSS2). Includes a source electrode. The Q node discharge control unit (T3N, T3NA) discharges the Q node to the second low-potential driving voltage (GVSS2) in response to the rear-end signal (CARRY(n+3)).

The third transistor T3 includes a gate electrode connected to the QB node, a drain electrode connected to the Q node, and a source electrode connected to the Qh node. The 3A transistor T3A includes a gate electrode connected to the QB node, a drain electrode connected to the Qh node, and a source electrode connected to an input terminal that supplies the second low-potential driving voltage GVSS2. The third transistor T3 and the third A transistor T3A respond to the voltage of the QB node and discharge the Q node to the second low-potential driving voltage GVSS2.

The 3q transistor 3q includes a gate electrode connected to the Q node, a drain electrode connected to an input terminal that supplies a high potential driving voltage (GVDD), and a source electrode connected to the Qh node. The 3q transistor 3q charges the Qh node with the high potential driving voltage (GVDD) while the Q node is at the high potential voltage. As a result, the 3rd q transistor (3q) suppresses the operation of the Q node discharge control units (T3N, T3NA) and the third transistor (T3) while the Q node is at a high potential voltage.

The inverters (T4A, T4q) include a 4A transistor (T4A) and a 4q transistor (T4q). The gate electrode and drain electrode of the 4A transistor (T4A) are connected to the input terminal that supplies the high potential driving voltage (GVDD), and the source electrode is connected to the QA node. The gate electrode of the fourth q transistor (T4q) is connected to the Q node, the drain electrode is connected to the QA node, and the source electrode is connected to the input terminal that supplies the first low-potential driving voltage (GVSS1). The inverters (T4A, T4q) maintain the voltage of the QA node in opposite phase to the voltage of the Q node. That is, the 4th q transistor (T4q) is turned on when the Q node is at a high potential voltage, and maintains the QA node at the first low driving voltage (GVSS1). When the Q node has a low potential voltage, the 4th q transistor (T4q) is turned off, and the QA node is charged with the high potential driving voltage (GVDD) supplied through the 4A transistor (T4A).

The fourth transistor (T4) charges the QB node with the high potential driving voltage (GVDD) in response to the voltage of the QA node.

The charging auxiliary unit C1 compensates so that the charging amount of the QB node does not decrease while the fourth transistor T4 charges the QB node. The charging auxiliary unit C1 may be made of a capacitor connected between the gate electrode and the source electrode of the fourth transistor T4.

The 5q transistor T5q includes a gate electrode connected to the Q node, a drain electrode connected to the QB node, and a source electrode connected to the second low-potential driving voltage GVSS2. The 5q transistor (T5q) discharges the QB node to the second low-potential driving voltage (GVSS2) in response to the Q node voltage.

The first pull-up transistor Tpu1 includes a gate electrode connected to the Q node, a drain electrode connected to an input terminal that supplies a carry clock (CRCLK), and a source electrode connected to the carry output terminal (n1). The first pull-up transistor (Tpu1) responds to the voltage of the Q node and charges the carry output terminal (n1) using the carry clock (CRCLK).

The first pull-down transistor (Tpd1) includes a gate electrode connected to the QB node, a drain electrode connected to the carry output terminal (n1), and a source electrode connected to an input terminal that supplies the second low-potential driving voltage (GVSS2). The first pull-down transistor (Tpd1) responds to the voltage of the QB node and discharges the carry output terminal (n1) to the second low-potential driving voltage (GVSS2).

The second pull-up transistor Tpu2 includes a gate electrode connected to the Q node, a drain electrode connected to an input terminal that supplies the scan clock (SCCLK), and a source electrode connected to the output terminal (n2). The first pull-up transistor (Tpu1) responds to the voltage of the Q node and charges the output terminal (n2) using the scan clock (SCCLK).

The second pull-down transistor Tpd2 includes a gate electrode connected to the QB node, a drain electrode connected to the output terminal (n2), and a source electrode connected to an input terminal that supplies a low-potential driving voltage (GVSS0). The second pull-down transistor (Tpd2) responds to the voltage of the QB node and discharges the output terminal (n2) to a low driving voltage (GVSS0).

FIG. 5 is a timing diagram showing the operation of the nth stage shown in FIG. 4.

With reference to FIGS. 4 and 5, the operation of the nth stage (STG(N)) is as follows.

During the (n-3)th horizontal period ((n-3)th H), the start control unit (T1, T1A) precharges the Q node in response to the previous carry signal (CARRY (n-3)). )do.

During the nth horizontal period (nth H), the drain electrode of the first pull-up transistor (Tpu1) rises to a high potential voltage due to the carry clock (CRCLK). Accordingly, the gate electrode of the first pull-up transistor (Tpu1) is bootstrapped, and the first pull-up transistor (Tpu1) is turned on to charge the carry output terminal (n1) with a high potential voltage. As a result, the carry output terminal (n1) outputs the nth carry signal (CARRYn) of high potential voltage.

Likewise, during the nth horizontal period (nth H), the second pull-up transistor (Tpu2) outputs the nth scan signal (SCANn) through the output terminal (n2).

During the (n+3)th horizontal period ((n+3)th H), in response to the rear end signal (CARRY(n+3)), the Q node discharge control units (T3N, T3NA) drive the Q node to the second low potential. Discharge to voltage (GVSS2). As a result, the 4th transistor T4q is turned off, and the QA node is charged with the high potential driving voltage (GVDD). The fourth transistor T4 is turned on in response to the QA node and charges the QB node with a high potential driving voltage (GVDD). The charging auxiliary unit C1 compensates so that the charging amount of the QB node does not decrease while the fourth transistor T4 charges the QB node.

The operation of the charging auxiliary unit (C1) is as follows.

The voltage that the fourth transistor (T4) charges at the QB node is proportional to the amount of driving current of the fourth transistor (T4). The voltage-current characteristic curve of the fourth transistor T4 may be shifted in the (+) direction due to deterioration. When the voltage-current characteristic curve of the fourth transistor T4 is shifted in the (+) direction, the amount of current passing through the drain electrode and the source electrode decreases even if the voltage of the gate electrode is constant. That is, when the fourth transistor T4 deteriorates, even if the voltage of the QA node is constant, the amount of charge charged to the QB node decreases, and as a result, the voltage level of the QB node becomes lower than before the deterioration. When the voltage level charged to the QB node is low, the transistors whose gate electrodes are connected to the QB node do not operate smoothly, causing malfunctions or shortening the lifespan of the GIP.

However, in the charging auxiliary unit C1 according to the first embodiment, the voltage of the gate electrode is bootstrapped according to the source electrode voltage of the fourth transistor T4. That is, when the fourth transistor T4 is turned on, the voltage of the source electrode increases due to the driving current flowing from the drain electrode to the source electrode, and the voltage of the gate electrode is bootstrapped according to the increase in the voltage of the source electrode. As a result, the gate-source voltage of the fourth transistor T4 increases and the driving current flowing through the fourth transistor T4 increases. As a result, the voltage level charged to the QB node can be further increased.

Figure 6 is a diagram showing simulation results showing the effect of the first embodiment. In FIG. 6, the first graph (gr1) is a diagram showing the gate-source voltage of the fourth transistor to which the charging auxiliary unit (C1) according to the first embodiment is connected, and the second graph (gr2) is a diagram showing the gate-source voltage when the charging auxiliary unit (C1) is not connected. This is a diagram showing the gate-source voltage of the fourth transistor. As shown in FIG. 6, the charging auxiliary unit C1 according to the first embodiment can maintain the gate-source voltage of the fourth transistor T4 higher, thereby improving incomplete charging of the voltage of the QB node. You can.

Figure 7 is a diagram showing the nth stage according to the second embodiment. In the second embodiment shown in FIG. 7, the same reference numerals are used for components that are substantially the same as those in the first embodiment described above, and detailed descriptions are omitted. The driving signal for driving the nth stage shown in FIG. 7 is the same as the driving signal shown in FIG. 5.

Referring to Figures 5 and 7, the n-th stage (STG(n)) according to the present invention includes a start control unit (T1, T1A), a Q node discharge control unit (T3n, T3nA), a 3q transistor (3q), and a third Transistor (T3), 3A transistor (T3A), inverter (T4A, T4q), QB charging control transistor (T4, hereinafter referred to as the 4th transistor), charging auxiliary unit (C2), 5q transistor (T5q), carry pull-up transistor (Tpu1) , a first pull-up transistor hereinafter), a carry pull-down transistor (Tpd1, hereinafter a first pull-down transistor), a pull-up transistor (Tpu2, a second pull-up transistor), and a pull-down transistor (Tpd2, hereinafter a second pull-down transistor).

The charging auxiliary unit (C2) is connected to the QA node and an input terminal that supplies an alternating current signal. An alternating current signal corresponds to a signal that swings within a range from a low potential voltage to a high potential voltage, and as an example, a scan clock (SCCLK) can be used. The charging auxiliary unit (C2) causes coupling between the QA node and the input terminal that supplies the scan clock (SCCLK). As a result, when the scan clock (SCCLK) is inverted from a low potential voltage to a high potential voltage, the voltage of the QA node increases due to the coupling effect. That is, the voltage of the gate electrode of the fourth transistor T4 increases in synchronization with the scan clock SCCLK. FIG. 8 is a simulation result showing that the voltage of the gate electrode of the fourth transistor T4 increases in synchronization with the scan clock SCCLK. If the QA node was at a level of about 20V in the absence of the charging auxiliary unit (C2), the voltage of the gate electrode of the fourth transistor (T4) according to the second embodiment rises to 50V or more at regular intervals by the scan clock (SCCLK). do.

In this way, according to the second embodiment, the voltage (Vgs) between the gate and source of the fourth transistor (T4) increases, and as a result, the voltage charged at the QB node increases. Accordingly, even if the voltage-current characteristic curve of the fourth transistor T4 is shifted in the (+) direction, the charging auxiliary unit C2 can be charged to a sufficient voltage level or higher.

Figure 9 is a diagram showing the nth stage according to the third embodiment. In the third embodiment shown in FIG. 9, the same reference numerals are used for components that are substantially the same as those of the above-described embodiments, and detailed descriptions are omitted. The driving signal for driving the nth stage shown in FIG. 9 is the same as the driving signal shown in FIG. 5.

Referring to Figures 5 and 9, the n-th stage (STG(n)) according to the present invention includes a start control unit (T1, T1A), a Q node discharge control unit (T3n, T3nA), a 3q transistor (3q), and a third Transistor (T3), 3A transistor (T3A), inverter (T4A, T4q), QB charging control transistor (T4, hereinafter referred to as the 4th transistor), charging auxiliary unit (C3), 5q transistor (T5q), carry pull-up transistor (Tpu1 , a first pull-up transistor hereinafter), a carry pull-down transistor (Tpd1, hereinafter a first pull-down transistor), a pull-up transistor (Tpu2, a second pull-up transistor), and a pull-down transistor (Tpd2, hereinafter a second pull-down transistor).

The charging auxiliary unit (C3) is connected to the QB node and an input terminal that supplies an alternating current signal. An alternating current signal corresponds to a signal that swings within a range from a low potential voltage to a high potential voltage, and as an example, a scan clock (SCCLK) can be used. A coupling phenomenon occurs between the QB node and the input terminal that supplies the scan clock (SCCLK) by the charging auxiliary unit (C3). As a result, when the scan clock (SCCLK) is reversed from a low voltage to a high voltage, the voltage of the QB node increases due to the coupling effect.

Since the voltage-current characteristic curve of the fourth transistor T4 is shifted in the (+) direction, the voltage charged to the QB node through the fourth transistor T4 may decrease. However, since the charging auxiliary unit C3 directly increases the voltage of the QB node using the coupling effect with the scan clock (SCCLK), it can compensate for the decrease in the voltage of the QB node.

Figure 10 is a simulation result showing that the voltage of the QB node increases in synchronization with the scan clock in the third embodiment. As shown in FIG. 10, while the voltage of the QB node charged through the fourth transistor T4 is less than 20V, the charging auxiliary unit C3 can increase the voltage of the QB node to about 30V at regular intervals.

As described above, each of the charging auxiliary units C1, C2, and C3 according to the first to third embodiments can compensate for the lowering of the voltage level charged to the QB node due to the deterioration of the fourth transistor T4. there is.

Embodiments of the present specification have been described focusing on embodiments in which a single charging auxiliary unit is used. However, the stage of the shift register may be implemented to include two or more charging auxiliary units according to the first to third embodiments. For example, the stage includes charging auxiliary units C1 and C2 according to the first and second embodiments, or includes charging auxiliary units C2 and C3 according to the second and third embodiments, or includes charging auxiliary units C2 and C3 according to the first and third embodiments. By way of example, it may include charging auxiliary units (C1, C3). Additionally, it may be implemented to include all of the charging auxiliary units C1, C2, and C3 according to the first to third embodiments.

Although embodiments of the present invention have been described with reference to the accompanying drawings, the technical configuration of the present invention described above can be modified by those skilled in the art in the technical field to which the present invention belongs in other specific forms without changing the technical idea or essential features of the present invention. You will understand that it can be done. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the claims described later rather than the detailed description above. In addition, the meaning and scope of the patent claims and all changes or modified forms derived from the equivalent concept should be construed as being included in the scope of the present invention.

100: display panel 110: timing controller
120: data driver 130, 140: gate driver
C1,C2,C3: Charging auxiliary unit

Claims (7)

delete delete a pixel array in which pixels connected to gate lines are arranged; and
Equipped with a gate driver that sequentially applies scan signals to the gate lines using a plurality of stages that are dependently connected,
The stage is
A pull-up transistor that charges the output terminal with a scan clock in response to the Q node voltage;
a pull-down transistor that discharges the output terminal to a low potential voltage in response to the voltage of the QB node, which is in phase opposite to the Q node voltage;
an inverter that controls the QA node in a phase opposite to the Q node voltage;
a QB node control unit that charges the QB node in response to the QA node voltage; and
It includes a charging auxiliary unit that compensates for a decrease in the amount of charge charged to the QB node due to a change in the threshold voltage of the QB node control unit,
The charging auxiliary unit
A display device that is a capacitor connected to the QA node and an input terminal that supplies an alternating current signal swinging within a range from a high potential voltage to a low potential voltage. delete According to claim 3,
A display device wherein the input terminal supplying the AC signal is an input terminal supplying the scan clock. According to claim 3,
The stage is
a carry pull-up transistor that charges a carry output terminal in response to the Q node using a carry clock having the same phase as the scan clock; and
The display device further includes a start control unit that charges the Q node in response to a carry signal output from the carry output terminal of the previous stage. delete

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