KR102719213B1 - Semiconductor device including pad pattern layers having stack-pad structure and fabricating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor device including pad pattern layers having a laminated pad structure. According to one embodiment of the present invention, the semiconductor device includes a plurality of power through silicon vias (TSVs) penetrating a plurality of semiconductor chips, a plurality of ground through silicon vias penetrating the plurality of semiconductor chips, a first pad pattern layer formed in a space between each of the plurality of semiconductor chips and extending from a first power through silicon via among the plurality of power through silicon electrodes in the direction of a first ground through silicon electrode among the plurality of ground through silicon electrodes, and a second pad pattern layer formed in the space between the plurality of semiconductor chips and extending from a second ground through silicon electrode among the plurality of ground through silicon electrodes in the direction of a second power through silicon electrode among the plurality of power through silicon electrodes, wherein the first pad pattern layer and the second pad pattern layer can form a laminated pad capacitor in the space between the plurality of semiconductor chips.

Description

{SEMICONDUCTOR DEVICE INCLUDING PAD PATTERN LAYERS HAVING STACK-PAD STRUCTURE AND FABRICATING METHOD THEREOF}

The present invention relates to a semiconductor device including pad pattern layers of a laminated pad structure, and more particularly, to a technology for increasing capacitance between a power through silicon via (TSV) electrode and a ground through silicon via electrode by including pad pattern layers of a laminated pad structure between a power through silicon via (TSV) electrode and a ground through silicon via electrode formed in a semiconductor device in which a plurality of semiconductor chips are laminated.

As technologies such as autonomous driving and artificial intelligence have recently attracted attention, research and development on high-performance and high-bandwidth memory (HBM) is actively being conducted to meet the demand for the ability to quickly and accurately process large amounts of data required for autonomous driving and artificial intelligence.

High-bandwidth memory refers to memory that vertically stacks dynamic random access memory (DRAM) using through silicon via (TSV).

High bandwidth memory has the advantage of reducing power consumption because it uses silicon through-hole electrode technology and has shorter signal lines than existing horizontally transmitted memory.

Specifically, high-bandwidth memory has the advantage of securing high bandwidth by vertically stacking multiple DRAMs, thereby dramatically increasing the number of inputs and outputs.

High bandwidth memory is showing an increasing number of stacks with each generation, but the power supply is decreasing from 1.2 V to 0.8 V.

Currently, the power supply for DDR5 memory, a type of DRAM, is 1.1V.

As the power supply decreases, the noise margin, which determines whether the logic state of the signal is HIGH or LOW, also decreases.

Therefore, power integrity in high-bandwidth memory is becoming more important over generations.

To ensure performance in high-speed/high-bandwidth systems, a stable power supply is required for integrated circuits (ICs), and the power grid for this purpose is called a Power Distribution Network (PDN).

Since all semiconductor chips in the system are connected to the PDN, if noise occurs, problems may occur in the entire system.

A representative noise that occurs in PDN is SSN (Simultaneous Switching Noise). SSN refers to the phenomenon in which a large amount of current flows momentarily when a large number of circuits switch simultaneously, and the switching current generated at this time is multiplied by the impedance of the PDN to generate unwanted voltage fluctuations.

Since this SSN voltage can degrade the performance of the system and, in the worst case, change the logic state, it is important to analyze and design the impedance of the PDN to predict and reduce the noise.

The impedance of the PDN varies depending on the location to be observed, but the impedance can be lowered by increasing the capacitance (C) and reducing the inductance (L).

A method of lowering impedance is often used by adding a decoupling capacitor to the PDN to lower the impedance.

However, the process of placing capacitors within high-bandwidth memory has the disadvantage of being complex and expensive, so a technology of placing external capacitors, such as multi-layer ceramic capacitors, on a logic die or semiconductor package is being utilized.

Korean Patent Publication No. 10-2021-0056853, “Laminated package including interposer bridge” Japanese Patent No. 6747299, “Semiconductor device, manufacturing method, electronic device” Korean Patent Publication No. 10-2021-0008917, “Large Metal Pad on TSV” Korean Patent No. 10-2047932, “Layered semiconductor circuit with impedance adjustment function”

The present invention aims to increase the capacitance between the power through silicon via (TSV) electrode and the ground through silicon electrode by including pad pattern layers of a laminated pad structure formed between a power through silicon via (TSV) electrode and a ground through silicon electrode in a semiconductor device in which a plurality of semiconductor chips are laminated, and to lower the impedance according to the increased capacitance.

The present invention aims to increase capacitance by forming a laminated pad capacitor in a region where pad pattern layers extending from each of a power silicon through-electrode and a ground silicon through-electrode are laminated.

The present invention aims to secure power integrity of a high-bandwidth memory through stable power supply by reducing simultaneous switching noise (SSN) noise affecting the power supply of a PDN (power distribution network) through a laminated pad capacitor.

The present invention aims to reduce process costs by preventing additional process costs by adding a pad pattern layer without changing the structure of a memory layer constituting a high-bandwidth memory and thus not requiring additional mask production.

According to an embodiment of the present invention, a semiconductor device includes a plurality of power through silicon vias (TSVs) penetrating a plurality of semiconductor chips, a plurality of ground through silicon vias penetrating the plurality of semiconductor chips, a first pad pattern layer formed in a space between each of the plurality of semiconductor chips and extending from a first power through silicon via among the plurality of power through silicon electrodes in the direction of a first ground through silicon electrode among the plurality of ground through silicon electrodes, and a second pad pattern layer formed in the space between the plurality of semiconductor chips and extending from a second ground through silicon electrode among the plurality of ground through silicon electrodes in the direction of a second power through silicon electrode among the plurality of power through silicon electrodes, wherein the first pad pattern layer and the second pad pattern layer can form a laminated pad capacitor in the space between the plurality of semiconductor chips.

The above-described laminated pad capacitor can increase capacitance in the horizontal interspace between the plurality of power silicon through-electrodes and the plurality of ground silicon through-electrodes, and reduce impedance based on the increased capacitance.

The above interstitial space may include a space in which each of the plurality of power silicon through-electrodes is vertically connected and a vertical interstitial space in which each of the plurality of ground silicon through-electrodes is vertically connected.

According to one embodiment of the present invention, the semiconductor device may further include a plurality of power conductive bumps electrically connecting the plurality of power silicon through-electrodes in the interspace, and a plurality of ground conductive bumps electrically connecting the plurality of ground silicon through-electrodes in the interspace.

The first pad pattern layer may be formed of the same metal material as the first power silicon through-hole electrode, and the second pad pattern layer may be formed of the same metal material as the second ground silicon through-hole electrode.

The first pad pattern layer and the second pad pattern layer are physically blocked by forming a laminated structure including a vertical space therebetween.

The above-described laminated pad capacitor may be a capacitor created through the first pad pattern layer and the second pad pattern layer in the vertical space between the first pad pattern layer and the second pad pattern layer.

The first pad pattern layer may be formed to extend from the lower portion of the first power silicon through-electrode toward the lower portion of the first ground silicon through-electrode, and the second pad pattern layer may be formed to extend from the upper portion of the second ground silicon through-electrode toward the upper portion of the second power silicon through-electrode.

According to one embodiment of the present invention, the semiconductor device may further include a third pad pattern layer formed to extend from a lower portion of the second power silicon through-electrode toward a lower portion of the second ground silicon through-electrode.

The second pad pattern layer and the third pad pattern layer can form a stacked pad capacitor within one of the semiconductor chips corresponding to the vertical space between the second pad pattern layer and the third pad pattern layer among the plurality of semiconductor chips.

A method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step of forming a plurality of power through silicon vias (TSVs) penetrating a plurality of semiconductor chips, a step of forming a plurality of ground through silicon vias penetrating the plurality of semiconductor chips, a step of extending a first pad pattern layer from a first power through silicon via among the plurality of power through silicon electrodes in a direction toward a first ground through silicon electrode among the plurality of ground through silicon electrodes in a space between each of the plurality of semiconductor chips, and a step of extending a second pad pattern layer from a second ground through silicon via among the plurality of ground through silicon electrodes in a direction toward a second power through silicon electrode among the plurality of power through silicon electrodes in the space between the plurality of semiconductor chips; and a step of forming a laminated pad capacitor in which the first pad pattern layer and the second pad pattern layer are formed in the space between the plurality of semiconductor chips.

The above-described laminated pad capacitor can increase capacitance in the horizontal interspace between the plurality of power silicon through-electrodes and the plurality of ground silicon through-electrodes, and reduce impedance based on the increased capacitance.

The present invention includes pad pattern layers having a laminated pad structure formed between a power through silicon via (TSV) electrode and a ground through silicon electrode in a semiconductor device in which a plurality of semiconductor chips are laminated, thereby increasing capacitance between the power through silicon via (TSV) electrode and the ground through silicon electrode, and lowering impedance according to the increased capacitance.

The present invention can increase capacitance by forming a laminated pad capacitor in a region where pad pattern layers extending from each of a power silicon through-electrode and a ground silicon through-electrode are laminated.

The present invention reduces simultaneous switching noise (SSN) noise that affects the power supply of a power distribution network (PDN) through a laminated pad capacitor, thereby ensuring power integrity of a high-bandwidth memory through a stable power supply.

The present invention can reduce process costs by preventing additional process costs since additional mask production is not required by adding a pad pattern layer without changing the structure of a memory layer constituting a high-bandwidth memory.

FIG. 1 is a drawing illustrating a semiconductor device including pad pattern layers of a laminated pad structure according to one embodiment of the present invention.
FIG. 2 is a drawing illustrating a method for manufacturing a laminated pad capacitor based on pad pattern layers of a laminated pad structure according to an embodiment of the present invention.
FIG. 3 is a drawing illustrating a three-dimensional structure of a laminated pad capacitor based on pad pattern layers of a laminated pad structure according to one embodiment of the present invention.
FIG. 4 is a drawing explaining the formation location of a laminated pad capacitor in a semiconductor device according to one embodiment of the present invention.
FIG. 5 is a drawing illustrating a semiconductor device including a laminated pad capacitor and a dummy structure for reducing leakage current according to one embodiment of the present invention.
FIGS. 6A and 6B are drawings explaining the shape of a dummy structure included in a semiconductor device according to one embodiment of the present invention.
FIG. 7 is a drawing explaining the results of impedance measurement of a semiconductor device including pad pattern layers of a laminated pad structure according to one embodiment of the present invention.

Below, various embodiments of this document are described with reference to the attached drawings.

It should be understood that the examples and terms used herein are not intended to limit the technology described in this document to a particular embodiment, but rather to encompass various modifications, equivalents, and/or alternatives of the embodiments.

In the following description of various embodiments, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the gist of the invention, the detailed description will be omitted.

And the terms described below are terms defined in consideration of functions in various embodiments, and may vary depending on the intention or custom of the user or operator. Therefore, the definitions should be made based on the contents throughout this specification.

In connection with the description of the drawings, similar reference numerals may be used for similar components.

A singular expression may include a plural expression unless the context clearly indicates otherwise.

In this document, expressions such as "A or B" or "at least one of A and/or B" may include all possible combinations of the items listed together.

Expressions such as "first," "second," "firstly," or "secondly," may be used to describe the components without regard to order or importance, and are only used to distinguish one component from another and do not limit the components.

When it is said that a certain (e.g., a first) component is "(functionally or communicatively) connected" or "connected" to another (e.g., a second) component, said certain component may be directly connected to said other component, or may be connected through another component (e.g., a third component).

In this specification, the phrase “configured to” may be used interchangeably with, for example, “suitable for,” “having the ability to,” “modified to,” “made to,” “capable of,” or “designed to,” in terms of hardware or software, depending on the context.

In some contexts, the expression "a device configured to" may mean that the device is "capable of" doing something in conjunction with other devices or components.

For example, the phrase "a processor configured (or set) to perform A, B, and C" can mean a dedicated processor (e.g., an embedded processor) to perform those operations, or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

Also, the term 'or' implies an inclusive or rather than an exclusive or.

That is, unless otherwise stated or clear from the context, the expression 'x utilizes a or b' means any one of the natural inclusive permutations.

The terms '..bu', '..gi', etc. used below mean a unit that processes at least one function or operation, and this can be implemented by hardware, software, or a combination of hardware and software.

FIG. 1 is a drawing illustrating a semiconductor device including pad pattern layers of a laminated pad structure according to one embodiment of the present invention.

FIG. 1 illustrates components of a semiconductor device in which a laminated pad capacitor is formed based on a laminated pad type, including pad pattern layers of a laminated pad structure according to one embodiment of the present invention.

Referring to FIG. 1, a semiconductor device (100) according to one embodiment of the present invention may be a high-bandwidth semiconductor device formed by vertically stacking a plurality of semiconductor chips.

For example, a semiconductor device (100) includes a plurality of through silicon vias (TSVs) to share signals transmitted to a plurality of vertically stacked semiconductor chips.

According to one embodiment of the present invention, a semiconductor device (100) includes a plurality of semiconductor chips, such as a first semiconductor chip (110) and a second semiconductor chip (111), which are vertically stacked.

For example, the semiconductor device (100) includes a first power silicon through-electrode (120) and a second power silicon through-electrode (121) penetrating a first semiconductor chip (110) and a second semiconductor chip (111), and includes a first ground silicon through-electrode (130) and a second ground silicon through-electrode (131) penetrating the first semiconductor chip (110) and the second semiconductor chip (111).

According to one embodiment of the present invention, the semiconductor device (100) further includes a power conductive bump (150) and a ground conductive bump (151).

For example, the power conductive bump (150) electrically connects the first power silicon through electrode (120) and the second power silicon through electrode (121).

Additionally, the ground conductive bump (151) electrically connects the first ground silicon through electrode (130) and the second ground silicon through electrode (131).

The power conductive bump (150) and the ground conductive bump (151) are formed of a metal material and can electrically connect the silicon through-hole electrodes by conducting power and ground signals.

According to one embodiment of the present invention, a semiconductor device (100) includes a first pad pattern layer (140) that extends from the lower portion of a first power silicon through electrode (120) toward the lower portion of a first ground silicon through electrode (130).

Additionally, the semiconductor device (100) includes a second pad pattern layer (141) that extends from the upper portion of the second ground silicon through electrode (131) toward the upper portion of the second power silicon through electrode (121).

That is, the first pad pattern layer (140) and the second pad pattern layer (141) form a laminated pad structure in the space between the lower region of the first semiconductor chip (110) and the upper region of the second semiconductor chip (111).

Additionally, the semiconductor device (100) includes a third pad pattern layer (142) that extends from the lower portion of the second power silicon through-hole electrode (121) toward the lower portion of the second ground silicon through-hole electrode (131).

According to one embodiment of the present invention, the first pad pattern layer (140) and the second pad pattern layer (141) can form a laminated pad capacitor (160) based on a laminated pad structure in the intervening space.

For example, the second pad pattern layer (141) and the third pad pattern layer (142) can form a laminated pad capacitor (161) based on a laminated pad structure in the intervening space.

The above description focuses on the first semiconductor chip (110) and the second semiconductor chip (111), but the semiconductor chips may be stacked in multiple layers.

Accordingly, a semiconductor device (100) according to one embodiment of the present invention may include a plurality of power through silicon vias (TSVs) and a plurality of ground through silicon electrodes penetrating a plurality of semiconductor chips.

A semiconductor device (100) includes a first pad pattern layer (140) that extends from a first power silicon through electrode (120) in a space between a first power silicon through electrode (120) and a second power silicon through electrode (121) among the spaces between each of a plurality of semiconductor chips toward a first ground silicon through electrode (130) among a plurality of ground silicon through electrodes.

In addition, the semiconductor device (100) includes a second pad pattern layer (141) formed to extend from the second ground silicon through electrode (131) toward the second power silicon through electrode (121) in the space between the first ground silicon through electrode (130) and the second ground silicon through electrode (131) among the spaces between each of the plurality of semiconductor chips.

Here, the first pad pattern layer (140) and the second pad pattern layer (141) can form a laminated pad capacitor (160) in the space between the first power silicon through electrode (120) and the second power silicon through electrode (121) and the space between the first ground silicon through electrode (130) and the second ground silicon through electrode (131).

A power conductive bump (150) and a ground conductive bump (151) can be positioned in the space between the laminated pad capacitors (160).

For example, the laminated pad capacitor (160) and the laminated pad capacitor (161) can increase the capacitance in the horizontal interspace between the plurality of power silicon through-electrodes and the plurality of ground silicon through-electrodes, and reduce the impedance based on the increased capacitance.

For example, the space between the laminated pad capacitor (160) and the laminated pad capacitor (161) formed may include a space in which each of the plurality of power silicon through-electrodes is vertically connected and a vertical space in which each of the plurality of ground silicon through-electrodes is vertically connected.

Accordingly, the present invention includes pad pattern layers having a laminated pad structure formed between a power through silicon via (TSV) electrode and a ground through silicon electrode in a semiconductor device in which a plurality of semiconductor chips are laminated, thereby increasing capacitance between the power through silicon via (TSV) electrode and the ground through silicon electrode, and lowering impedance according to the increased capacitance.

In addition, the present invention can increase capacitance by forming a laminated pad capacitor in an area where pad pattern layers extending from each of the power silicon through-electrode and the ground silicon through-electrode are laminated.

FIG. 2 is a drawing illustrating a method for manufacturing a laminated pad capacitor based on pad pattern layers of a laminated pad structure according to an embodiment of the present invention.

Referring to FIG. 2, a laminated pad structure (210) forming a laminated pad capacitor based on pad pattern layers of a laminated pad structure according to one embodiment of the present invention includes a first pad pattern layer (211) and a second pad pattern layer (212).

For example, the manufacturing method of a laminated pad capacitor has the advantage of not requiring additional mask production because it adds a pad pattern layer to an existing layer.

Therefore, the method for manufacturing a laminated pad capacitor has the advantage of not incurring additional process costs.

In other words, the present invention can reduce process costs by preventing additional process costs since additional mask production is not required by adding a pad pattern layer without changing the structure of the memory layer constituting the high-bandwidth memory.

For example, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a method for manufacturing a laminated pad capacitor.

A method for manufacturing a laminated pad capacitor according to one embodiment of the present invention can be formed in a space between a first semiconductor chip (200) and a second semiconductor chip (201).

A method for manufacturing a laminated pad capacitor according to one embodiment of the present invention is performed after the step of forming a plurality of power through silicon vias (TSVs) penetrating a plurality of semiconductor chips and the step of forming a plurality of ground through silicon vias penetrating a plurality of semiconductor chips.

For example, a method for manufacturing a laminated pad capacitor includes a step of extending a first pad pattern layer (211) from a first power silicon through electrode among a plurality of power silicon through electrodes in the direction of a first ground silicon through electrode among a plurality of ground silicon through electrodes in the space between each of a plurality of semiconductor chips.

That is, the method of manufacturing a laminated pad capacitor extends a first pad pattern layer (211) from the lower portion (Core_B_M1) of the first power silicon through-electrode of the first semiconductor chip (200) toward the lower portion of the first ground silicon through-electrode of the first semiconductor chip (200).

Additionally, the method for manufacturing a laminated pad capacitor includes a step of extending a second pad pattern layer (212) from a second ground silicon through electrode among a plurality of ground silicon through electrodes toward a second power silicon through electrode among a plurality of power silicon through electrodes.

That is, the method of manufacturing a laminated pad capacitor extends a second pad pattern layer (212) from the upper portion (Core_T_M1) of the second ground silicon through-hole electrode of the second semiconductor chip (201) toward the upper portion of the second power silicon through-hole electrode of the second semiconductor chip (201).

For example, the first pad pattern layer (211) may be formed of the same metal material as the first power silicon through-hole electrode of the first semiconductor chip (200).

Additionally, the second pad pattern layer (212) may be formed of the same metal material as the second ground silicon through-hole electrode of the second semiconductor chip (201).

For example, the first pad pattern layer (211) and the second pad pattern layer (212) are physically blocked by forming a laminated structure including a space between them vertically.

The first pad pattern layer (211) and the second pad pattern layer (212) are physically blocked.

The power silicon through-electrode and the ground silicon through-electrode are unconditionally separated and physically blocked.

That is, the first pad pattern layer (211) and the second pad pattern layer (212) may have a structure that is not electrically connected by forming a laminated structure including a vertical space between them.

For example, a laminated pad capacitor may be a capacitor created based on a laminated pad structure (210) formed by a first pad pattern layer (211) and a second pad pattern layer (212) in a vertical space between the first pad pattern layer (211) and the second pad pattern layer (212).

FIG. 3 is a drawing illustrating a three-dimensional structure of a laminated pad capacitor based on pad pattern layers of a laminated pad structure according to one embodiment of the present invention.

Referring to FIG. 3, a semiconductor device (300) according to one embodiment of the present invention is formed by including a first pad pattern layer and a second pad pattern layer forming a laminated pad structure (320) inside a semiconductor chip (310).

For example, the semiconductor device (300) may include a stacked pad structure (320) that increases as the number of stacked semiconductor chips (310) increases.

According to one embodiment of the present invention, as the number of stacked pad structures (320) increases, the number of stacked pad capacitors increases, and thus the increase in capacitance increases, and the decrease in impedance due to the increase in capacitance may also increase.

For example, when the number of stacked semiconductor chips (310) increases from 4 to 12, a decrease in impedance may occur due to an increase in capacitance.

FIG. 4 is a drawing explaining the formation location of a laminated pad capacitor in a semiconductor device according to one embodiment of the present invention.

FIG. 4 illustrates a location where a laminated pad capacitor is formed in a semiconductor device according to one embodiment of the present invention.

Referring to FIG. 4, a semiconductor device (400) according to one embodiment of the present invention has a structure in which four semiconductor chips (420) are stacked on a logic die or semiconductor package (410), and a power silicon through-electrode (430) and a ground silicon through-electrode (440) penetrate the four semiconductor chips (420).

For example, a semiconductor device (400) includes pad pattern layers extending horizontally from each of a power silicon through-electrode (430) and a ground silicon through-electrode (440), and a laminated pad capacitor (450) can be formed as the pad pattern layers form a laminated pad structure.

For example, a laminated pad capacitor (450) may be formed in the space between four semiconductor chips (420) or inside the semiconductor chip.

According to one embodiment of the present invention, the laminated pad capacitor (450) reduces impedance as capacitance increases.

The semiconductor device (400) can ensure power integrity for stable power supply as the impedance decreases.

Accordingly, the present invention can secure power integrity of a high-bandwidth memory through stable power supply by reducing simultaneous switching noise (SSN) noise that affects the power supply of a power distribution network (PDN) through a laminated pad capacitor.

FIG. 5 is a drawing illustrating a semiconductor device including a laminated pad capacitor and a dummy structure for reducing leakage current according to one embodiment of the present invention.

FIG. 5 illustrates a semiconductor device including a laminated pad capacitor for increasing capacitance between a power through-silicon electrode and a ground through-silicon electrode, while including a dummy structure for reducing signal leakage current between a signal through-silicon electrode and a ground through-silicon electrode, according to one embodiment of the present invention.

Referring to FIG. 5, a semiconductor device (500) according to one embodiment of the present invention includes a plurality of semiconductor chips stacked, and a power silicon through electrode (510), a ground silicon through electrode (520), and a signal silicon through electrode (530) penetrating the stacked semiconductor chips.

For example, the plurality of semiconductor chips include a first semiconductor chip (510) and a second semiconductor chip (511).

For example, a semiconductor device (500) includes a power pad pattern layer (540) that extends from a power silicon through electrode (510) toward a ground silicon through electrode (520) and a ground pad pattern layer (541) that extends from a ground silicon through electrode (520) toward the power silicon through electrode (510).

The power pad pattern layer (540) and the ground pad pattern layer (541) are formed in the interspace corresponding to the stacked connection portions of each of the plurality of semiconductor chips, and a stacked pad capacitor (542) is formed between the power pad pattern layer (540) and the ground pad pattern layer (541) without being physically connected by forming a stacked pad structure.

The laminated pad capacitor (542) reduces the impedance of the power distribution network by increasing the capacitance between the power silicon through electrode (510) and the ground silicon through electrode (520), and enables the semiconductor device (500) to secure power integrity as the impedance of the power distribution network is reduced.

For example, a semiconductor device (500) includes a dummy structure (550) in a substrate area of a semiconductor chip corresponding to a space between a ground silicon through electrode (520) and a signal silicon through electrode (530).

The dummy structure (550) is formed of silicon dioxide (SiO ₂ ), a material having low conductivity, and thereby reduces the conductivity of a portion of a silicon substrate of a semiconductor chip through which a ground silicon through electrode (520) and a signal silicon through electrode (530) pass, thereby reducing current leaking from the signal silicon through electrode (530) to the ground silicon through electrode (520).

That is, the dummy structure (550) can reduce leakage current that causes signal degradation due to the conductive properties of silicon in the silicon substrate portion of the first semiconductor chip (510) and the second semiconductor chip (511).

For example, when the value related to conductivity in the silicon of the semiconductor chip is 11.9, and the value related to conductivity of the dummy structure (550) is 4, the value related to conductivity in the substrates of the first semiconductor chip (510) and the second semiconductor chip (511) between the ground silicon through electrode (520) and the signal silicon through electrode (530) can be reduced to about 6.

In other words, the dummy structure (550) can improve signal integrity by reducing leakage current from the signal silicon through electrode (530) to the ground silicon through electrode (520) due to leakage current of the silicon substrate of the semiconductor chip.

According to one embodiment of the present invention, a semiconductor device (500) can improve power integrity related to power supply by reducing impedance by increasing capacitance between a power TSV and a ground TSV based on a stacked pad capacitor, while also improving signal integrity by reducing leakage current of a signal of a signal TSV through a silicon substrate to the ground TSV side based on a dummy structure.

FIGS. 6A and 6B are drawings explaining the shape of a dummy structure included in a semiconductor device according to one embodiment of the present invention.

FIG. 6a illustrates a cylindrical shape and structure of a dummy structure included in a semiconductor device according to one embodiment of the present invention.

Referring to FIG. 6a, a dummy structure (601) may be added in a cylindrical structure between a silicon through-electrode (600) penetrating the semiconductor chips of the semiconductor device or around the silicon through-electrode (600).

For example, the silicon through-electrodes (600) may be arranged in the order of a ground silicon through-electrode, a signal silicon through-electrode, a ground silicon through-electrode, and a signal silicon through-electrode, or may be arranged in the order of a ground silicon through-electrode, a signal silicon through-electrode, a signal silicon through-electrode, and a ground silicon through-electrode.

In addition, the silicon through-electrode (600) includes a ground silicon through-electrode and a signal silicon through-electrode, and the arrangement of the silicon through-electrode (600) can be changed according to the designer's intention.

For example, when the dummy structure (601) is added in a cylindrical structure, the width of the dummy structure (601) may be about 20 μm.

The dummy structure (601) is formed of silicon dioxide (SiO ₂ ), a material with low conductivity, and can reduce the current leaking between the silicon through-electrodes (600) by lowering the conductivity characteristics of the silicon substrate portion of the semiconductor chip through which the silicon through-electrodes (600) penetrate.

That is, the dummy structure (601) can reduce leakage current that causes signal degradation due to the conductive properties of silicon in the silicon substrate portion of the semiconductor chip.

FIG. 6b illustrates a box-shaped shape and structure of a dummy structure included in a semiconductor device according to one embodiment of the present invention.

Referring to FIG. 6b, a dummy structure (611) surrounding a silicon through-hole electrode (610) penetrating semiconductor chips of a semiconductor device can be added in a box-shaped structure.

For example, the silicon through-electrodes (610) may be arranged in the order of a ground silicon through-electrode, a signal silicon through-electrode, a ground silicon through-electrode, and a signal silicon through-electrode, or may be arranged in the order of a ground silicon through-electrode, a signal silicon through-electrode, a signal silicon through-electrode, and a ground silicon through-electrode.

Additionally, the silicon through-electrode (610) includes a ground silicon through-electrode and a signal silicon through-electrode, and the arrangement of the silicon through-electrode (610) can be changed according to the designer's intention.

For example, when the dummy structure (611) is added in a box-shaped structure, the outer length ( _{d_box} ) of the dummy structure (611) may be about 50 μm, and the inner length (d _{non_box} ) of the dummy structure (6011) may be 20 μm to 30 μm.

The dummy structure (611) is formed of silicon dioxide (SiO ₂ ), a material with low conductivity, and can reduce the current leaking between the silicon through-electrodes (610) by lowering the conductivity characteristics of the silicon substrate portion of the semiconductor chip through which the silicon through-electrodes (610) penetrate.

That is, the dummy structure (611) can reduce leakage current that causes signal degradation due to the conductive properties of silicon in the silicon substrate portion of the semiconductor chip.

FIG. 7 is a drawing explaining the results of impedance measurement of a semiconductor device including pad pattern layers of a laminated pad structure according to one embodiment of the present invention.

Referring to the graph (700) of Fig. 7, the horizontal axis represents the change in frequency and the vertical axis represents the change in impedance.

Graph line (701) illustrates the impedance measurement result in the case where the laminated pad structure is not included according to the prior art, and graph line (702) illustrates the impedance measurement result in the case where the laminated pad structure is included according to the present invention.

Graph (700) shows the results of impedance measurement according to the presence or absence of a stacked pad structure based on the case where 12 semiconductor chips are stacked on a semiconductor device.

In the low frequency region, the capacitance is measured as 0.9 nF with respect to the graph line (701), and the capacitance is measured as 2.5 nF with respect to the graph line (702), so it can be confirmed that the capacitance increases by about 2.7 times and the impedance decreases by about 2.7 times.

In other words, it can be confirmed by comparing graph lines (701) and (702) that the capacitance in the low-frequency region increases by about 2.7 times due to the addition of the laminated pad structure corresponding to the point (710).

In the specific embodiments described above, the components included in the invention are expressed in singular or plural depending on the specific embodiment presented.

However, the singular or plural expressions are selected appropriately for the situations presented for the convenience of explanation, and the above-described embodiments are not limited to singular or plural components, and even components expressed in the plural may be composed of singular elements, or even components expressed in the singular may be composed of plural elements.

Meanwhile, although the description of the invention has described specific embodiments, it is obvious that various modifications are possible within the scope that does not depart from the scope of the technical ideas contained in the various embodiments.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the claims described below but also by equivalents of the claims.

Claims (12)

Multiple power through silicon vias (TSVs) that penetrate multiple semiconductor chips;
A plurality of ground silicon through-hole electrodes penetrating the plurality of semiconductor chips;
A first pad pattern layer formed in the space between each of the plurality of semiconductor chips extending from a first power silicon through electrode among the plurality of power silicon through electrodes toward a first ground silicon through electrode among the plurality of ground silicon through electrodes;
A second pad pattern layer formed in the space between the above, extending from the second ground silicon through electrode among the plurality of ground silicon through electrodes toward the second power silicon through electrode among the plurality of power silicon through electrodes; and
A third pad pattern layer is formed extending from the lower portion of the second power silicon through-electrode toward the lower portion of the second ground silicon through-electrode,
The first pad pattern layer and the second pad pattern layer form a first laminated pad capacitor through the first pad pattern layer and the second pad pattern layer in the vertical space between the first pad pattern layer and the second pad pattern layer in the interspace,
The second pad pattern layer and the third pad pattern layer form a second stacked pad capacitor within one of the semiconductor chips corresponding to the vertical space between the second pad pattern layer and the third pad pattern layer among the plurality of semiconductor chips,
The first and second stacked pad capacitors are characterized by increasing the capacitance in the horizontal interspace between the plurality of power silicon through-electrodes and the plurality of ground silicon through-electrodes, and reducing the impedance based on the increased capacitance.
Semiconductor devices. delete In the first paragraph,
The above interspace is characterized in that it includes a space in which each of the plurality of power silicon through-electrodes is vertically connected and a vertical interspace in which each of the plurality of ground silicon through-electrodes is vertically connected.
Semiconductor devices. In the first paragraph,
a plurality of power conductive bumps electrically connecting the plurality of power silicon through-electrodes in the above intervening space; and
characterized in that it further comprises a plurality of ground conductive bumps electrically connecting the plurality of ground silicon through-electrodes in the above interspace.
Semiconductor devices. In the first paragraph,
The above first pad pattern layer is formed of the same metal material as the first power silicon through-hole electrode,
The second pad pattern layer is characterized in that it is formed of the same metal material as the second ground silicon through-hole electrode.
Semiconductor devices. In the first paragraph,
The first pad pattern layer and the second pad pattern layer are characterized in that they are physically blocked by forming a laminated structure including a vertical space between them.
Semiconductor devices. delete In the first paragraph,
The first pad pattern layer is formed to extend from the lower portion of the first power silicon through-electrode toward the lower portion of the first ground silicon through-electrode,
The second pad pattern layer is characterized in that it is formed to extend from the upper portion of the second ground silicon through-hole electrode toward the upper portion of the second power silicon through-hole electrode.
Semiconductor devices. delete delete A step of forming a plurality of power through silicon vias (TSVs) that penetrate a plurality of semiconductor chips;
A step of forming a plurality of ground silicon through-hole electrodes penetrating the plurality of semiconductor chips;
A step of forming a first pad pattern layer by extending from a first power silicon through electrode among the plurality of power silicon through electrodes in the space between each of the plurality of semiconductor chips toward a first ground silicon through electrode among the plurality of ground silicon through electrodes; and
A step of extending a second pad pattern layer from a second ground silicon through electrode among the plurality of ground silicon through electrodes in the space between the above toward a second power silicon through electrode among the plurality of power silicon through electrodes;
A step of forming a third pad pattern layer extending from the lower portion of the second power silicon through-electrode toward the lower portion of the second ground silicon through-electrode;
A step of forming a first laminated pad capacitor through the first pad pattern layer and the second pad pattern layer in the vertical interspace between the first pad pattern layer and the second pad pattern layer in the interspace; and
The second pad pattern layer and the third pad pattern layer include a step of forming a second stacked pad capacitor within one of the semiconductor chips corresponding to the vertical space between the second pad pattern layer and the third pad pattern layer among the plurality of semiconductor chips,
The first and second stacked pad capacitors are characterized by increasing the capacitance in the horizontal interspace between the plurality of power silicon through-electrodes and the plurality of ground silicon through-electrodes, and reducing the impedance based on the increased capacitance.
A method for manufacturing a semiconductor device. delete