KR102775548B1 - Transition metal chalcogen compound based semiconductor device array having work function controlled electrode layer and method of manufacturing the same - Google Patents

Abstract

The present invention provides a semiconductor device array based on a transition metal chalcogenide including a work function control electrode layer capable of simultaneously implementing semiconductor devices having various work functions with the same channel layer, and a method for manufacturing the same. A method for manufacturing a semiconductor device array based on a transition metal chalcogenide including a work function control electrode layer according to an embodiment of the present invention includes the steps of: providing a first substrate; simultaneously forming first and second channel pattern layers including a first phase transition metal chalcogenide compound on the first substrate; forming a first electrode layer including a second phase transition metal chalcogenide compound and exhibiting a first work function on the first channel pattern layer; and forming a second electrode layer including a second phase transition metal chalcogenide compound and exhibiting a second work function different from the first work function on the second channel pattern layer.

Description

Transition metal chalcogen compound based semiconductor device array having work function controlled electrode layer and method of manufacturing the same

The technical idea of the present invention relates to a semiconductor device, and more specifically, to a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer and a method for manufacturing the same.

Transition metal dichalcogenides are one of the next-generation semiconductor materials and are widely used in many fields such as low-power electrical devices, thermoelectric materials, display devices, hydrogen production, and photovoltaics.

As semiconductor devices are miniaturized, the size of the active layer is reduced, and the contact resistance at the metal-semiconductor contact surface within the semiconductor device becomes an important factor that determines the performance of the semiconductor device. Therefore, a technology for fabricating a device with a clean interface is required in the study of transistor devices based on transition metal chalcogenide compounds. In the direct deposition process of three-dimensional commercial metals used to fabricate conventional silicon-based field-effect transistor devices, defects occur at the interface between the metal and the semiconductor, resulting in high contact resistance values and limitations in fabricating low-power transistor devices. Therefore, an optimized process technique is required to lower the contact resistance in transistor devices based on transition metal chalcogenide compounds.

In addition, in the past, in order to change the work function of a semiconductor device, the channel layer was changed by ion implantation or other methods, but in order to simplify the process, a process method for forming semiconductor devices with various work functions using the same channel layer is required.

Korean Patent Publication No. 10-2013-0103913

The technical problem to be achieved by the technical idea of the present invention is to provide a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer capable of simultaneously implementing semiconductor devices having various work functions with the same channel layer, and a method for manufacturing the same.

However, these tasks are exemplary and the technical idea of the present invention is not limited thereto.

According to the technical idea of the present invention for achieving the above technical problem, a method for manufacturing a semiconductor device array based on a transition metal chalcogenide including a work function control electrode layer comprises the steps of: providing a first substrate; simultaneously forming first and second channel pattern layers including a first phase transition metal chalcogenide compound on the first substrate; forming a first electrode layer including a second phase transition metal chalcogenide compound and exhibiting a first work function on the first channel pattern layer; and forming a second electrode layer including a second phase transition metal chalcogenide compound and exhibiting a second work function different from the first work function on the second channel pattern layer.

In one embodiment of the present invention, the step of forming the first electrode layer may include the steps of: providing a second substrate having a first layer formed on a surface thereof, the first layer including a second phase transition metal chalcogenide compound including a second transition metal and having a first region and a second region; forming a first metal pattern layer on the first region of the first layer; using the first metal pattern layer as a mask layer, removing the second region of the first layer exposed by the first metal pattern layer to form a first pattern structure; separating the first pattern structure from the second substrate; and transferring the first pattern structure onto the first channel pattern layer of the first substrate to form the first electrode layer.

In one embodiment of the present invention, the step of forming the second electrode layer includes the steps of: providing a third substrate having a first layer formed on a surface thereof, the first layer including a second phase transition metal chalcogenide compound including a second transition metal and having a first region and a second region; forming a second metal pattern layer on the first region of the first layer; using the second metal pattern layer as a mask layer, removing the second region of the first layer exposed by the second metal pattern layer to form a second pattern structure; separating the second pattern structure from the third substrate; and transferring the second pattern structure onto the second channel pattern layer of the first substrate to form the second electrode layer, wherein the first electrode layer and the second electrode layer may have different work functions.

In one embodiment of the present invention, the step of separating the first pattern structure may include the steps of forming a transfer assistant on the second substrate to cover the first pattern structure; attaching an adhesive on the transfer assistant; and separating the transfer assistant containing the first pattern structure from the second substrate using the adhesive.

In one embodiment of the present invention, the step of forming the first electrode layer may include the step of placing a transfer assistant receiving the first pattern structure on the first channel pattern layer of the first substrate; and the step of removing the transfer assistant so that the first pattern structure remains on the first channel pattern layer.

In one embodiment of the present invention, after performing the step of disposing the transfer assistant, by heating to a temperature in the range of 100° C. to 200° C., the first phase transition metal chalcogen compound of the first channel pattern layer and the second phase transition metal chalcogen compound of the first pattern structure can form a van der Waals bond.

In one embodiment of the present invention, the step of simultaneously forming the first and second channel pattern layers may include the steps of: forming a target layer on the first substrate, in which a second phase transition metal chalcogen compound including a first transition metal is formed; providing a seed layer on which a first phase transition metal chalcogen compound including the first transition metal is formed; disposing the seed layer on at least a portion of the target layer; providing a chalcogen material on the target layer; heating the chalcogen material; when the first phase transition metal chalcogen compound of the seed layer is transferred as a seed, the second phase transition metal chalcogen compound of the target layer reacts with the chalcogen material, thereby causing the second phase transition metal chalcogen compound of the target layer to undergo a phase change to a first phase transition metal chalcogen compound to form a channel layer; and patterning the channel layer to form the first channel pattern layer and the second channel pattern layer.

In one embodiment of the present invention, the step of providing the chalcogen material may include the step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate; the step of providing the chalcogen material on the preliminary metal layer and heating it to form a compound layer of the third transition metal and the chalcogen material by preliminary chalcogenization of the third transition metal; and the step of providing the compound layer as the chalcogen material.

In one embodiment of the present invention, the step of providing the chalcogen material may be accomplished by providing the chalcogen material in a solid state, a liquid state, a gaseous state, or a mixed state thereof.

In one embodiment of the present invention, the step of providing the chalcogen material can be accomplished by providing a eutectic alloy of the chalcogen material and a transition metal.

In one embodiment of the present invention, the step of heating the chalcogen material may be such that the chalcogen material is heated and vaporized, and the vaporized chalcogen material may be provided to the transition metal chalcogen compound of the first phase of the target layer by a carrier gas composed of an inert gas or a mixed gas of a hydrogen-containing gas and an inert gas.

In one embodiment of the present invention, in the step of forming the channel layer, the phase transition to the first phase transition metal chalcogen compound can be achieved by lateral epitaxial growth from the seed layer.

In one embodiment of the present invention, in the step of providing the seed layer, the seed layer can be formed by the steps of: forming a metal layer including the first transition metal on a surface of a substrate using sputtering or electron beam evaporation; providing a chalcogen material to the metal layer and heating it to a temperature in a range of from 600° C. to less than 750° C.; and reacting the metal layer with the chalcogen material to form a chalcogenide to form a transition metal chalcogen compound layer of the second phase.

In one embodiment of the present invention, in the step of providing the seed layer, the seed layer can be formed by performing mechanical exfoliation from a first phase transition metal chalcogenide compound mother crystal.

In one embodiment of the present invention, the step of simultaneously forming the first and second channel pattern layers may include: forming a metal layer including a first transition metal on the first substrate; providing a chalcogen material to the metal layer; heating the chalcogen material to a first temperature so that the first transition metal and the chalcogen material react to form a transition metal chalcogen compound of the second phase; heating the transition metal chalcogen compound of the second phase and the chalcogen material to a second temperature higher than the first temperature so as to form a first phase transition metal chalcogen compound from the second phase transition metal chalcogen compound to form a channel layer; and patterning the channel layer to form the first channel pattern layer and the second channel pattern layer.

In one embodiment of the present invention, the first temperature may be in a range of 400°C to less than 600°C, and the second temperature may be in a range of 600°C to less than 750°C.

In one embodiment of the present invention, the transition metal chalcogenide compound of the first phase may have a crystal structure arranged in a 2H phase, and the transition metal chalcogenide compound of the second phase may have a crystal structure arranged in a 1T phase or a 1T' phase.

In one embodiment of the present invention, the first transition metal constituting the transition metal chalcogen compound of the first phase or the second transition metal constituting the transition metal chalcogen compound of the second phase includes at least one of molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd), and the first chalcogen material constituting the transition metal chalcogen compound of the first phase or the second chalcogen material constituting the transition metal chalcogen compound of the second phase may include at least one of sulfur (S), selenium (Se), and tellurium (Te).

According to the technical idea of the present invention for achieving the above technical problem, a semiconductor device array based on a transition metal chalcogenide including a work function control electrode layer is provided, which is a semiconductor device array based on a transition metal chalcogenide manufactured by the above-described manufacturing method, comprising: one or more first semiconductor devices arranged in a first device region on a first substrate; and one or more second semiconductor devices arranged in a second device region on the first substrate, wherein the first semiconductor device and the second semiconductor device have a channel layer including a transition metal chalcogenide of a first phase, and the first semiconductor device and the second semiconductor device have an electrode layer including a lower layer composed of a transition metal chalcogenide of a second phase and an upper layer disposed on the lower layer, wherein the channel layer and the lower layer form a van der Waals bond, and since the upper layer includes different metals, the first semiconductor device and the second semiconductor device can have different work functions.

According to the technical idea of the present invention for achieving the above technical task, a method for manufacturing a semiconductor device array based on a transition metal chalcogenide including a work function controlling electrode layer comprises the steps of: providing a substrate; forming a channel pattern layer including a first phase transition metal chalcogenide compound on the substrate; forming a pattern structure including a lower layer including a second phase transition metal chalcogenide compound and an upper layer including a metal; and forming an electrode layer by transferring the pattern structure onto the channel pattern layer, wherein the metal forming the upper layer can be selected to have a target work function.

According to a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to the technical idea of the present invention, semiconductor devices having various work functions can be implemented simultaneously by changing the electrode structure while using the same channel layer including a transition metal chalcogenide compound of a semiconducting 2H phase.

The effects of the present invention described above are described as examples, and the scope of the present invention is not limited by these effects.

FIG. 1 is a plan view illustrating a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.
FIG. 2 is a flow chart showing a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 4 is a flow chart showing a step of simultaneously forming the first and second channel pattern layers in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.
FIG. 5 is a flow chart showing a step of simultaneously forming the first and second channel pattern layers in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.
FIG. 6 is a flowchart showing a step of forming the first electrode layer in a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to one embodiment of the present invention.
FIG. 7 is a schematic diagram exemplarily showing a step of forming the first electrode layer in a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to one embodiment of the present invention.
FIG. 8 is an optical microscope photograph showing a channel layer formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 9 is a scanning transmission electron microscope photograph of a seed layer and a phase-change layer formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 10 is a schematic diagram showing the band structures of 1T' MoTe ₂ phase and 2H MoTe ₂ phase formed using a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 11 is an optical microscope photograph of a P-type semiconductor device formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 12 is a scanning transmission electron microscope photograph showing the microstructure of a semiconductor device formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIG. 13 shows the band structure of a transition metal chalcogenide compound applied in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.
FIGS. 14 to 18 are graphs showing electrical characteristics of a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. The embodiments of the present invention are provided to more completely explain the technical idea of the present invention to those skilled in the art, and the following embodiments may be modified in various different forms, and the scope of the technical idea of the present invention is not limited to the following embodiments. Rather, these embodiments are provided to more faithfully and completely convey the technical idea of the present invention to those skilled in the art. Like reference numerals throughout this specification denote like elements. Furthermore, various elements and areas in the drawings are schematically drawn. Therefore, the technical idea of the present invention is not limited by the relative sizes or intervals drawn in the attached drawings.

Extensive research is being conducted on novel transistor nanomaterials, such as two-dimensional van der Waals semiconductors. However, most two-dimensional semiconductors are n-type or bipolar, and the lack of unipolar p-type two-dimensional semiconductors limits the widespread use of CMOS inverters for energy-efficient circuits with low bit-power delay in two-dimensional electronic devices. Research on two-dimensional semiconductors that can be grown directly at low temperatures (below 550 °C) or easily transferred onto desired substrates and have high electrical performance is important for device fabrication targeting CMOS back-end-of-line (BEOL) compatible processes. Among transition metal dichalcogenides (TMDs), two-dimensional 2H phase molybdenum ditelluride (MoTe ₂ ) has the lowest valence band maximum energy (E _VBM ) in the range of 4.9–5.1 eV, which enables the fabrication of unipolar p-type semiconductors with suppressed electron mobility compared to other transition metal dichalcogenides. Therefore, the development of a reliable and scalable method for fabricating high-quality p-type 2H-MoTe ₂ with several layers can enable next-generation two-dimensional electronic devices for upstream and downstream processes.

However, the formation of single-crystal 2H-MoTe ₂ polymorph with 100% wafer-scale coverage by chemical vapor deposition (CVD) growth has not been achieved yet. This is because 2H-MoTe ₂ is formed only within a narrow growth window, and the uncontrolled Te flux (low equilibrium vapor pressure) during the growth hinders the polymorph control between the metallic 1T' structure and the semiconducting 2H structure due to the small free energy difference of about 35 meV per molecular weight. The partial 1T' residual products generated by CVD along with oxygen-related impurities, Te vacancies, and grain boundaries of 2H-MoTe ₂ on the surface can increase the sheet resistance of electronic devices, cause improper functioning, and thus lead to deterioration of their electrical properties. Recently, pioneering studies have been performed to synthesize 2H-MoTe ₂ using solid-solid phase transition or two-dimensional seed growth methods. However, the practical applications of these methods have limitations, such as the use of powder-based horizontal CVD or the requirement of an AlO _x passivation layer, and it is difficult to produce uniform and high-quality 2H-MoTe ₂ thin films at high speed and on a large scale. In addition, the electrical conductivity of 2H-MoTe ₂ synthesized using these methods is limited. For example, the on-state surface conductivity is less than about 10 μS, and the on-off current ratio is about 10 ⁴ . Therefore, a new growth technique is required.

When fabricating electrical contacts, the formation of interface defects such as vacancy defects, glassy layers, and alloys in 2H-MoTe ₂ -based heterojunctions can increase during the three-dimensional metallization process due to the small electronegativity difference between Mo and Te, which further weakens the bonding. These defects cause the Fermi energy level (E _F ) to be pinned at a specific energy level to form a new interface state, so that the contact properties or Schottky barrier height (SBH) cannot be effectively controlled by selecting metals with different work functions. In this regard, the p-type mobility performance of conventional 2H-MoTe ₂ field-effect transistors is mainly limited by the on/off current ratio (I _on /I _off < 10 ⁴ ), the on-state current (I _on < 1 μA/μm at V _ds = -1 V), and the field-effect hole mobility (μ _h < 10 cm ² V ^-1 s ^-1 ), even when using high-work-function 3D metal contact electrodes such as Pd and Pt. Alternatively, the vdW integration of 1T'-phase MoTe ₂ as a 2D polymorphic metal electrode can provide a very sharp and pristine interface in vertical 2D/2D metal-semiconductor junctions (MSJs). However, although 3D contact pads are required for all 2D devices, there has been no systematic study on the effect of 3D metallization on the 2D metal, which is located opposite to the 2D semiconductor in the 2D/2D MSJs. The use of two-dimensional metals as electronic components in all-two-dimensional circuits is of great importance as they are increasingly emerging. For example, graphene, VSe ₂ , NbSe ₂ , etc. are the relevant two-dimensional (semi)metal materials and can be used as contact electrodes in WSe ₂ transistors. However, the work function of two-dimensional semimetals tuned to three-dimensional metals is often overlooked. In addition, most van der Waals-integrated two-dimensional metals have been fabricated using irregular flakes either mechanically exfoliated or CVD grown, which are not practical for high-yield manufacturing. In addition, significant differences in performance metrics or field-effect transistor switching polarity raise questions about the reproducibility of polymorphic junctions using 1T'-MoTe ₂ .

Throughout the specification, it is noted that the term "electrically connected" includes components being in direct contact, components being in contact with each other through other components, and includes various ways in which components are electrically connected.

First, the first phase transition metal chalcogenide compound and the second phase transition metal chalcogenide compound described throughout the specification will be described in detail.

The above first phase transition metal chalcogen compound may be composed of a first transition metal and a first chalcogen material. The above second phase transition metal chalcogen compound may be composed of a second transition metal and a second chalcogen material. The first transition metal and the second transition metal may be the same material or different materials. The first chalcogen material and the second chalcogen material may be the same material or different materials.

The first transition metal constituting the first phase transition metal chalcogenide compound or the second transition metal constituting the second phase transition metal chalcogenide compound may include at least one of, for example, molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd). However, this is exemplary, and the first transition metal or the second transition metal may include all transition metal groups capable of forming a layered structure with chalcogen elements.

The first chalcogen material constituting the transition metal chalcogen compound of the first phase or the second chalcogen material constituting the transition metal chalcogen compound of the second phase may include, for example, at least one of sulfur (S), selenium (Se), and tellurium (Te).

The transition metal chalcogenide compound of the first phase may be a crystalline compound represented by the chemical formula MX ₂ . Here, M is a transition metal, and X is a chalcogen. Alternatively, the transition metal chalcogenide compound of the first phase may include a transition metal chalcogenide compound having a ratio of a chalcogen element to a transition metal element of 5:1 to 1:5. The transition metal chalcogenide compound of the first phase may have a crystal structure arranged in a 2H phase. The crystal structure of the 2H phase is a thermodynamically stable structure, and the transition metal chalcogenide compound of the first phase may strongly exhibit semiconductor properties and may have a relatively high band gap energy compared to the 1T phase or the 1T' phase.

The transition metal chalcogen compound of the second phase may be a crystalline compound represented by the chemical formula MX ₂ . Here, M is a transition metal, and X is a chalcogen. Alternatively, the transition metal chalcogen compound of the second phase may include a transition metal chalcogen compound having a ratio of a chalcogen element to a transition metal element of 5:1 to 1:5. When the chalcogen material is sulfur (S) or selenium (Se), the crystal structure of the transition metal chalcogen compound of the first phase may be a 1T phase. When the chalcogen material is tellurium (Te), the crystal structure of the transition metal chalcogen compound of the first phase may be a 1T' phase. The crystal structure of the 1T phase or the 1T' phase is a thermodynamically metastable state, and the transition metal chalcogen compound of the second phase strongly exhibits metallic characteristics. The above second phase transition metal chalcogen compound may have semi-metal properties.

For example, the transition metal may include molybdenum (Mo). The chalcogenide may include tellurium (Te). The transition metal chalcogenide compound of the first phase may include 2H MoTe ₂ . The transition metal chalcogenide compound of the second phase may include 1T' MoTe ₂ . However, these are exemplary and the technical idea of the present invention is not limited thereto.

FIG. 1 is a plan view illustrating a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.

Referring to FIG. 1, a semiconductor device array (1000) based on a transition metal chalcogenide compound may include one or more first semiconductor devices (1) arranged in a first device region (11) on a first substrate (10) and one or more second semiconductor devices (2) arranged in a second device region (12).

The first semiconductor element (1) may have a first work function. The second semiconductor element (2) may have a second work function different from the first work function.

The semiconductor element (1) and the second semiconductor element (2) may be P-type semiconductor elements. Alternatively, the semiconductor element (1) and the second semiconductor element (2) may be N-type semiconductor elements. Alternatively, one of the semiconductor element (1) and the second semiconductor element (2) may be a P-type semiconductor element, and the other may be an N-type semiconductor element.

According to the technical idea of the present invention, the work function and polarity of a semiconductor device can be changed by a material constituting an electrode layer rather than a channel layer.

The first element region (11) and the second element region (12) are schematically illustrated as rectangular shapes for concise explanation, but the technical idea of the present invention is not limited thereto, and may be divided into various shapes and numbers as regions where semiconductor elements having different work functions are respectively formed.

The first semiconductor element (1) and the second semiconductor element (2) may have a channel layer including a first phase transition metal chalcogen compound.

A first semiconductor element (1) may include a first channel pattern layer including a first phase transition metal chalcogenide compound; and a first electrode layer formed on the first channel pattern layer and including a first lower layer including a second phase transition metal chalcogenide compound and a first upper layer including a first metal. The first channel pattern layer and the first lower layer may form a van der Waals bond.

The second semiconductor element (2) may include a second channel pattern layer including a first phase transition metal chalcogenide compound; and a second electrode layer disposed on the second channel pattern layer and composed of a second lower layer including a second phase transition metal chalcogenide compound and a second upper layer including a second metal. The second channel pattern layer and the second lower layer may form a van der Waals bond.

According to the technical idea of the present invention, a semiconductor device array based on a transition metal chalcogenide including a work function controlling electrode layer comprises: one or more first semiconductor devices arranged in a first device region on a first substrate; and one or more second semiconductor devices arranged in a second device region on the first substrate, wherein the first semiconductor device and the second semiconductor device have a channel layer including a transition metal chalcogenide of a first phase, and the first semiconductor device and the second semiconductor device have an electrode layer including a lower layer composed of a transition metal chalcogenide of a second phase and an upper layer disposed on the lower layer, wherein the channel layer and the lower layer form van der Waals bonds, and since the upper layer includes different metals, the first semiconductor device and the second semiconductor device can have different work functions.

FIG. 2 is a flow chart showing a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to an embodiment of the present invention.

Referring to FIGS. 2 and 3, a method (S1) for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer includes the steps of: providing a first substrate (S10); simultaneously forming first and second channel pattern layers, each of which includes a first phase transition metal chalcogenide compound, on the first substrate (S20); forming a first electrode layer including a second phase transition metal chalcogenide compound and exhibiting a first work function on the first channel pattern layer (S30); and forming a second electrode layer including a second phase transition metal chalcogenide compound and exhibiting a second work function different from the first work function on the second channel pattern layer (S40).

In addition, the method (S1) for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer may further include a step (S50) of forming a gate insulating layer on the first channel pattern layer and the second channel pattern layer; and a step (S60) of forming a gate electrode on the gate insulating layer.

The step (S10) of providing the first substrate can be performed by providing the first substrate (10).

The first substrate (10) may include a first element region (11) in which a first semiconductor element (1) is formed and a second element region (12) in which a second semiconductor element (2) is formed.

The first substrate (10) may be configured by forming a silicon insulating layer on silicon. The silicon may be a silicon wafer. The silicon insulating layer may function as a reaction prevention film that prevents a reaction between the transition metal chalcogenide compound formed and the silicon. The silicon insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first substrate (10) may have a structure of SiO ₂ /Si in which a silicon oxide layer is formed on silicon. In addition, the first substrate (10) may be configured by including hexagonal boron nitride (h-BN) or mica. In addition, the first substrate (10) may be configured as a layered substrate. In addition, the substrate used below may have the same components as the first substrate.

The step (S20) of simultaneously forming the first and second channel pattern layers can be accomplished by simultaneously forming the first and second channel pattern layers (21, 22), each of which includes a first phase transition metal chalcogen compound, on the first substrate (10).

The first channel pattern layer (21) may be formed on the first element region (11) of the first substrate (10). The second channel pattern layer (22) may be formed on the second element region (12) of the first substrate (10). The first and second channel pattern layers (21, 22) may each include a transition metal chalcogen compound of the first phase.

The first and second channel pattern layers (21, 22) can be formed by patterning a semiconductor layer after forming a semiconductor layer including a transition metal chalcogen compound of the first phase. Accordingly, the first and second channel pattern layers (21, 22) can include the same material and can be formed simultaneously in the same process.

The step (S20) of simultaneously forming the first and second channel pattern layers will be described in detail with reference to FIGS. 4 and 5 below.

The step (S30) of forming the first electrode layer can be performed by forming a first electrode layer (30) including a second phase transition metal chalcogen compound and exhibiting a first work function on the first channel pattern layer (21).

The first electrode layer (30) can be formed on the first element region (11) of the first substrate (10). The first electrode layer (30) can be electrically connected to a portion of the first channel pattern layer (21). The first electrode layer (30) can function as a source/drain electrode of the first semiconductor element (1).

The first electrode layer (30) may include a first lower layer (32) including a first phase transition metal chalcogen compound and a second upper layer (34) including a metal. The first lower layer (32) and the first upper layer (34) may be physically connected by contact or electrically connected.

The first lower layer (32) may include a transition metal chalcogen compound of the second phase.

The first upper layer (34) may include a metal, for example, gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof. However, this is exemplary and the technical idea of the present invention is not limited thereto.

The step (S40) of forming the second electrode layer can be performed by forming a second electrode layer (40) that includes a second phase transition metal chalcogen compound on the second channel pattern layer (22) and exhibits a second work function different from the first work function.

The second electrode layer (40) can be formed on the second element region (12) of the first substrate (10). The second electrode layer (40) can be electrically connected to a portion of the second channel pattern layer (22). The second electrode layer (40) can function as a source/drain electrode of the second semiconductor element (2).

The second electrode layer (40) may include a second lower layer (42) including a second phase transition metal chalcogen compound and a second upper layer (44) including a metal. The second lower layer (42) and the second upper layer (44) may be physically connected by contact or electrically connected.

The second lower layer (42) may include a transition metal chalcogen compound of the second phase.

The second upper layer (44) may include a metal, for example, gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof. However, this is exemplary and the technical idea of the present invention is not limited thereto.

The metal constituting the first upper layer (34) and the metal constituting the second upper layer (44) may be different from each other, and accordingly, the first semiconductor element (1) and the second semiconductor element (2) may have different work functions. For example, the first upper layer (34) may include gold, and the second upper layer (44) may include platinum or silver.

In addition, the second electrode layer (40) may not include a second lower layer (42), but may include only a second upper layer (44) made of metal. In this case, the second electrode layer (40) may be formed by forming a metal layer on the second channel pattern layer (22) using sputtering or electron beam evaporation, and then patterning the metal layer. The patterning of the metal layer may be implemented using a photolithography method using photoresist, a lift-off method, or the like.

The formation of the first electrode layer (30) and the second electrode layer (40) will be described in detail with reference to FIGS. 6 and 7 below.

The step (S50) of forming the gate insulating layer can be performed by forming a gate insulating layer (50) on the first channel pattern layer (21) and the second channel pattern layer (22).

The gate insulating layer (50) may be formed to cover the first channel pattern layer (21) and the second channel pattern layer (22), and may also extend to cover the first electrode layer (30), the second electrode layer (40), or both. The gate insulating layer (50) may be formed using various deposition methods such as sputtering or electron beam evaporation, and various patterning methods such as photolithography and lift-off. The gate insulating layer (50) may include an insulating material, and may include, for example, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), lanthanum oxide (La ₂ O ₃ ), or a combination thereof.

The step (S60) of forming the above gate electrode can be performed by forming a gate electrode (60) on a gate insulating layer (50).

The gate electrode (60) may be positioned on the first channel pattern layer (21) and the second channel pattern layer (22), with the gate insulating layer (50) interposed therebetween. The gate electrode (60) may be formed using various deposition methods, such as sputtering or electron beam evaporation, and various patterning methods, such as photolithography and lift-off. The gate electrode (60) may include a metal, and may include, for example, gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof.

Accordingly, a first semiconductor element (1) can be completed in a first element region (11), and a second semiconductor element (2) can be completed in a second element region (12). As described above, the first semiconductor element (1) and the second semiconductor element (2) have the same channel layer, but may have different work functions because the materials constituting the electrode layers are different. The first work function of the first semiconductor element (1) may be larger or smaller than the second work function of the second semiconductor element (2).

Below, the step (S20) of forming the first and second channel pattern layers (21, 22) will be described in detail.

FIG. 4 is a flow chart showing a step of simultaneously forming the first and second channel pattern layers in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.

Referring to FIG. 4, the step of simultaneously forming the first and second channel pattern layers (S20) includes: a step of forming a target layer on which a second phase transition metal chalcogenide compound including a first transition metal is formed on the first substrate (S210); a step of providing a seed layer on which a first phase transition metal chalcogenide compound including the first transition metal is formed (S220); a step of disposing the seed layer on at least a portion of the target layer (S230); a step of providing a chalcogen material to the target layer (S240); a step of heating the chalcogen material (S250); a step of simultaneously forming a channel layer by phase-changing the second phase transition metal chalcogenide compound of the target layer into a first phase transition metal chalcogenide compound as the first phase transition metal chalcogenide compound of the seed layer is transferred as a seed and the second phase transition metal chalcogenide compound of the target layer reacts with the chalcogenide material (S260); And it may include a step (S270) of patterning the channel layer to form the first channel pattern layer and the second channel pattern layer.

The step (S210) of forming the target layer may be performed by forming a target layer on which a second phase transition metal chalcogen compound including a first transition metal is formed on the first substrate. The target layer may be formed using the steps (S310) to (S310) described below.

The step (S220) of providing the seed layer can be performed by providing a seed layer on which a first phase transition metal chalcogen compound including the first transition metal is formed.

The step of placing the seed layer (S230) can be performed by placing the seed layer on at least a portion of the target layer.

The area of the seed layer may be small compared to the area of the target layer. The target layer and the seed layer may be arranged facing each other so as to directly contact a portion of the transition metal chalcogenide compound of the first phase and a portion of the transition metal chalcogenide compound of the second phase.

The step (S240) of providing the chalcogen material may be performed by providing the chalcogen material to the target layer. For example, the step (S240) of providing the chalcogen material may be performed by placing the chalcogen material in the reactor so as to face the target layer. Additionally, the chalcogen material may be placed so as to face the seed layer.

The chalcogen material may include, for example, at least one of sulfur (S), selenium (Se), and tellurium (Te). The chalcogen material may be the same as the chalcogen material constituting the transition metal chalcogen compound of the first phase and the transition metal chalcogen compound of the second phase.

The chalcogen material may be provided in a solid state, a liquid state, a gaseous state, or a mixed state thereof. The chalcogen material may be provided, for example, as a eutectic alloy of the chalcogen material and a transition metal.

The step (S240) of providing a chalcogen material to the target layer may include the step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate; the step of providing the chalcogen material to the preliminary metal layer and heating it to form a compound layer of the third transition metal and the chalcogen material by preliminary chalcogenization of the third transition metal; and the step of providing the compound layer as the chalcogen material. However, this This is exemplary and the technical idea of the present invention is not limited thereto.

The above-described spare substrate may have the same configuration as the first substrate described above.

The above preliminary chalcogenidation can be performed, for example, at a temperature in the range of 400°C to 600°C for 1 minute to 60 minutes.

The third transition metal may include at least one of, for example, scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd). The third transition metal may include a material that forms a eutectic alloy with the chalcogen material.

For example, the third transition metal may include nickel (Ni), the chalcogen material may include tellurium (Te), and the compound may include a nickel-tellurium eutectic alloy (Ni _x Te _y ). Here, x and y are numbers that change corresponding to the oxidation number of nickel, and the ratio between x and y may be, for example, a number in the range of 1 to 10.

The step of heating the chalcogen material (S250) can be performed by heating the chalcogen material.

The step (S250) of heating the chalcogen material may further include a step of providing the chalcogen material to the second phase transition metal chalcogen compound of the target layer by vaporizing the chalcogen material. The target layer and the seed layer may be heated together by the heating. The heating may be performed at a temperature in the range of, for example, 400° C. to less than 600° C., for example, at a temperature in the range of, for example, 400° C. to 550° C., for a period of 1 minute to 4 hours. The heating may be performed by a heating unit disposed in the reactor.

The above-described vaporized chalcogen material can be provided to the transition metal chalcogen compound of the first phase of the target layer by a carrier gas, and the carrier gas can perform a function of uniformly transferring the vaporized chalcogen material to the transition metal chalcogen compound of the first phase.

The carrier gas may be composed of an inert gas or a mixture of a hydrogen-containing gas and an inert gas. The hydrogen-containing gas reacts with the chalcogen material to form a chalcogenide hydrogen gas, thereby enabling effective transport of the chalcogen material. The hydrogen-containing gas may include, for example, hydrogen gas and ammonia gas, or both. The inert gas may include, for example, nitrogen gas and argon gas, or both.

In the above mixed gas, the hydrogen-containing gas may be provided in a flow rate ranging from, for example, 50 sccm to 2,000 sccm, and the inert gas may be provided in a flow rate ranging from, for example, 300 sccm to 7,000 sccm. The ratio of the hydrogen-containing gas and the inert gas in the above mixed gas may be in a volume ratio ranging from 1:10 to 10:1.

The step (S260) of forming the channel layer may be performed by, when the transition metal chalcogen compound of the first phase of the seed layer is transferred as a seed, the transition metal chalcogen compound of the second phase of the target layer reacts with the chalcogen material, thereby causing the transition metal chalcogen compound of the second phase of the target layer to undergo a phase change into the transition metal chalcogen compound of the first phase, thereby forming a channel layer.

In addition, as the compound layer is heated, the chalcogen material can be vaporized from the compound layer, and the vaporized chalcogen material can be provided so that the second phase transition metal chalcogen compound undergoes a phase change to form the first phase transition metal chalcogen compound.

The target layer and the chalcogen material may be disposed so as to face each other so as to contact each other, or may be disposed with a gap that can minimize the escape of the vaporized chalcogen material to the outside. For example, the target layer and the preparatory metal layer may be disposed with a gap that can be minimized. Accordingly, most of the vaporized chalcogen material can reach the target layer and react with the transition metal chalcogen compound of the second phase, and a chalcogen deficiency phenomenon can be prevented during the reaction. This method may be referred to as a vertical tellurization process.

In the step (260) of forming the channel layer, the phase transition to the first phase transition metal chalcogen compound can be achieved by lateral epitaxial growth from the seed layer.

The above seed layer and the above channel layer may have a 2H MoTe ₂ phase having a (0001) aggregate structure formed equiangularly in the [0001] direction.

The step (S270) of forming the first channel pattern layer and the second channel pattern layer can be performed by patterning the channel layer. The patterning can be implemented using a photolithography method using photoresist, a lift-off method, or the like.

The above seed layer can be formed by performing mechanical exfoliation from a first phase transition metal chalcogenide compound mother crystal.

Alternatively, the seed layer may be formed in the same or similar manner as the above-described method of forming the target layer. The seed layer may be formed by: forming a metal layer including the first transition metal on a surface of a substrate using sputtering or electron beam evaporation; providing a chalcogen material to the metal layer and heating the metal layer to a temperature in a range of from 600° C. to less than 750° C.; and reacting the metal layer with the chalcogen material to form a chalcogenide to form a transition metal chalcogen compound layer of the first phase. The heating may be performed, for example, at a temperature in a range of from 400° C. to 600° C. for from 1 minute to 4 hours.

FIG. 5 is a flow chart showing a step of simultaneously forming the first and second channel pattern layers in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to one embodiment of the present invention.

Referring to FIG. 5, the step of simultaneously forming the first and second channel pattern layers (S20A) may include the steps of: forming a metal layer including a first transition metal on the first substrate (S310); providing a chalcogen material to the metal layer (S320); heating the chalcogen material to a first temperature so that the first transition metal and the chalcogen material react to form a transition metal chalcogen compound of the second phase (S330); heating the transition metal chalcogen compound of the second phase and the chalcogen material to a second temperature higher than the first temperature so as to form a first phase transition metal chalcogen compound from the second phase transition metal chalcogen compound to form a channel layer (S340); and patterning the channel layer to form the first channel pattern layer and the second channel pattern layer (S350).

The step (S310) of forming the metal layer can be performed by forming a metal layer including a first transition metal on the surface of the first substrate using sputtering or electron beam evaporation.

The step (S320) of providing the chalcogen material can be performed by providing the chalcogen material to the metal layer. It can be performed in the same manner as the step (S240) of providing the chalcogen material.

The step (S330) of forming the second phase transition metal chalcogen compound can be performed by heating the chalcogen material to a first temperature so that the first transition metal and the chalcogen material react.

The step (S340) of forming the channel layer may be performed by heating the second phase transition metal chalcogen compound and the chalcogen material to a second temperature higher than the first temperature, thereby forming the first phase transition metal chalcogen compound from the second phase transition metal chalcogen compound.

Heating to the first temperature and the second temperature can be accomplished by a heating unit disposed in the reactor.

The first temperature is a temperature at which the second phase transition metal chalcogen compound is formed, and may be, for example, in a range of 400° C. to less than 600° C. The time for maintaining the first temperature may be, for example, in a range of 1 minute to 60 minutes.

The second temperature is a temperature at which the second phase transition metal chalcogenide compound undergoes a phase transformation to form the first phase transition metal chalcogenide compound, and may be, for example, in a range of less than 600° C. to 750° C. The time for maintaining the second temperature may be, for example, in a range of 1 minute to 4 hours.

As described above, the chalcogen material can be vaporized and provided by a carrier gas.

The step (S350) of forming the first channel pattern layer and the second channel pattern layer can be performed by patterning the channel layer. The patterning can be implemented using a photolithography method using photoresist, a lift-off method, or the like.

FIG. 6 is a flowchart showing a step of forming the first electrode layer in a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to one embodiment of the present invention.

Referring to FIG. 6, the step of forming the first electrode layer (S30) includes the step of providing a second substrate having a first layer formed on a surface thereof, the first layer including a second phase transition metal chalcogenide compound including a second transition metal and having a first region and a second region; the step of forming a first metal pattern layer on the first region of the first layer (S420); the step of forming a first pattern structure by removing the second region of the first layer exposed by the first metal pattern layer using the first metal pattern layer as a mask layer (S430); the step of separating the first pattern structure from the second substrate (S440); and the step of transferring the first pattern structure onto the first channel pattern layer of the first substrate to form the first electrode layer (S450).

The step (S410) of providing the second substrate may be performed by providing a second substrate having a first layer formed on a surface thereof, the first layer including a second phase transition metal chalcogenide compound including a second transition metal and having a first region and a second region.

The second substrate may be configured by forming a silicon insulating layer on silicon. The silicon may be a silicon wafer. The silicon insulating layer may function as a reaction prevention film that prevents a reaction between the formed transition metal chalcogenide and the silicon. The silicon insulating layer may include, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the second substrate may have a structure of SiO ₂ /Si in which a silicon oxide layer is formed on silicon. In addition, the second substrate may be configured by including hexagonal boron nitride (h-BN) or mica. In addition, the second substrate may be configured as a layered substrate.

The step (S420) of forming the first metal pattern layer can be performed by forming the first metal pattern layer on the first region of the first layer.

The step (S420) of forming the first metal pattern layer may include forming a metal layer on the first layer by using sputtering or electron beam evaporation, and patterning the metal layer to form the first metal pattern layer. The patterning may be implemented by using a photolithography method using photoresist, a lift-off method, or the like. The first region of the first layer may be overlapped and covered by the first metal pattern layer, and the second region of the first layer may be exposed by the first metal pattern layer. The first metal pattern layer may include gold, platinum, silver, palladium, copper, aluminum, tungsten, molybdenum, titanium, ruthenium, iridium, or a combination thereof. However, this is exemplary and the technical idea of the present invention is not limited thereto.

The step (S430) of forming the first pattern structure can be performed by using the first metal pattern layer as a mask layer to remove the second region of the first layer exposed by the first metal pattern layer to form the first pattern structure.

The removal of the second region can be performed using plasma etching or reactive ion etching. The first substrate can be exposed between the first metal pattern layers by the removal of the second region. Accordingly, the first pattern structure composed of the first pattern layer in which the first layer is patterned and the first metal pattern layer can be formed.

The above separating step (S440) can be performed by separating the first pattern structure from the second substrate.

The above-described separating step (S440) may include a step of forming a transfer assistant to cover the first pattern structure on the second substrate; a step of attaching an adhesive on the transfer assistant; and a step of separating the transfer assistant containing the first pattern structure from the second substrate using the adhesive.

The above transfer assistant may be a solid material that is hardened after coating a liquid. The above transfer assistant may be formed using at least one of spin coating, drop coating, spray coating, screen printing, offset printing, inkjet printing, and gravure printing, for example.

The above-described transcriptional assistant may include a polymer, and may include, for example, at least one of polymethyl methacrylate (PMMA), polyimide, polyvinyl alcohol (PVA), acrylic, polybutadiene, polybenzoxazole, benzocyclo butene (BCB), polyphenylene benzobisoxazole (PBO), epoxy resin, and silicone resin.

The adhesive may be composed of a material capable of temporary adhesion and detachment, and may be, for example, a solid material that is hardened after coating a liquid, or an adhesive film. The adhesive may be composed of a base film composed of PET (polyethylene terephthalate), PP (polypropylene), PE (polyethylene), PVC (polyvinyl chloride), PI (polyimide), PEN (polyethylene naphthalene), PTFE (polytetrafluoro ethylene), ETFE (ethylene terafluoroethylene), PEEK (polyether ether keton), PPS (polyphenylene sulfide), PES (polyether sulfone), or the like, and a silicone resin or acrylic resin may be applied as an adhesive.

The above adhesive may be a thermal release tape.

The step (S450) of forming the second electrode layer can be performed by transferring the first pattern structure onto the second channel pattern layer of the first substrate.

The step (S450) of forming the second electrode layer may include the step of arranging the transfer assistant receiving the first pattern structure on the second channel pattern layer of the first substrate; and the step of removing the transfer assistant so that the first pattern structure remains on the second channel pattern layer.

In the step of forming the second electrode layer (S450), after performing the step of arranging the transfer assistant, a step of heating at a temperature in the range of 100° C. to 200° C. for 1 minute to 30 minutes may be further included. By this heating, the transition metal chalcogenide compound of the first phase of the channel layer and the transition metal chalcogenide compound of the second phase of the first pattern structure can form a van der Waals bond. The heat dissipating tape of the adhesive can transfer heat for the van der Waals bond.

The step of removing the above-mentioned transcriptional assistant can be performed using water or an organic solvent. The organic solvent can include alcohol, acetone, or the like.

The step (S40) of forming the second electrode layer can be performed in the same manner as the step (S30) of forming the first electrode layer. That is, the step (S40) of forming the second electrode layer includes the steps of: providing a third substrate having a first layer formed on a surface thereof, the first layer including a second phase transition metal chalcogenide compound including a second transition metal and having a first region and a second region; forming a second metal pattern layer on the first region of the first layer; using the second metal pattern layer as a mask layer, removing the second region of the first layer exposed by the second metal pattern layer to form a second pattern structure; separating the second pattern structure from the third substrate; and transferring the second pattern structure onto the second channel pattern layer of the first substrate to form the second electrode layer.

Here, the first metal pattern layer and the second metal pattern layer may have different work functions, and for this purpose, they may be formed using different metals, for example. For example, the first metal pattern layer may include gold, and the second metal pattern layer may include platinum or silver. However, this is an example, and the technical idea of the present invention is not limited thereto.

Additionally, the first pattern structure and the second pattern structure may include different metals. However, both the first pattern structure and the second pattern structure may include a second phase transition metal chalcogenide compound.

FIG. 7 is a schematic diagram exemplarily showing a step of forming the first electrode layer in a method for manufacturing a semiconductor device array based on a transition metal chalcogen compound including a work function control electrode layer according to one embodiment of the present invention.

Molybdenum (Mo) was selected as the first transition metal and the second transition metal, tellurium (Te) was selected as the chalcogen material, gold (Au) was selected as the material constituting the first metal pattern layer, and PMMA was selected as the transfer assistant. This is exemplary, and the technical idea of the present invention is not limited thereto.

Referring to (a) of FIG. 7, a second substrate (210) composed of SiO 2 /Si is provided, which has a first layer (220) formed on a surface thereof, which is composed of 1T' MoTe ₂ as a second phase transition metal chalcogen compound including a second _transition metal and has a first region (221) and a second region (222).

Referring to (b) of Fig. 7, a first metal pattern layer (230) composed of gold (Au) is formed on the first region (221) of the first layer (220), and the first region (222) of the first layer (220) is exposed.

Referring to (c) of Fig. 7, the first region (222) of the exposed first layer (220) is removed using plasma etching.

Referring to (d) of Fig. 7, the second substrate (210) is exposed in the portion where the first region (222) is removed. The first metal pattern layer (230) and the first pattern layer (240) in which the first layer (220) is patterned form a first pattern structure (250).

Referring to (e) of Fig. 7, a transfer auxiliary body (260) made of PMMA is formed to cover the first pattern structure (250) on the second substrate (210).

Referring to (f) of FIG. 7, after attaching an adhesive on a transfer assistant (260), the transfer assistant (260) containing the first pattern structure (250) is separated from the second substrate (210) using the adhesive.

Referring to (g) of FIG. 7, a first substrate (10) is provided having a first channel pattern layer (21) formed on a surface thereof, which is composed of 2H MoTe ₂ as a first phase transition metal chalcogen compound. A transfer assistant (260) containing a first pattern structure (250) is placed on the first channel pattern layer (21). Then, the entire structure is heated to cause van der Waals bonding between the 2H MoTe ₂ of the first channel pattern layer (21) and the 1T' MoTe ₂ of the first pattern structure (250).

Referring to (h) of Fig. 7, the transfer assistant (260) is removed using a detergent such as water or an organic solvent.

Referring to (i) of FIG. 7, the second channel pattern layer (21) includes a third region (323) and a fourth region (324). A first pattern structure (250) composed of a first metal pattern layer (230) and a first pattern layer (240) is arranged on the third region (323). The fourth region (324) is exposed with the first pattern structure (250) interposed therebetween. Accordingly, a first electrode layer (40) including a first lower layer (32) and a first upper layer (34) is formed.

According to one embodiment of the present invention, a semiconductor device based on a transition metal chalcogenide is provided, which is manufactured by the method for manufacturing a semiconductor device based on a transition metal chalcogenide described above, and includes an electrode portion formed by stacking a first phase transition metal chalcogenide layer and a metal layer; and a channel layer formed of a second phase transition metal chalcogenide layer and electrically connected to the electrode portion, wherein the first phase transition metal chalcogenide layer and the second phase transition metal chalcogenide layer form van der Waals bonds.

In the semiconductor device based on the above transition metal chalcogenide, the first phase transition metal chalcogenide includes 1T' MoTe ₂ , the second phase transition metal chalcogenide includes 2H MoTe ₂ , and the metal layer can control the work function by changing the metal included therein.

In addition, a method for manufacturing a semiconductor device array based on a transition metal chalcogenide including a work function control electrode layer according to an embodiment of the present invention comprises the steps of: providing a substrate; forming a channel pattern layer including a first phase transition metal chalcogenide compound on the substrate; forming a pattern structure including a lower layer including a second phase transition metal chalcogenide compound and an upper layer including a metal; and transferring the pattern structure onto the channel pattern layer to form the electrode layer, wherein the metal forming the upper layer can be selected to have a target work function.

Experimental example

Below, experimental examples are described to help understand the present invention. The following experimental examples are presented to help understand the invention, and the present invention is not limited to the following experimental examples.

According to the technical idea of the present invention, wafer-scale and polymorph-controlled synthesis for high-performance field-effect transistor arrays can be realized by layer-by-layer integration of semimetal 1T' MoTe ₂ and semiconductor 2H MoTe ₂ .

Preparation of transition metal chalcogenides

MoTe ₂ was selected as the transition metal chalcogen compound. Ni _x Te _y eutectic alloy was used as the tellurium source.

A nickel layer having a thickness of about 65 nm was formed on a SiO ₂ /Si substrate using DC magnetron sputtering. Then, tellurization was performed based on tellurium powder at 500° C. for 10 minutes to form a Ni _x Te _y eutectic alloy. Accordingly, a first preform in which Ni _x Te _y was formed on a SiO ₂ /Si substrate was formed.

A molybdenum (Mo) precursor layer having a thickness of 1 nm to 20 nm was formed on a SiO ₂ /Si substrate using DC magnetron sputtering. Accordingly, a second preform in which a molybdenum precursor layer was formed on the SiO ₂ /Si substrate was formed.

The first and second preforms were placed facing each other so that the Ni _x Te _y layer and the molybdenum layer faced each other, thereby forming a sandwich structure. At this time, no powder precursor was used. The sandwich structure was placed in a 4-inch quartz tube as a hot-wall furnace. The sandwich structure was heated at about 500° C. at atmospheric pressure for 1 hour, thereby forming 1T' MoTe ₂ .

The substrate on which the above 1T' MoTe ₂ was formed was used as a first substrate having a first layer including a first phase transition metal chalcogenide formed on its surface for manufacturing a semiconductor device.

In addition, the substrate on which the 1T' MoTe ₂ was formed was additionally manufactured and used as a second substrate including the 1T' MoTe ₂ target layer.

An adhesive tape was attached to a bulk MoTe ₂ mother crystal obtained from high-quality graphene, and then removed to transfer the single crystal flake onto the adhesive tape, thereby forming a mechanically exfoliated 2H MoTe ₂ seed layer.

The 2H MoTe ₂ seed layer was placed so as to face the 1T' MoTe ₂ target layer of the second substrate. Another first preform was placed on the 1T' MoTe ₂ target layer to cover the 2H MoTe ₂ seed layer, and heated at about 500° C. for 1 hour at atmospheric pressure. By this heating, tellurium from the Ni _x Te _y eutectic alloy of the first preform vaporizes to form tellurium vapor, and the tellurium vapor continuously evaporates and is fixed in the space between the first preform and the 1T' MoTe ₂ target layer, thereby phase-changing the 1T' MoTe ₂ of the 1T' MoTe ₂ target layer to form a 2H MoTe ₂ phase-change layer. In the process, a mixed gas including 100 sccm of hydrogen gas (H ₂ ) and 500 sccm of argon gas (Ar) was used as a carrier gas.

According to the present invention, tellurium is uniformly evaporated from the surface of the Ni _x Te _y process alloy and uniformly provided to molybdenum, so that a phase transition from the 1T' MoTe ₂ to the 2H MoTe ₂ can occur uniformly, which is currently limited by the conventional powder-based horizontal chemical vapor synthesis method.

Additionally, a 2H WSe ₂ phase transition layer was formed using the same method and used as a channel layer.

Manufacturing of semiconductor devices

To fabricate the vertical 1T' MoTe ₂ /2H MoTe ₂ heterostructure, large-area growth was performed at various growth temperatures and times for each phase. For example, the formation of 1T' MoTe ₂ was performed at 500 °C for 30 min, and the formation of 2H MoTe ₂ was performed at 700 °C for 60 min.

In order to form the first pattern structure, the Au/1T' MoTe ₂ first pattern structure, as the first pattern structure, a gold (Au) pattern was deposited on the 1T' MoTe ₂ with a thickness of 40 nm using photolithography and an electron beam evaporator (Temescal FC-2000). In order to reduce material damage and interface deterioration during the high-energy deposition process, the deposition rate was reduced to 0.1 Å/s in an ultra-high vacuum (10 ^-9 Torr). Using the gold pattern as a mask layer, a reactive ion etching (RIE) technique of SF ₆ and O ₂ plasma was used to leave the 1T' MoTe ₂ disposed under the gold pattern, and the exposed 1T'-MoTe ₂ was removed to form the first pattern structure. 0.4 M PMMA as the transfer assistant was coated and cured on the first pattern structure, and a single-sided heat-dissipating tape was attached on the transfer assistant.

The above structure was separated from the substrate by applying a mechanical force from the side. Then, it was transferred onto the substrate on which the 2H MoTe ₂ phase was formed. Then, a weight of about 300 g was applied onto the first pattern structure. Then, it was heated at about 150° C. for 5 to 10 minutes. By this heating, van der Waals (vdW) adhesion was formed between the 1T'-MoTe ₂ layer and the 2H-MoTe ₂ layer. In order to prevent the heat budget effect, heat treatment at a temperature higher than 150° C. was not performed during the transfer.

After performing the transcription, the PMMA was removed by immersing it in acetone solution (CMOS grade, J.T. Baker) for about 20 minutes and cleaned using isopropanol alcohol.

This dry transfer method enabled the formation of Au/1T' MoTe ₂ /2H MoTe ₂ junctions, and defined the channel width composed of 2H-MoTe ₂ .

Additionally, in the same manner, instead of gold, platinum and silver were used to form Ag/1T' MoTe ₂ /2H MoTe ₂ junctions and Pt/1T' MoTe ₂ /2H MoTe ₂ junctions. The 1T' MoTe ₂ /2H MoTe ₂ junction without forming a metal layer will be referred to as "pristine 1T'".

Measurement of characteristics of semiconductor devices

Atomic force microscopy images were acquired using an atomic force microscope (Bruker Dimension AFM) in tapping mode. High-resolution scanning transmission electron microscopy images, SAED patterns, and EDS were acquired aberration-corrected (FEI Titan3 G2 60-300) at an acceleration voltage of 200 kV. High-resolution scanning transmission electron microscopy images were acquired using a high-angle annular dark-field (HAADF) detector with half-angles collected in the range of 50.5 to 200 mrad. Noise in the high-resolution scanning transmission electron microscopy images was removed using a Wiener filter. Simulations of multi-slice scanning transmission electron microscopy images were performed using the commercial software TEMPAS (Total Resolution). TEM images and diffraction patterns were acquired using an acceleration voltage of 200 kV (Tecnai G2 F20 X-Twin system). Single-crystal MoTe ₂ thin films were observed by scanning transmission electron microscopy (FEI Verios 460) and electron backscatter diffraction (EBSD) (AMTEK, Inc., Hikari).

The electrical characterization of semiconductor devices (field-effect transistors) was performed using a low-temperature probe station (Lakeshore CRX-4K) equipped with a detector (Keithley 4200-SCS) at temperatures ranging from 138 K to 300 K and a ^high vacuum of 10 -6 torr. The back gate voltage was applied to the semiconductor devices through a 300 nm thick SiO ₂ layer on the silicon layer of the substrate.

The carrier density (n _2D ) in the channel layer was calculated using the following equation: n _2D = C _ox (V _g -V _th )/q, where C _ox is the capacitance of the oxide dielectric. The average device-to-device variation (C _v = σ/μ, where σ is the standard deviation and μ represents the mean value) was estimated to be about 11 ± 5% for the Transfer Length Method (TLM) devices. Inhomogeneities of the two-dimensional material, contact, and dielectric interfaces, or local carrier impurities can cause the device-to-device variation. All statistically estimated values are presented as 'mean ± standard deviation', excluding the fitted values ('mean ± standard error').

Results and Analysis

FIG. 8 is an optical microscope photograph showing a channel layer formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Fig. 8 (a) shows a state in which a 2H MoTe ₂ seed layer is arranged on a 1T' MoTe ₂ target layer, and Fig. 8 (b) shows a state after telluride treatment by heating at 500° C. while providing tellurium. Fig. 8 (c) and (d) show a state after telluride treatment by heating at 700° C. in (a).

Referring to (a) and (b) of FIG. 8, when the telluride treatment was performed by heating to 500°C, an optically distinct shape appeared along the periphery of the 2H MoTe ₂ seed layer, and accordingly, it can be seen that the 1T' MoTe ₂ phase of the target layer was transformed into the 2H MoTe ₂ phase.

Referring to (c) and (d) of Fig. 8, when telluride treatment was performed by heating to 700°C, 2H MoTe ₂ was randomly formed in areas other than the periphery of the seed layer, as indicated by the arrow.

Therefore, it can be seen that when the telluride treatment is performed by heating to 500°C, the 2H MoTe ₂ phase transition layer is formed by transfer only in the peripheral area of the 2H MoTe ₂ seed layer, and the random nucleation of the 2H phase MoTe ₂ is suppressed. Therefore, when grown in a seed growth mode at a temperature of 500°C or lower, it is possible to control the synthesis location of a two-dimensional chalcogenide semiconductor having a 2H phase by accelerating the phase transition from the 1T' phase to the 2H phase. In this way, the growth in which the 2H MoTe ₂ phase preferentially nucleates and grows in the peripheral area of the seed layer and random nucleation and growth are suppressed can be referred to as "abnormal crystal growth."

According to the Raman spectrum analysis results, the Raman spectra of the 2H MoTe ₂ phase change layer after the 2H MoTe 2 seed layer and the 1T' MoTe ₂ target layer were phase changed appeared to have the same shape. Therefore, the 2H MoTe ₂ phase change layer is analyzed to be composed of the 2H MoTe ₂ phase _, similar to the 2H MoTe ₂ seed layer.

According to the inventors' previous study, when no seed layer was used, the minimum temperature for forming the 2H MoTe ₂ phase from the 1T' MoTe ₂ phase was 550°C. However, when the 2H MoTe ₂ seed layer was used, the 2H MoTe ₂ phase can be formed from the 1T' MoTe ₂ phase at a lower temperature of 500°C.

FIG. 9 is a scanning transmission electron microscope photograph of a seed layer and a phase-change layer formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Referring to Fig. 9 (a), an atomic-resolution high-angle annular dark-field (HAADF) image and a selected-area electron diffraction (SAED) pattern are shown for a 2H MoTe ₂ seed layer and a 2H MoTe ₂ phase transition layer after tellurization treatment by heating to 500°C. The 2H-MoTe ₂ seed layer and the 2H MoTe ₂ phase transition layer are analyzed to be composed of single crystals having the same plane. In addition, the 2H MoTe ₂ phase transition layer is analyzed to have been formed by lateral grain growth from the 2H MoTe ₂ seed layer. For reference, since the 2H MoTe ₂ phase seed layer has a larger thickness than the 2H MoTe ₂ phase transition layer, it appears as a brighter area. Analysis of the above-described selective electron diffraction pattern shows that the 2H MoTe ₂ phase transition layer has a set of triple symmetry planes that are well aligned with the single crystal of the 2H MoTe ₂ seed layer and exhibits the same crystal orientation. This suggests that solid-state epitaxial and abnormal grain growth have been performed. The 2H MoTe ₂ phase transition layer can be used as a channel layer.

Referring to Fig. 9(b), as a comparative example, an atomic-resolution high-angle annular dark-field image and a selected area electron diffraction pattern are shown for the 1T' MoTe ₂ target layer and the 2H MoTe ₂ phase transition layer after tellurization treatment by heating at 700°C. The 1T' MoTe ₂ target layer shows a ring formation, and therefore, it is analyzed to be a polycrystal. In addition, the inner image shows the corresponding fast Fourier transform (FFT) pattern showing random arrangement between polymorphs, and therefore, the 1T' MoTe ₂ target layer and the 2H MoTe ₂ phase transition layer are analyzed to have random orientations. It is analyzed that these results are due to the phase transition caused by random nucleation and growth from the 1T' phase to the 2H phase at 700°C as described above.

According to the technical idea of the present invention, the 2H MoTe ₂ has a growth temperature of 500°C or less, and exhibits a minimum thickness in the range of 1 nm to 2 nm. Therefore, the present invention can form a 2H MoTe ₂ thin film with a relatively low growth temperature and a thin thickness. In addition, since the temperature at which the BEOL process of the present invention is possible is 550°C or less, it can be directly integrated with the post-process and performed. On the other hand, when the conventional horizontal chemical vapor deposition (CVD) method was used, it had a growth temperature of 600°C and a minimum thickness of 3 nm or more. When the conventional metalorganic chemical vapor deposition (MOCVD) method was used, it had a growth temperature of 400°C and a minimum thickness of 2 nm or more.

FIG. 10 is a schematic diagram showing the band structures of 1T' MoTe ₂ phase and 2H MoTe ₂ phase formed using a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Referring to Fig. 10, the 1T' MoTe ₂ phase constituting the target layer has a work function (WF) of about 4.51 eV and appears to be a semimetal with no energy band gap.

The 2H MoTe ₂ phase constituting the above-mentioned phase change layer was shown to be a semiconductor with a work function (WF) of approximately 4.44 eV and an energy band gap (E _g ). This is similar to the work function (4.35 to 4.42 eV) of the 2H MoTe ₂ phase formed by conventional mechanical exfoliation.

The Fermi energy level (E _F ) of the above 2H MoTe _{2 phase} is higher than the half position of the energy band gap since the valence band offset (E _F - E _VBM ) is about 0.57 eV, which means that the 2H MoTe ₂ phase is not doped as p-type. The valence band offset showed a relatively low value compared to the 2H MoTe ₂ phase formed by conventional mechanical exfoliation, and therefore, it is predicted to be advantageous for carrier movement such as electrons or holes.

FIG. 11 is an optical microscope photograph of a P-type semiconductor device formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Fig. 11(a) shows a P-type field-effect transistor (FET) array as a semiconductor element formed on a SiO ₂ /Si substrate having a size of 1 x 1 cm ² . Fig. 11(b) shows a transfer length method (TLM) pattern of the semiconductor element. Fig. 11(c) shows 2H MoTe ₂ arranged between Au/1T' MoTe ₂ of the semiconductor element.

Compared with recent studies on van der Waals integration using mechanically exfoliated flakes for recent 2D/2D metal-semiconductor junction field-effect transistors, the present invention combines two different types of synthetic 2D thin films to fabricate field-effect transistor arrays with higher yields. For example, the number of field-effect transistors per chip was increased by about 490%.

FIG. 12 is a scanning transmission electron microscope photograph showing the microstructure of a semiconductor device formed by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Referring to FIG. 12, (a) is a 1T' MoTe ₂ layer, (b) is a 2H-MoTe ₂ layer, (c) is a bonding interface between the 2H-MoTe ₂ layer and the 1T' MoTe ₂ layer, and (d) is a comparative example in which the 3D metal layer and the 2H-MoTe ₂ layer form an interface as a metal contact without the 1T' MoTe ₂ layer. The heterostructure composed of the 2H-MoTe ₂ layer and the 1T' MoTe ₂ layer exhibited a very clean and sharp interface. In addition, according to the EDS analysis, the 2H MoTe ₂ exhibited a Te/Mo of 2.14 at%, and the 1T' MoTe ₂ exhibited a Te/Mo of 2.11 at%, and no tellurium vacancies were found. Therefore, the heterostructure composed of 2H-MoTe ₂ layers and 1T' MoTe ₂ layers has excellent interface quality and no signs of degradation were observed after the device fabrication process.

In forming a metal layer constituting an electrode layer, etc. in a semiconductor device, a two-dimensional semi-metal layer mechanically fixed by a thicker three-dimensional metal can prevent the formation of large defects such as wrinkles or cracks during the transfer process, so that the integration of the three-dimensional metal and the two-dimensional metal can ensure a high-yield process. Accordingly, a semiconductor device array can be manufactured at a high density on a centimeter-scale chip. Here, the two-dimensional metal is 1T' MoTe ₂ , and the three-dimensional metal refers to a metal formed on the 1T' MoTe ₂ , for example, gold (Au).

The manufacturing method according to the present invention has a great advantage over the existing deposition method of three-dimensional metals, such as titanium (Ti) or platinum (Pt), for forming a MoTe ₂ -based metal-semiconductor junction. Platinum (Pt) has a high work function of 5.64 eV and is expected to have high p-type mobility within the Pt contact metal-semiconductor junction, and therefore can be selected as a contact electrode. Titanium (Ti) has a work function of 4.4 eV and therefore can be applied to an n-type contact. However, due to the high-energy process for deposition and the chemical interaction with the two-dimensional MoTe ₂ , defects, such as vacancy defects, alloy formation, and glass layer formation, may occur.

Gold can be the best three-dimensional contact pad for 1T'-MoTe ₂ . In addition, it can prevent the oxidation of the second sublayers during the manufacturing process. In addition, gold can introduce more charges to enhance carrier transport to the semimetal, and prevent the formation of intermetallic compounds AuTe _x or non-stoichiometric MoTe _2-x .

FIG. 13 shows the band structure of a transition metal chalcogenide compound applied in a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Referring to Fig. 13, considering the band structure, MoTe ₂ can operate as a better p-type channel than other group VI two-dimensional transition metal chalcogenides in CMOS. In addition, WSe ₂ can also have similar performance. Typical group VI two-dimensional transition metal chalcogenides, except for MoTe ₂ , have difficulty in suppressing electron transport because their valence band maximum energy (E _VBM ) is higher than 5.0 eV. Therefore, the Schottky barrier height (SBH) of holes increases, which limits the hole conductivity. On the other hand, MoTe ₂ has a high valence band maximum energy (E _VBM ), so the Schottky barrier height (SBH) decreases, which increases the hole conductivity. In particular, the ratio of the thermionic barrier height for holes (Φ _hole ) to thermionic barrier height for electrons (Φ _electron ) of MoTe ₂ is also the smallest among the group VI two-dimensional transition metal chalcogenides. Therefore, _MoTe2 tends to exhibit unipolar p-type, which results in smaller off-state current in p-type MOS, higher efficiency in high-to-low and low-to-high transitions, and thus lower power-delay product per bit in CMOS.

FIGS. 14 to 18 are graphs showing electrical characteristics of a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to an embodiment of the present invention.

Figure 14 is for a van der Waals semimetal contact electrode with a controlled Fermi level.

Figure 14(a) shows the transfer characteristics of field-effect transistors having 2H MoTe ₂ channel layers contacted with van der Waals Au/1T' MoTe ₂ (red), Pt/1T' MoTe ₂ (gold), and Ag/1T' MoTe ₂ (purple). The internal diagram shows that the threshold voltage (V _th ) changes with the addition of a 3D metal to the metal layer in the van der Waals semimetal contact.

Figure 14(b) shows the UV photoelectron spectroscopy (UPS) characteristics of the 1T' MoTe ₂ interface deposited with 3D metals. The spectra of pristine 1T' MoTe ₂ (gray) and 1T' MoTe ₂ deposited with silver (Ag) (purple), gold (Au) (red), and Pt (gold) are shown. The UV photoelectron spectroscopy is for the secondary electron edge region of the 3D metal/1T' MoTe ₂ surface. The work function (WF) can be extracted from the x-intercept of the linear region (solid line), and the kinetic energy (E _k ) represents the difference between the UV photon energy (ca. 21.21 eV, He I radiation) and the binding energy (E _b ).

Figure 14(c) shows X-ray photoelectron spectroscopy (XPS) characteristics of the 1T' MoTe ₂ interface deposited with 3D metals. The spectra of pristine 1T' MoTe ₂ (gray) and 1T' MoTe ₂ deposited with silver (Ag) (purple), gold (Au) (red), and Pt (gold) are shown. The X-ray photoelectron spectroscopy is the normalized XPS spectrum of Te 3d core level obtained at the 3D metal/1T' MoTe ₂ interface. The dashed line represents the binding energy (E _b ) of pristine 1T' MoTe ₂ .

Figure 14(d) shows the I _ds -V _g relationship for the van der Waals contacted Au/1T' MoTe ₂ (red) and 3D Pt (blue) with the 2H MoTe ₂ channel layer in a field-effect transistor at various temperatures. The inner figure shows the on/off current ratio (I _on /I _off ) as a function of temperature.

Figure 14(e) shows the hot electron barrier height (Φ _{B )} for various gate voltages (V g ) for Au/1T' MoTe ₂ (red), 3D Pt (blue), and Ag/1T' MoTe ₂ (purple) in van der Waals contact with the 2H MoTe 2 channel layer in the field-effect transistor. The Schottky barrier height ( _SBH ), which is the hot electron barrier height at the flat band voltage (V _FB ) _, is indicated by the arrow.

Figure 14(f) shows a field effect transistor having a 2H MoTe ₂ channel layer of the present invention and the Schottky barrier height (SBH) and work function are compared with the results of a prior art study. The present invention is shown in color and the results of a prior art study are shown in black. The Fermi level pinning factor (S=dΦ _B /dWF) is shown for the van der Waals semimetal and the three-dimensional contact.

Figure 15(a) shows the band structure showing the formation of the Schottky barrier height (SBH) and the alignment of the Fermi energy level (E _F ) for the 2H MoTe ₂ channel layer and the van der Waals semimetal contact of the field-effect transistor, and (b) shows the band structure showing the alignment of the 2H MoTe ₂ channel layer and the 3D metal contact. E _c and E _v represent the energy levels of the conductor and valence band edges, respectively.

Figure 16(a) shows the average total resistance ( _RW ) as a function of channel length (L) for van der Waals Au/1T' MoTe ₂ and 3D Pt contact electrodes of 2H MoTe ₂ field-effect transistors at a gate voltage (V g ) of ^-100 V (corresponding to an induced carrier density (n _2D ) of ^7.5 to 7.9 × 10 12 cm -2 ). The average is for at least five transfer length method (TLM) sets.

Figure 16 (b) is a graph comparing the contact resistance (R _c ) and on/off current ratio (I _on /I _off ) of the 2H MoTe ₂ field-effect transistor obtained in the present invention with the results of prior research.

Figure 16 (c) is a graph comparing the on/off current ratio (I _on /I _off ) and surface resistance (R _sh ) of the 2H MoTe ₂ field-effect transistor obtained using the transfer length method pattern in the present invention with the results of prior research.

Figure 16 (d) is a graph comparing the sheet resistance (R _sh ) of the 2H MoTe ₂ field-effect transistor obtained in the present invention with the results of a previous study according to the number of 2H MoTe ₂ layers.

FIG. 16(e) is a graph comparing the “intrinsic” field-effect mobility (μ _i ) of the 2H MoTe ₂ field-effect transistor obtained in the present invention with the results of a prior study according to the number of 2H MoTe ₂ layers.

Here, the on-state sheet resistance (R _sh ) was determined using the transfer length method (TLM) and is estimated to be ~44.3 ± 2.3 kΩ/sq at V _g = -100 V. The on-state sheet resistance (R _sh ) is a material-dependent quantity and does not include contributions from device size and contact resistance. From the analysis of the on-state (R _sh ) of 2H MoTe ₂ , the present invention exhibits the lowest sheet resistance (R _sh ) (ca. 44.3 ± 2.3 kΩ/sq), the highest on/off current ratio (I _on /I _off ) (> 2.9 × 10 ⁵ ), and the smallest number of layers (ca. 6 layers) compared to the CVD-grown MoTe ₂ field-effect transistors in prior studies (see FIG. 16 (c) and (d)).

Additionally, using the relationship between the on-state sheet resistance (R _sh ) (ca. 44.3 ± 2.3 kΩ/sq) obtained by the transfer length method (TLM) and the carrier density (n _2D ) induced by the gate voltage (V _g ) (ca. 7 x 10 ¹² cm ^-2 ), the "intrinsic" field-effect mobility (μ _i ) of MoTe ₂ can be calculated as:

The calculated intrinsic field-effect mobility (μ _i ) is about 20.2 ± 1.1 cm ² V ^-1 s ^-1 , indicating intrinsic channel characteristics that are not affected by the contact resistance. It is noteworthy that this value is almost consistent with the averaged two-terminal field-effect mobility (μ _h ) (about 21.0 ± 3.3 cm ² V ^-1 s ^-1 ), which means that the two-dimensional semimetal contact electrode of the present invention has little effect on the terminal field-effect mobility (μ _h ).

Moreover, in the present invention, the intrinsic field-effect mobility (μ _i ) (about 20.2 ± 1.1 cm ² V ^-1 s ^-1 ) acquired by the transfer length method (TLM) exceeds the calculated values for the CVD-grown MoTe ₂ in the previous studies (see Fig. 16(e)). In the previous studies, the ON-state sheet resistance (R _sh ) was extracted from the slope of the transfer length method graph, and the carrier density (n _2D ) was acquired using the parallel capacitance model (n _2D = Cox(V _g - V _th )/q). Considering that all the compared FETs use SiO ₂ dielectric layer as the bottom gate, the intrinsic field-effect mobility (μ _i ) or carrier density (n _2D ) is mainly affected by the material properties (e.g., defect density and doping capacity), and is not significantly affected by the device configuration or dielectric interface.

Figures 17(a), (b), (c) and (d) are the I _ds -V _g curves at various temperatures of 2H MoTe ₂ metal-semiconductor junction field-effect transistors, for van der Waals Au/1T' MoTe ₂ , van der Waals Ag/1T' MoTe ₂ , 3D Ti and 3D Pt contact electrodes, respectively.

Figure 17(e) shows the temperature-dependent two-terminal hole mobility of van der Waals Au/1T' MoTe ₂ (red), 3D Ti (green), and 3D Pt (blue) in contact with the 2H MoTe ₂ channel layer of the field-effect transistor. Temperature dependence of mobility represents the main phonon scattering in field-effect transistors.

Figure 17(f) shows the Arrhenius plots of _the 1T'/2H MoTe ₂ field-effect transistor (red) and the Pt/2H MoTe ₂ (blue) ^{metal -} semiconductor junction field-effect transistors at a carrier density (n _2D ) of about 6 x 10 12 cm -2 (ΔV g is about 1 V). The acquired hot electron barrier heights (Φ _B ) of the 1T'/2H MoTe ₂ field-effect transistor and the Pt/2H MoTe ₂ field-effect transistor are -1.6 meV and 152.2 meV.

Figure 17(g) shows the hot electron barrier height (Φ _B ) obtained at various gate voltages (V _g ) for hole transport in a 3D Ti-contact 2H MoTe ₂ field-effect transistor. At flat band voltage, the hot electron barrier height (Φ _B ) was 188 meV.

Figures 17(h), (i), and (j) show the reproducibility of the Schottky barrier height (SBH) of the van der Waals Au/1T' MoTe ₂ contact electrodes of the 2H MoTe ₂ field-effect transistor in the transfer length method (TLM) pattern.

Fig. 17(h) is a graph of I _ds -V _g of a field-effect transistor measured at various temperatures (from 218 K to 338 K). A more prominent mark in the same color indicates that the measurement was made at a higher temperature.

Figure 17(i) shows the thermoelectron barrier height (Φ _B ) of the 1T'/2H MoTe ₂ field-effect transistor, which exhibits similar behavior regardless of the channel length. The curve shows a linearity of the thermoelectron barrier height (Φ _B ) until the flat band voltage (V _FB ), from which the true Schottky barrier height (SBH) can be extracted.

Figure 17(j) shows the calculated Schottky barrier heights (SBH) of eight different devices, with an average value of 27.4 ± 17.3 meV.

The gray line in Fig. 17(e) represents the ideal phonon scattering model from theoretical calculations, and for the van der Waals Au/1T' contact for 2H MoTe ₂ in this study, the γ value was positive as 0.92 ± 0.24 (mean ± standard error), indicating that the transport was still limited by phonon scattering. The slight deviation from the ideal value (ca. 1.69) could be due to the temperature dependence of the effective Schottky barrier height and/or the interaction between the hole-polarized phonon mode vibration and carrier impurity scattering. On the other hand, the 2H MoTe ₂ FETs with 3D metal contacts (i.e., Pt and Ti) showed a decrease in the field-effect hole mobility (μ _FE ) with decreasing T , indicating that the transport was limited by the contact resistance rather than phonon scattering.

Figure 18 shows the band diagrams based on the hole injection mechanism through the Schottky barrier at the 3D/2D metal-semiconductor junction of Pt/2H MoTe ₂ and the 2D/2D interface of 1T'/2H MoTe ₂ . Here, the p-doping of the channel layer is performed by decreasing the gate voltage (V _g ) or by applying a large gate voltage (V _g ) down to −100 V. For example, (a) and (d) are the cases where V _g > V _FB , (b) and (e) are V _g = V _FB , and (c) and (f) are V _g < V _FB . (1) and (2) represent thermionic emission and tunneling transport, respectively. The work function values of Pt (ca. 5.6 eV) and Au/1T' MoTe ₂ (ca. 5.0 eV) are sufficiently high that the Schottky barrier height (SBH) can be neglected, but the extracted Schottky barrier height (SBH) of the Pt/2H MoTe ₂ metal-semiconductor junction is about 174 meV, which is higher than that of the 1T'/2H _MoTe 2 metal-semiconductor junction, which is about 27.4 meV. This is because of the pinned Fermi level at the interface state due to defects between Pt and 2H MoTe ₂ , such as atomic-level discontinuities, microdefects, or phase aggregation.

Hereinafter, the electrical characteristics of the semiconductor device according to the present invention will be described in detail with reference to FIGS. 14 to 18.

By selecting various three-dimensional metals, such as gold (Au), platinum (Pt), and silver (Ag), as the contact pads of the van der Waals 1T' MoTe ₂ electrode, the transfer characteristics of the 2H MoTe ₂ MSJ field-effect transistor can be controlled (see Fig. 14(a), Fig. 17(a), and Fig. 17(b)). The hole injection efficiency of the metal-semiconductor junction was the highest when van der Waals Au/1T' MoTe ₂ was used, followed by van der Waals Pt/1T' and van der Waals Ag/1T', in that order. This was shown by various current densities at gate voltages (V _g ) below 0 V (see Fig. 14(a)).

Moreover, the threshold voltage (V _th ) in the van der Waals 3D/2D metal system was changed depending on the choice of the 3D metal. When the same fabrication process and channel material are used, the change in the threshold voltage (V _th ) indicates the modulation of carrier injection at the contact due to the reduction of contact resistance (R _c ) and Schottky barrier height (SBH) rather than the doping effect of the channel. This modulation of the contact properties can be attributed to the change in the work function of the 1T' MoTe ₂ van der Waals semimetal depending on the deposited 3D metal, based on ultraviolet photoelectron spectroscopy (UPS) measurements (see Fig. 14(b)). For example, the van der Waals Au/1T' MoTe ₂ and van der Waals Pt/1T' MoTe ₂ surfaces exhibited high work function values of about 5.0 eV and about 5.6 eV, respectively, which are higher than that of the pristine 1T' MoTe ₂ of about 4.5 eV. Such a high work function is advantageous for hole transport.

However, although the work function of platinum (Pt) was increased the most, the performance of the field-effect transistor with van der Waals Pt/1T' MoTe ₂ contact was not significantly improved compared to van der Waals Au/1T' MoTe ₂ (see Fig. 14(a)). This is analyzed to be due to the generation of PtTe _x and the degradation of the van der Waals Pt/1T' MoTe ₂ interface due to non-stoichiometric MoTe _2-x , as shown in the X-ray photoelectron spectroscopy (XPS) analysis (see Fig. 14(c)). From the X-ray photoelectron spectroscopy (XPS) Te 3d scans of van der Waals Ag/1T' and van der Waals Au/1T' MoTe ₂ , it can be seen that the energy shifts to lower values without minimal peak broadening. This indicates the doping of 1T' MoTe ₂ induced by carrier mobility in silver (Ag) or gold (Au), and also implies the absence of interface defect problems. These results indicate that the selection of non-reactive 3D metal pads is very important to achieve the desired performance for van der Waals 2D (semi)metal contacts in 2D field-effect transistors.

In order to further investigate the contact characteristics of the field-effect transistor, electrical measurements were performed at various temperatures (178 K < T < 338 K) in the present invention. Fig. 14(d) shows representative transfer characteristics of the 2H MoTe ₂ field-effect transistor through the contact of a van der Waals semimetal contact with tuned Fermi energy level (i.e., van der Waals Au/1T' MoTe ₂ ) and 3D platinum (Pt), which showed the best p-type performance among the tested 3D metal contacts. As the temperature decreased, the on/off current ratio (I _on /I _off ) increased and reached about 10 ⁷ at 178 K (see the inner drawing of Fig. 14(d) ; the corresponding quasi-logarithmic scale graph is shown in Fig. 16(a) ). This is analyzed to be a result caused by the suppression of thermionic-assisted emission of carriers of the off-state current (I _off ) at low temperatures. The on-state current (I _on ) of the Pt/2H MoTe ₂ field-effect transistor decreased with decreasing temperature, but this decrease was not observed in the 1T' MoTe ₂ contact field-effect transistor. Rather, the on-state current (I _on ) increased significantly with decreasing temperature from 338 K to 218 K (see Fig. 14(d) and Fig. 17(h)).

This increase in channel conductance can be explained by the insulator-to-metal transition (MIT) with temperature. The metallic response of the on-state current (I _on ) of 2H MoTe ₂ at low temperatures implies that the hot electron-assisted transport through a constant barrier height (Φ _B ) at the 1T'/2H junction interface is negligible, and carriers can tunnel across the barrier to exhibit the original transport characteristics. Therefore, the insulator-to-metal transition behavior of the field-effect transistor implies that a true ohmic contact can be realized for holes. In addition, the carriers in the van der Waals Au/1T'/2H MoTe ₂ field-effect transistor follow phonon-limited transport between 218 K and 338 K, and the mobility (μ) exhibits a power-law dependence proportional to T ^-0.92 (see Figure 17(e)). On the other hand, the mobility (μ) of the Pt-contacted field-effect transistor significantly decreased with decreasing temperature, because the high value of the thermionic barrier height (Φ _B ) mainly limited the carrier transport through the three-dimensional metal in the turn-on state. This was due to the relatively high contribution of thermionic emission at the contact interface.

According to the thermionic emission model, the effective thermionic barrier height (Φ _B ) can be calculated by providing additional information on the temperature-dependent I _ds .

In the above equation, A represents the area of the heterojunction, and A* represents the effective Richardson-Boltzmann constant.

From the above equation, the thermoelectron barrier height (Φ _B ) can be derived from the slope of the linear fit to the Arrhenius plot (ln (I _ds /T ^3/2 ) versus 1000/T) (Fig. 17(f)). Compared with the 3D Pt-contacted field-effect transistor, the van der Waals Au/1T'/2H MoTe ₂ field-effect transistor exhibited a positive slope (negligible Φ _B ), indicating that the thermoelectron barrier height (Φ _B ) exists near the threshold voltage (V _th ) when the gate voltage (V _g ) is low. The thermoelectron barrier height (Φ _B ) of the 2H MoTe ₂ field-effect transistor is extracted from the slope and plotted as a function of the gate voltage (V _g ) in Fig. 14(e) and can also be confirmed in Fig. 17(g).

The behavior of the thermoelectron barrier height (Φ _B ) varies with the gate voltage (V _g ), which is determined by the flat band voltage (V _FB ; the point at which the linear relationship between the gate voltage (V _g ) and the thermoelectron barrier height ( _{Φ B} ) that turns on the p-type field-effect transistor by decreasing the gate voltage (V _g ) ends). The flat band voltage (V _FB ) is the point at which the linear relationship between the gate voltage (V _g ) and the thermoelectron barrier height (Φ _B ) that turns on the p-type field-effect transistor ends. This is because band bending after the flat band condition (V _g < V _FB ) induces tunneling transport through a narrow barrier width, and thermoelectron emission through the Schottky barrier height (SBH) occurs together (see Fig. 18). Therefore, the exact thermoelectron barrier height (Φ _B ) at the flat band voltage (V _FB ) is interpreted as the "exact SBH" for the thermoelectron emission.

The hot electron barrier height (Φ _B ) of the Au/1T'/2H MoTe ₂ field-effect transistor integrated with van der Waals, i.e., the hot electron barrier height (Φ _B ) at the flat band voltage (V _FB ), was close to zero. It was about 14 meV, and the average was 27.4 ± 17.3 meV in Fig. 17(j). This is much smaller than that of the three-dimensional metallic Pt/2H MoTe ₂ field-effect transistor, which was about 129 meV. In addition, the band bending caused by additionally inducing the gate voltage (V _g ) caused the negative value of the hot electron barrier height (Φ _B ), which indicates the transparency of the hot electron barrier height (Φ _B ) in the tunneling region when the gate voltage (V _g ) is below 0 V. The Schottky barrier height (SBH) is negligible due to the van der Waals Au/1T' MoTe ₂ contact and is independent of the channel length (L) (see (h) to (j) of Fig. 17). In addition, the acquired near-zero Schottky barrier height (SBH), i.e., the hot electron barrier height (Φ _B ) at the flat band voltage (V _FB ), is the lowest compared to the results of previous studies on 2H MoTe ₂ field-effect transistors.

Ideally, the band alignment between the metal and the semiconductor follows the Schottky–Mott rule for p-type semiconductors, which can determine the Schottky barrier height (SBH) based on the following equation:

Here, "E _g " is the band gap of 2H MoTe ₂ (about 0.89 eV) and "χ" is the electron affinity (about 4.12 eV).

However, the Schottky barrier height (SBH) of the 2H MoTe ₂ field-effect transistor was not effectively controlled by the work function of the 3D metal contact pad. For example, the 2H MoTe ₂ field-effect transistor in this study connected to the 3D Pt metal contact pad exhibited a significant Schottky barrier height (SBH) for holes, which was about 129 meV (blue in (5) of Fig. 14). However, considering the theory above, the ideal SBH of a metal having a work function higher than about 5.01 eV should be zero. In addition, even when using a low-work function metal contact pad, Ti (work function is about 4.4 eV), the interface has a Schottky barrier height (SBH) of about 188 meV, which is low enough to allow hole transport (see (g) of Fig. 17).

The large difference between the Schottky barrier height (SBH) and the work function indicates that the Fermi level pinning (FLP) may be due to the defect-induced gap states, i.e., the defects at the interface of the three-dimensional metal and MoTe ₂ in Fig. 12(d). Therefore, the transferred carrier neutralization induced strong Fermi level pinning (FLP) for various metals, and even S [= d(SBH)/d(WF)], which is an indicator of the strength of Fermi level pinning (FLP), approached 0 for platinum (Pt) contact field-effect transistors or titanium (Ti) contact field-effect transistors. As shown in the blue line in Fig. 14(f), the S is about 0.18.

A similar Fermi level pinning (FLP) phenomenon was also observed in our previous study of MoTe ₂ field-effect transistors using Ti, Cr, Pd, and Au contacts (see Fig. 14(f)), i.e., regardless of the work function of the corresponding metal electrodes, the reported field-effect transistors exhibited a similar Schottky barrier height of 110 ± 85 meV for hole transport.

In contrast, the metal-semiconductor junction interface of the 2H MoTe ₂ FETs using van der Waals 3D-metal/1T' MoTe ₂ contact electrodes had a Schottky barrier height (SBH) close to the Schottky–Mott limit, which was effectively controlled by their different work function values. The experimentally obtained average Schottky barrier height (SBH) of the van der Waals Au/1T' MoTe ₂ contacted 2H MoTe ₂ is about 27.4 ± 17.3 meV (see Figure 17(j)), which is similar to the calculated value of about 10 meV using eq. 2 and the work function of the doped van der Waals 1T' MoTe ₂ contact of about 5.0 eV (see Figure 14(b)).

Additionally, a larger Schottky barrier height (SBH) could be achieved by metallizing with the reactive van der Waals Ag/1T' MoTe ₂ contact at a smaller work function, around 4.8 eV (see Fig. 14(b)), which approached around 207 meV (see Fig. 14(e)). The pinning factor S for the field-effect transistor contacted with the Fermi-level tuned van der Waals 1T' MoTe ₂ metal contact was around 0.99, which was close to the ideal value of 1 for the Schottky–Mott limit, indicating a partially unpinned van der Waals interface.

Figures 15(g) and (h) illustrate the role of the two-dimensional semimetallic 1T' MoTe ₂ electrode in forming an interface without Fermi level pinning (FLP) with a tunable Schottky barrier height (SBH) in terms of band alignment and carrier transport.

Unlike 3D metals (Fig. 15(h)), van der Waals integration at the metal-semiconductor junction interface can avoid the generation of defects at the underlying 2H MoTe ₂ surface, i.e., defect-induced gap states. In addition, since the density of states (DOS) of 2D semimetals is smaller than that of 3D metals, the possibility of generating metal-induced gap states becomes less, thereby eliminating the need for Fermi level pinning (FLP). Most importantly, the small DOS of 1T' MoTe ₂ facilitates the doping level change of the Fermi energy level (E _F ) of the 3D metal adsorbed on the top surface, which is similar to the phenomenon observed in semimetal graphene. In this respect, gold-contacted 1T' MoTe ₂ can have promising large work function values for p-type contacts, and the very clean van der Waals contact with two-dimensional semiconductors allows metal-semiconductor junctions without Fermi level pinning (FLP), which facilitates a scalable technique for producing field-effect transistors with low Schottky barrier height (SBH).

This provides versatility and generality for obtaining FLP-free MOJ interfaces and high-performance p-type 2D MOJFETs. For example, this method can be applied to other 2D semiconductors, WSe ₂ and MOJFETs. In contrast to the n-type characteristics of multilayer WSe ₂ MOJFETs fabricated by evaporation of 3D metal contacts, p-type transport was achieved in WSe ₂ MOJFETs via the interface-defect-free and Fermi-level-tuned van der Waals Au/1T' MoTe ₂ contact electrodes. Therefore, the FLP-free van der Waals contact scheme in this study can be a practical approach for controlling n- and p-type polarities in 2D integrated circuits.

The above 2H MoTe ₂ thin film formed by seed transfer has great potential for use in optical communication devices such as saturable absorbers, modulators, and photodetectors. In particular, a field-effect transistor using the above 2H MoTe ₂ thin film can be applied to a high-performance photodetector in the near-infrared range, which cannot be achieved with other two-dimensional transition metal dichalcogenides having a wider bandgap. The photosensitivity of the transistor can be improved by the photo-gating effect under the near-infrared. In addition, the asymmetric contact barrier formed by using different emission-source electrodes can further improve the rectification ratio. The 1T'-MoTe ₂ with the controlled Fermi level can provide an efficient van der Waals contact for hole transport, and a fast photoresponse can be secured because of less charge trapping at the metal-semiconductor junction interface.

The difference in grain size between the 1T' MoTe ₂ phase and the 2H MoTe ₂ phase is analyzed to be about 1000 times or more. This difference in grain size is analyzed to have occurred through recrystallization and atomic rearrangement during the phase transition from the 1T' MoTe ₂ phase to the 2H MoTe ₂ phase during growth. For example, some of the junctions between the 1T' MoTe ₂ phase and the 2H MoTe ₂ phase share an atomic orientation with the [2-1-10] _2H //[020] _1T' interface, which may be the energetically most favorable interface for the phase transition. However, not all in-plane junctions of the 1T' MoTe ₂ phase and the 2H MoTe ₂ phase exhibit similar orientations.

It is implied that the growth mode of 2H MoTe ₂ phase according to the present invention can help to overcome the energy barrier of arranging random crystallographic orientation of polycrystals, resulting in grain growth of 2H-MoTe ₂ . This can be generally referred to as "abnormal grain growth", in contrast to "normal grain growth" where the formation of single crystals exhibits a relatively uniform grain size distribution.

Previous studies on MoTe ₂ synthesis have shown that the amount of tellurium is an important factor in determining the MoTe ₂ phase during growth. When a large amount of tellurium is present, the 2H MoTe ₂ phase is thermodynamically stable. However, a lack of tellurium leads to the formation of nonstoichiometric MoTe _2-x , which can lead to the formation of metastable 1T' MoTe ₂ phase.

The tellurium-limited growth method according to the present invention can promote uniform growth and abnormal grain growth of 2H MoTe ₂ phase across the wafer by providing a constant and significant amount of tellurium vapor flow to the molybdenum precursor. This is in contrast to tellurium sources using powder-based horizontal CVD in which tellurium is supplied non-uniformly horizontally, which inevitably leads to a compositional gradient across the substrate and limits growth scaling.

According to the technical idea of the present invention, phase-controlled growth and position-controlled growth of 2H MoTe ₂ single crystals and three-dimensional metal-assisted van der Waals (vdW) integration of two polymorphs were implemented to fabricate large-area high-performance p-type metal-semiconductor junction field-effect transistor (MSJ FET) arrays.

An atmosphere sufficiently supplying tellurium promoted the synthesis of high-quality _MoTe2 and enabled the phase transition from 1T' _MoTe2 to 2H _MoTe2 . Here, the 2H _MoTe2 single-crystal domain was able to cover a 4-inch _SiO2 /Si wafer through abnormal grain growth. This growth technique could be extended to form large-sized two-layer _MoTe2 thin films of about 20 mm without noticeable microcavities or impurities. This was the thinnest film achievable using CVD mode with a size of several meters. In addition, the energetically favorable spatial arrangement of the 2H _MoTe2 seed layer enabled the lateral solid-state epitaxy of single-crystal 2H _MoTe2 patterns, which enabled the controllable crystal orientation of the two-dimensional semiconductor on all amorphous substrates at a low temperature of about 500°C.

Furthermore, high-performance van der Waals (vdW) integrated MOSFET arrays were fabricated via standard photolithography patterning and transfer of the two-dimensional 1T' MoTe ₂ structure onto which the three-dimensional metal was deposited. Compared with the conventional ones, the single-crystal 2H MoTe ₂ MOSFETs in the present invention exhibited better performance in terms of the on-state current ratio (I _on /I _off ) of about 1.3 x 10 ⁵ and μ _h of about 29.5 cm ² V ^-1 s ^-1 . The considerably high on-state conductivity (i.e., I _on is about 7.8 μA μm ^-1 ) is attributed to the high crystallinity of MoTe ₂ , i.e., the absence of oxides, metallic impurities, and amorphous or non-stoichiometric structures.

Furthermore, the formation of an ultraclean and atomically precise interface between the 1T' MoTe ₂ and 2H MoTe ₂ prevented the formation of gap states and formed an interface without Fermi level pinning (FLP). Through this, the height of the thermionic emission barrier can be controlled based on the electronic states of various 3D metals on the 2D semimetal. For example, the metallization of the 1T' MoTe ₂ semimetal with gold provided a high work function value of the van der Waals metal electrode, about 5.0 eV, and significantly suppressed the barrier height for hole transport at the contact interface, that is, about 14 meV at the flat band voltage (V _FB ).

Considering the relative ease of formation of n-type two-dimensional transistors, the present invention represents a significant advance toward the scalable fabrication of p-type two-dimensional transistors with enhanced hole mobility. For example, two-dimensional semiconductors are vulnerable to external n-type doping by chalcogen vacancies and dielectric layers, but the present approach may help to avoid this.

The synthesis of p-type two-dimensional selenide and telluride often requires a high growth temperature of about 700°C or higher. This is because selenium (Se) and tellurium (Te) have lower vapor pressures than sulfur (S). Accordingly, they can deteriorate the quality of two-dimensional channels and form chalcogen vacancies due to heat. The vacancies of selenium (Se) and tellurium (Te) are considered as n-type dopants in two-dimensional chalcogenides, and can cause Fermi level pinning (FLP) near the conduction band when two-dimensional semiconductors come into contact with metal electrodes. In addition, widely used dielectric layers such as silicon oxide (SiO ₂ ) and aluminum oxide (AlO _x ) can cause n-doping of the two-dimensional active layer. In this respect, the present invention can prevent undesired n-type doping effects by growing high-quality two-dimensional single crystal semiconductors on random amorphous substrates at a low temperature of about 500°C.

In addition, conventional p-type high work function 3D metal electrodes, for example, Au, Pt, and Pd, have high melting points of 1064°C to 1768°C, which require high energy deposition processes, which may damage the 2D metal-semiconductor junction interface and increase the contact resistance (R _c ). This is in contrast to indium (In) or bismuth (Bi) for n-type ohmic metal contacts of MoS ₂ , which have low melting points of 157°C to 271°C, which create a defect-free contact interface.

Therefore, the attempt to fabricate on-chip ultra-high quality, ultra-clean van der Waals metal semiconductor junction transistor arrays of the present invention is significant in implementing a minimum contact barrier for improved p-type mobility. The significance of the present invention is that it has a low contact resistance (R _c ) of about 0.7 kΩ μm between the two-dimensional semiconductor and the two-dimensional semimetal. Here, the contact resistance (R _c ) is obtained by excluding the contact resistance (R _c ) of the three-dimensional metal/two-dimensional semimetal. The contact resistance (R _c ) is the lowest value in p-type two-dimensional transistors with less than 10 layers based on 2H-MoTe ₂ and WSe ₂ . Therefore, by combining material synthesis, device fabrication and interface engineering, the present invention has significant potential to expand the scope of two-dimensional electronic device applications.

It will be apparent to a person skilled in the art that the technical idea of the present invention described above is not limited to the above-described embodiments and the attached drawings, and that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical idea of the present invention.

Claims (20)

A step of providing a first substrate;
A step of simultaneously forming first and second channel pattern layers including a first phase transition metal chalcogen compound on the first substrate;
A step of forming a first electrode layer including a second phase transition metal chalcogen compound on the first channel pattern layer and exhibiting a first work function; and
A step of forming a second electrode layer including a second phase transition metal chalcogen compound on the second channel pattern layer and exhibiting a second work function different from the first work function,
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 1,
The step of forming the first electrode layer is:
A step of providing a second substrate having a first layer formed on a surface thereof, the first layer comprising a second phase transition metal chalcogenide compound including a second transition metal, and having a first region and a second region;
A step of forming a first metal pattern layer on the first region of the first layer;
A step of forming a first pattern structure by removing the second region of the first layer exposed by the first metal pattern layer using the first metal pattern layer as a mask layer;
a step of separating the first pattern structure from the second substrate; and
A step of forming the first electrode layer by transferring the first pattern structure onto the first channel pattern layer of the first substrate,
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 2,
The step of forming the second electrode layer is:
A step of providing a third substrate having a first layer formed on a surface thereof, the first layer comprising a second phase transition metal chalcogenide compound including a second transition metal, and having a first region and a second region;
A step of forming a second metal pattern layer on the first region of the first layer;
A step of forming a second pattern structure by removing the second region of the first layer exposed by the second metal pattern layer using the second metal pattern layer as a mask layer;
a step of separating the second pattern structure from the third substrate; and
A step of forming the second electrode layer by transferring the second pattern structure onto the second channel pattern layer of the first substrate,
The first electrode layer and the second electrode layer have different work functions.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 2,
The step of separating the first pattern structure is:
A step of forming a transfer assistant to cover the first pattern structure on the second substrate;
a step of attaching an adhesive on the above-mentioned transfer assistant; and
A step of separating the transfer assistant containing the first pattern structure from the second substrate using the adhesive,
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 2,
The step of forming the first electrode layer is:
A step of placing a transfer assistant receiving the first pattern structure on the first channel pattern layer of the first substrate; and
A step of removing the transfer assistant so that the first pattern structure remains on the first channel pattern layer,
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 5,
After performing the step of placing the above warrior auxiliary body,
By heating to a temperature in the range of 100°C to 200°C, the transition metal chalcogen compound of the first phase of the first channel pattern layer and the transition metal chalcogen compound of the second phase of the first pattern structure form a van der Waals bond.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 1,
The step of simultaneously forming the first and second channel pattern layers is:
A step of forming a target layer on which a second phase transition metal chalcogenide compound including a first transition metal is formed on the first substrate;
A step of providing a seed layer on which a first phase transition metal chalcogen compound including the first transition metal is formed;
A step of disposing the seed layer on at least a portion of the target layer;
A step of providing a chalcogen material to the above target layer;
A step of heating the above chalcogen material;
A step in which the transition metal chalcogen compound of the second phase of the target layer is phase-transformed into the transition metal chalcogen compound of the first phase to form a channel layer as the transition metal chalcogen compound of the first phase of the target layer is transferred as a seed; and
A step of patterning the channel layer to form the first channel pattern layer and the second channel pattern layer.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
The step of providing the above chalcogen material is:
A step of forming a preliminary metal layer including a third transition metal on a surface of a preliminary substrate;
A step of providing the chalcogen material to the preliminary metal layer and forming a compound layer of the third transition metal and the chalcogen material by heating the third transition metal through preliminary chalcogenization; and
A step of providing the compound layer as the chalcogen material is included.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
The step of providing the above chalcogen material is:
The above chalcogen material is provided in a solid state, a liquid state, a gaseous state, or a mixed state thereof.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
The step of providing the above chalcogen material is:
It is made by providing a process alloy of the above chalcogen material and a transition metal.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
The step of heating the above chalcogen material is:
The above chalcogen material is heated and vaporized,
The above-mentioned vaporized chalcogen material is provided to the transition metal chalcogen compound of the first phase of the target layer by a carrier gas composed of an inert gas or a mixed gas of a hydrogen-containing gas and an inert gas.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
In the step of forming the above channel layer,
The phase transition to the first phase transition metal chalcogenide compound is achieved by lateral epitaxial growth from the seed layer.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
In the step of providing the seed layer,
The above seed layer is,
A step of forming a metal layer including the first transition metal on a surface of a substrate using sputtering or electron beam evaporation;
A step of providing a chalcogen material to the metal layer and heating it to a temperature in the range of 600°C to less than 750°C; and
The metal layer is formed by a step of reacting with the chalcogen material to form a chalcogenide-type transition metal chalcogen compound layer of the second phase.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 7,
In the step of providing the seed layer,
The above seed layer is formed by performing mechanical exfoliation from the first phase transition metal chalcogen compound mother crystal.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 1,
The step of simultaneously forming the first and second channel pattern layers is:
A step of forming a metal layer including a first transition metal on the first substrate;
A step of providing a chalcogen material to the above metal layer;
A step of heating the chalcogen material to a first temperature, so that the first transition metal and the chalcogen material react to form a transition metal chalcogen compound of the second phase;
A step of forming a channel layer by heating the second phase transition metal chalcogen compound and the chalcogen material to a second temperature higher than the first temperature, thereby forming a first phase transition metal chalcogen compound from the second phase transition metal chalcogen compound; and
A step of forming the first channel pattern layer and the second channel pattern layer by patterning the channel layer,
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 15,
The above first temperature is in the range of 400°C to less than 600°C,
The second temperature is in the range of 600°C to less than 750°C.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 1,
The above first phase transition metal chalcogen compound has a crystal structure arranged in a 2H phase,
The above second phase transition metal chalcogen compound has a crystal structure arranged in a 1T phase or a 1T' phase.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. In claim 1,
The first transition metal constituting the transition metal chalcogenide compound of the first phase or the second transition metal constituting the transition metal chalcogenide compound of the second phase includes at least one of molybdenum (Mo), tungsten (W), titanium (Ti), vanadium (V), chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), zinc (Zn), yttrium (Y), zirconium (Zr), niobium (Nb), technetium (Tc), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), and cadmium (Cd).
The first chalcogen material constituting the transition metal chalcogen compound of the first phase or the second chalcogen material constituting the transition metal chalcogen compound of the second phase contains at least one of sulfur (S), selenium (Se) and tellurium (Te).
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer. A semiconductor device array based on a transition metal chalcogenide compound manufactured by a method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer according to any one of claims 1 to 18,
One or more first semiconductor elements arranged in a first element region on a first substrate; and
comprising one or more second semiconductor elements arranged in a second element region on a first substrate;
The first semiconductor element and the second semiconductor element have a channel layer including a first phase transition metal chalcogen compound,
The above first semiconductor element and the above second semiconductor element have an electrode layer comprising a lower layer composed of a second phase transition metal chalcogen compound and an upper layer disposed on the lower layer,
The above channel layer and the lower layer form van der Waals bonds,
Since the upper layer contains different metals, the first semiconductor element and the second semiconductor element have different work functions.
An array of semiconductor devices based on transition metal chalcogenide compounds including a work function control electrode layer. Step of providing a substrate;
A step of forming a channel pattern layer including a first phase transition metal chalcogen compound on the substrate;
A step of forming a pattern structure comprising a lower layer including a second phase transition metal chalcogen compound and an upper layer including a metal; and
A step of forming an electrode layer by transferring the pattern structure onto the channel pattern layer is included.
The metal constituting the upper layer is selected to have a target work function.
A method for manufacturing a semiconductor device array based on a transition metal chalcogenide compound including a work function control electrode layer.