KR102784807B1 - Storage device and operation method thereof - Google Patents

Abstract

A method of operating a storage device including a first nonvolatile memory device and a second nonvolatile memory device according to an embodiment of the present invention includes the steps of detecting a sudden power-off, interrupting an operation being performed by the first nonvolatile memory device in response to detecting the sudden power-off, writing interruption information about the interrupted operation to the second nonvolatile memory device, and performing a block management operation for the first nonvolatile memory device based on the interruption information written to the second nonvolatile memory device after power-up.

Description

{STORAGE DEVICE AND OPERATION METHOD THEREOF}

The present invention relates to semiconductor memory, and more specifically, to a storage device and an operating method thereof.

Semiconductor memory is divided into volatile memory devices such as SRAM and DRAM, which lose stored data when power is cut off, and nonvolatile memory devices such as flash memory devices, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when power is cut off.

A mass storage device based on flash memory operates using external power. At this time, if a sudden power off (SPO) occurs while the storage device is operating, the storage device uses a separate auxiliary power source, such as a super capacitor or a tantalum capacitor, to complete the operation being performed by the storage device (e.g., a program operation, an erase operation, etc.). However, since it takes a long time for the storage device to complete the operation being performed, a large-capacity auxiliary power source is required, and this increases the area and cost of the storage device, which is a problem.

An object of the present invention is to provide a storage device capable of responding to sudden power-off using reduced auxiliary power and a method of operating the same.

According to an embodiment of the present invention, a storage device includes a first nonvolatile memory device and a second nonvolatile memory device. A method of operating the storage device includes the steps of detecting a sudden power-off, suspending an operation being performed by the first nonvolatile memory device in response to the detected sudden power-off, writing suspension information about the suspended operation to the second nonvolatile memory device, and performing a block management operation for the first nonvolatile memory device based on the suspension information written to the second nonvolatile memory device upon power-up after the sudden power-off.

According to an embodiment of the present invention, a storage device includes a first nonvolatile memory device configured to store user data, a second nonvolatile memory device configured to store operation information on an operation of the first nonvolatile memory device, and a storage controller configured to, when a sudden power-off occurs, interrupt an operation being performed by the first nonvolatile memory device, write a sudden power-off flag to the second nonvolatile memory device in operation information corresponding to the interrupted operation among the operation information stored in the second nonvolatile memory device, and perform a block management operation for the first nonvolatile memory device based on the sudden power-off flag written to the second nonvolatile memory device at power-up after the sudden power-off.

According to an embodiment of the present invention, a storage device includes a first nonvolatile memory device, a second nonvolatile memory device configured to temporarily store user data to be stored in the first nonvolatile memory device, and a storage controller configured to, when a sudden power-off occurs, stop an operation being performed in the first nonvolatile memory device, write a sudden power-off flag for data not stored in the first nonvolatile memory device among the user data temporarily stored in the second nonvolatile memory device, and, when a power-up occurs after the sudden power-off occurs, migrate the data not stored in the first nonvolatile memory device from the second nonvolatile memory device to the first nonvolatile memory device based on the sudden power-off flag written in the second nonvolatile memory device.

According to the present invention, when a sudden power-off occurs, the storage device can interrupt an operation being performed in a first nonvolatile memory device and write interrupted operation information into a second nonvolatile memory device. In this case, since the power used to write the interrupted operation information into the second nonvolatile memory device is smaller than the power used to complete the operation of the first nonvolatile memory device, the storage device can respond to the sudden power-off using an auxiliary power supply of reduced capacity. Accordingly, a storage device having a reduced cost and a reduced area and an operating method thereof are provided.

FIG. 1 is a block diagram showing a storage system according to an embodiment of the present invention.
Figure 2 is a block diagram exemplarily showing the software layer of the storage system of Figure 1.
Figure 3 is a block diagram exemplarily showing the storage controller of Figure 1.
Figure 4 is a flowchart showing the operation of the storage device of Figure 1.
Figure 5 is a flowchart showing the operation of step S160 of Figure 4.
FIGS. 6A to 6C are drawings for explaining the operation of a storage device according to the flowcharts of FIGS. 4 to 5.
Figures 7a and 7b are drawings for explaining the erasure operation of the pre-verification-then-erase method.
FIGS. 8A and 8B are timing diagrams showing an operation of writing interrupt information into a second nonvolatile memory device.
FIGS. 9, 10a, and 10b are drawings for explaining the operation of a storage device according to an embodiment of the present invention.
FIG. 11 is a block diagram showing a storage system according to an embodiment of the present invention.
FIG. 12 is a block diagram showing a storage system according to an embodiment of the present invention.
Figure 13 is a flowchart showing the operation of the storage device of Figure 12.
Figures 14a to 14c are drawings for explaining operations according to the flowchart of Figure 13.
FIG. 15 is a block diagram showing a storage system according to an embodiment of the present invention.
FIG. 16 is a block diagram showing a storage system according to an embodiment of the present invention.
FIG. 17 is a block diagram exemplarily showing a storage system according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described clearly and in detail so that a person having ordinary skill in the art can easily practice the present invention.

FIG. 1 is a block diagram showing a storage system according to an embodiment of the present invention. Referring to FIG. 1, the storage system (10) may include a host (11) and a storage device (100). The storage system (11) may be a computing system such as a personal computer, a server, a workstation, a laptop, a digital camera, a smart phone, etc. The storage device (100) may be used as a large-capacity storage medium of the storage system (10).

The host (11) can store data in the storage device (100) or read data stored in the storage device (100). In an exemplary embodiment, the host (11) can supply power (PWR) to the storage device (100).

The storage device (100) may include a storage controller (110), a first nonvolatile memory device (120), a second nonvolatile memory device (130), and a power management circuit (PMIC; Power Management Integrated Circuit).

The storage controller (110) can store data in the first nonvolatile memory device (120) or read data stored in the first nonvolatile memory device (120) under the control of the host (11).

The first nonvolatile memory device (120) can operate under the control of the storage controller (110). The second nonvolatile memory device (130) can store various information required for the storage controller (110) to operate.

In an exemplary embodiment, the first nonvolatile memory device (120) may be a NAND flash memory device, and the second nonvolatile memory device (130) may be a MRAM (Magnetic Random Access Memory) device. However, the scope of the present invention is not limited thereto. For example, the first and second nonvolatile memory devices (120, 130) may include various nonvolatile memory memory elements such as flash memory, MRAM, PRAM, RRAM, FRAM, etc. In an exemplary embodiment, the second nonvolatile memory device (130) may have a relatively faster operating speed than the first nonvolatile memory device (120).

The power management circuit (PMIC) can provide power required for the storage device (100) to operate based on power (PWR) from the host (11). For example, the power management circuit (PMIC) can supply power required for each of the storage controller (110), the first nonvolatile memory device (120), and the second nonvolatile memory device (120) to operate.

In an exemplary embodiment, power (PWR) from the host (11) may be suddenly cut off or interrupted. Such a sudden power cut is called a “sudden power off (SPO).” A power management circuit (PMIC) may detect the sudden power off and transmit a sudden power off signal (SPO) (hereinafter, referred to as an “SPO signal”) to the storage controller (110).

The storage controller (110) may, in response to the SPO signal, suspend an operation for the first nonvolatile memory device (120) and store information about the suspended operation as suspension information (SPI) in the second nonvolatile memory device (130). The suspension information (SPI) may include command information and address information about the suspended operation in the first nonvolatile memory device (120).

After a sudden power-off, when the storage device (100) is powered-up (i.e., power supply is resumed), the storage controller (110) can perform various block management operations based on the interruption information (SPI) stored in the second nonvolatile memory device (120). The block management operations based on the interruption information (SPI) after the power-up are described in more detail with reference to the drawings below.

In an exemplary embodiment, a write operation of interrupt information (SPI) to the second nonvolatile memory device (130) may be performed using a separate auxiliary power source (not shown) included in the storage device (100). For example, the storage device (100) may include a separate device (not shown) for providing an auxiliary power source, such as a super capacitor or a tantalum capacitor. When a sudden power-off occurs, a power management circuit (PMIC) may provide the auxiliary power source to the storage controller (110), the first nonvolatile memory device (120), and the second nonvolatile memory device (130). The second nonvolatile memory device (130) may perform the write operation for the interrupt information (SPI) described above using the auxiliary power source.

In an exemplary embodiment, a conventional storage device uses auxiliary power to complete an operation (e.g., a read operation, a program operation, or an erase operation) being performed in a first nonvolatile memory device (120) when a sudden power-off occurs. In this case, since the operation speed of the first nonvolatile memory device (120) is relatively slower than the operation speed of the second nonvolatile memory device (130), a lot of time is consumed to complete the operation being performed. Accordingly, the total amount of auxiliary power required when a sudden power-off occurs increases.

On the other hand, when a sudden power-off occurs, the storage device (100) according to the present invention stops the operation being performed in the first nonvolatile memory device (120) and writes operation information about the stopped operation to the second nonvolatile memory device (130). That is, since only the write operation is performed for the second nonvolatile memory device (130) having a relatively fast operation speed, the storage device (100) according to the present invention can respond to a sudden power-off using a small auxiliary power supply compared to the prior art.

In the above-described embodiment, sudden power-off is described as a case where power (PWR) provided from the host (11) is suddenly cut off, but the scope of the present invention is not limited thereto. For example, power (PWR) provided from the host (11) is maintained constant, but power provided to the storage controller (110), the first nonvolatile memory device (120), or the second nonvolatile memory device (130) may become unstable due to various internal problems of the storage device (100). In this case, the power management circuit (PMIC) may determine that a sudden power-off situation has occurred for a specific device and output an SPO signal.

In the above-described embodiment, the power management circuit (PMIC) has been described as detecting a sudden power-off and outputting a SPO signal, but the scope of the present invention is not limited thereto. For example, each of the storage controller (110), the first nonvolatile memory device (120), and the second nonvolatile memory device (130) may include a power detector or a voltage detector (not shown). The power detector included in each may be configured to detect a sudden power-off situation occurring in each configuration. That is, the power detector included in the storage controller (110) may detect a sudden power-off for power provided to the storage controller (110). Alternatively, the power detector included in the first nonvolatile memory device (120) may detect a sudden power-off for power provided to the first nonvolatile memory device (120). Alternatively, a power detector included in the second nonvolatile memory device (120) can detect sudden power-off of power provided to the second nonvolatile memory device (120).

That is, sudden power-off may refer to sudden power-off for power provided to the storage device (100) or may refer to sudden power-off for each of the storage controller (110), the first nonvolatile memory device (120), and the second nonvolatile memory device (130). For convenience of explanation below, sudden power-off is described as sudden power-off for the storage device (100), but as described above, sudden power-off may refer to sudden power-off for each of the components.

FIG. 2 is a block diagram exemplarily showing a software layer of the storage system of FIG. 1. Referring to FIGS. 1 and 2, the software layer of the user device (100) may include an application (11a), a file system (11b), and a flash translation layer (FTL).

The application (11a) may include various application programs running on the storage system (10) or the host (11). The file system (11b) may organize files or data used by the application (11a). For example, the file system (11b) may manage the storage space of the storage device (100) with a logical address, and may assign a logical address to data to be stored or stored in the storage device (102) and manage it.

In an exemplary embodiment, the file system (12b) may have different forms depending on the operating system (OS) of the storage system (10) or the host (11). For example, the file system (12b) may include FAT (File Allocation Table), FAT32, NTFS (NT File System), HFS (Hierarchical File System), JSF2 (Journaled File System2), XFS, ODS-5 (On-Disk Structure-5), UDF, ZFS, UFS (Unix File System), ext2, ext3, ext4, ReiserFS, Reiser4, ISO 9660, Gnome VFS, BFS, or WinFS. For example, the application (11a) and the file system (11b) may be software layers running on the host (101).

The Flash Translation Layer (FTL) can perform various maintenance operations between the host (11) and the first nonvolatile memory device (120) so that the first nonvolatile memory device (120) can be used efficiently. For example, the Flash Translation Layer (FTL) can perform a translation operation between a logical address and a physical address. The logical address is information managed by the file system (11b), and the physical address is information indicating a physical location where data is stored in the first nonvolatile memory device (120). The Flash Translation Layer (FTL) manages the above-described address translation operation through a mapping table (not shown).

In an exemplary embodiment, the block management operation based on the interrupt information (SPI) described with reference to FIG. 1 may be performed by the flash translation layer (FTL). For example, the flash translation layer (FTL) may update or remap a mapping table based on the interrupt information (SPI), or adjust the GC priority of memory blocks of the first nonvolatile memory device (120).

FIG. 3 is a block diagram exemplarily showing the storage controller of FIG. 1. Referring to FIG. 1 and FIG. 3, the storage controller (110) may include a processor (111), an SRAM (112), an error correction engine (ECC Engine) (113), a nonvolatile memory manager (114), a host interface (115), and a flash interface (116).

The processor (111) can control all operations of the storage controller (110). The SRAM (112) can be used as an operating memory or cache memory of the storage controller (110). In an exemplary embodiment, the flash translation layer (FTL) described with reference to FIG. 2 can be provided in the form of software, and program codes, commands, etc. related to the flash translation layer (FTL) can be stored in the SRAM (112). The flash translation layer (FTL) stored in the SRAM (112) can be executed by the processor (111).

The ECC engine (113) may be configured to correct errors in various data transmitted and received through the storage controller (110). For example, the ECC engine (113) may generate an error correction code for data provided from the host (11). Alternatively, the ECC engine (113) may correct errors based on data and an error correction code provided from the first nonvolatile memory device (120). In an exemplary embodiment, the ECC engine (113) may perform an error correction operation on data stored in the second nonvolatile memory device (130).

The nonvolatile memory manager (114) may be configured to control the second nonvolatile memory device (130). For example, the nonvolatile memory manager (114) may read data stored in the second nonvolatile memory device (130) or write data to the second nonvolatile memory device (130).

The storage controller (110) can communicate with the host (11) via the host interface (115). The host interface (115) can include at least one of various interfaces, such as DDR (Double Data Rate), LPDDR (Low-Power DDR), USB (Universal Serial Bus), MMC (multimedia card), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), SATA (Serial-ATA), PATA (Parallel-ATA), SCSI (small computer small interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), MIPI (Mobile Industry Processor Interface), NVM-e (Nonvolatile Memory-express), UFS (Universal Flash Storage), etc.

The storage controller (110) can communicate with the first nonvolatile memory device (120) via a flash interface (115). The flash interface (115) can include a NAND interface.

FIG. 4 is a flowchart showing the operation of the storage device of FIG. 1. Referring to FIG. 1 and FIG. 4, at step S110, the storage device (100) can detect sudden power-off. For example, the power management circuit (PMIC) can detect the cutoff of power (PWR) provided from the host (11). The power management circuit (PMIC) can provide an SPO signal to the storage controller (110) in response to the sudden power-off detection.

In an exemplary embodiment, as described above, the power management circuit (PMIC) may be configured to detect sudden power-off for each component of the storage device (100), or each component of the storage device (100) may be configured to detect sudden power-off via its own power detector.

At step S120, the storage device (100) may suspend an operation for the first nonvolatile memory device (120). For example, at the time when sudden power-off is detected, the first nonvolatile memory device (120) may be performing an operation, such as a program, a read, or an erase operation. The storage controller (110) may suspend the operation currently being performed by the first nonvolatile memory device (120) (e.g., a program, a read, or an erase operation) in response to the SPO signal. In an exemplary embodiment, the storage controller (110) may provide a separate suspend command to the first nonvolatile memory device (120) to suspend the operation of the first nonvolatile memory device (120).

In step S130, the storage device (100) can write interrupt information (SPI) to the second nonvolatile memory device (130) based on the interrupted operation. For example, the storage controller (110) can write a command corresponding to the interrupted operation and an address corresponding to the interrupted operation as the interrupt information (SPI). That is, when a program operation for a first memory block among a plurality of memory blocks of the first nonvolatile memory device (120) is interrupted, the storage controller (110) can write an address and a program command for the first memory block as the interrupt information (SPI). Hereinafter, for convenience of explanation, a command included in the interrupt information (SPI) is referred to as an “interrupt command,” and an address included in the interrupt information (SPI) is referred to as an “interrupt address.”

After this, at step S140, the storage device (100) can be powered up.

After power-up, at step S150, the storage device (100) can scan the interruption information (SPI) stored in the second nonvolatile memory device (130). For example, the storage controller (110) can read the interruption information (SPI) stored in the second nonvolatile memory device (130) in an initialization operation according to power-up.

At step S160, the storage device (100) can perform a block management operation based on the interrupt information (SPI). For example, the storage controller (110) can perform a block management operation, such as invalid block processing, data migration, or GC priority adjustment for a memory block, based on the interrupt command and interrupt address included in the interrupt information (SPI).

In an exemplary embodiment, when a sudden power-off is detected for the first nonvolatile memory device (120), operations according to the flowchart of FIG. 4 may be performed. In an exemplary embodiment, when a sudden power-off is detected for the second nonvolatile memory device (130) and a sudden power-off is not detected for the first nonvolatile memory device (120), a separate interrupt operation may not be performed, and general operations (e.g., a program operation, a read operation, etc.) for the first nonvolatile memory device (120) may be continuously performed.

FIG. 5 is a flowchart showing the operation of step S160 of FIG. 4. Referring to FIG. 1, FIG. 4, and FIG. 5, the storage device (100) can perform the operation of step S160 after step S150. The operation of step S160 can include the operations of steps S161 to S163.

At step S161, the storage device (100) can determine the type of command. For example, the storage controller (110) can determine whether the interrupt command is a read command (RD), a program command (PGM), or an erase command (ERS).

If the interrupt command is a read command (RD), the storage device (100) may not perform a separate block management operation. For example, as described above, the interrupt command refers to a command corresponding to an operation that has been interrupted in the first nonvolatile memory device (120). If an operation corresponding to the read command (i.e., a read operation) has been interrupted, there will be no modification to data stored in the first nonvolatile memory device (120). That is, if the interrupt command is a read command (RD), since the data stored in the first nonvolatile memory device (120) is not modified, even if the storage device (100) does not perform a separate block management operation, the data stored in the first nonvolatile memory device (120) may be maintained.

If the interrupt command is a program command (PGM), at step S162, the storage device (100) can remap a memory block corresponding to the interrupt address. For example, the storage controller (110) can process a memory block corresponding to the interrupt address as an invalid block, migrate data stored in the memory block processed as an invalid block to another memory block (e.g., a free memory block), and update the mapping table.

As a more detailed example, if a program operation for a first memory block of a first nonvolatile memory device (120) is interrupted, data will not be normally stored in the first memory block. That is, since the reliability of data to be stored in the first memory block is not guaranteed, the storage controller (110) may process the first memory block as an invalid block. However, in order to guarantee the reliability of data pre-stored in the first memory block (i.e., data pre-stored before the interrupted program operation), the data stored in the first memory block processed as an invalid block may be migrated to another memory block (e.g., a free memory block). In this case, the storage controller (110) may map a logical address for data stored in the first memory block to a physical address of the free memory block.

As described above, by processing the first memory block where the program operation is interrupted as an invalid block, migrating the data stored in the first memory block to another free memory block, and mapping the logical address of the migrated data to the physical address of the free memory block, the reliability of the data previously stored in the first memory block can be guaranteed. Hereinafter, for the convenience of explanation, the above-described series of operations is referred to as a "remapping operation on the first memory block." That is, when the interrupt command is a program command, the storage controller (110) can perform a remapping operation on the memory block corresponding to the interrupt address.

If the interrupt command is an erase command (ERS), in step S163, the storage device (100) can adjust the GC priority of the memory block corresponding to the interrupt address. For example, if the interrupt command is an erase command (ERS), the storage controller (110) can process the memory block corresponding to the interrupt address as an invalid block and increase the GC priority of the memory block processed as an invalid block. The storage controller (110) can perform garbage collection according to the GC priority. That is, the storage controller (110) can preferentially select the memory block corresponding to the interrupt address (i.e., the memory block for which the erase operation is interrupted) as the target memory block and perform an erase operation on the target memory block.

Since the memory cells of the memory block in which the erase operation is suspended have a lower threshold voltage than the memory cells of the general memory block (i.e., the memory block in which user data is stored), the memory block in which the erase operation is suspended can be erased somewhat faster than the general memory block. That is, by preferentially selecting the memory block in which the erase operation is suspended as the target memory block, the erase operation for the target memory block is performed quickly, and thus the overall speed of the garbage collection operation is improved.

FIGS. 6A to 6C are drawings for explaining the operation of the storage device according to the flowcharts of FIGS. 4 to 5. For convenience of explanation, it is assumed that the first nonvolatile memory device (120) includes first to sixth memory blocks (BLK1 to BLK6), and the first to sixth memory blocks (BLK1 to BLK6) correspond to first to sixth addresses (ADDR1 to ADDR6), respectively. In addition, it is assumed that the first nonvolatile memory device (120) is performing a read operation, a program operation, and an erase operation on the first to third memory blocks (BLK1 to BLK3), respectively. However, the scope of the present invention is not limited thereto.

Referring to FIG. 6A, a sudden power-off may occur in the storage device (100). A power management circuit (PMIC) may detect the sudden power-off and provide an SPO signal to the storage controller (110). In response to the SPO signal, the storage controller (110) may suspend operations being performed in the first nonvolatile memory device (120) (e.g., a read operation, a program operation, or an erase operation).

Thereafter, the storage controller (110) can write information about the interrupted operations as interrupt information (SPI) to the second nonvolatile memory device (130). The interrupt information (SPI) can include an interrupt command and an interrupt address for the interrupted operations.

For example, as illustrated in FIG. 6A, when a read operation being performed in a first memory block (BLK1) is interrupted, the storage controller (110) can write a first interrupt command (CMD1) indicating a read operation (RD) interrupted in the first memory block (BLK1) and a first interrupt address (ADDR1) corresponding to the first memory block (BLK1) as interrupt information (SPI) to a second nonvolatile memory device (130). Similarly, when the program operation and erase operation being performed in the second and third memory blocks (BLK2, BLK3), respectively, are interrupted, the storage controller (110) can write second and third interrupt commands (CMD2, CMD3) indicating the interrupted program operation (PGM) and erase operation (ERS) in the second and third memory blocks (BLK2, BLK3), respectively, and second and third interrupt addresses (ADDR2, ADDR3) corresponding to the second and third memory blocks (BLK2, BLK3) as interrupt information (SPI) to the second nonvolatile memory device (130).

Thereafter, as shown in FIGS. 6b and 6c, the storage device (100) may be powered up. In this case, the storage controller (110) may perform a block management operation based on the interruption information (SPI) stored in the second nonvolatile memory device (130).

For example, as illustrated in FIG. 6b, the storage controller (110) may perform a remapping operation for a specific memory block based on the interruption information (SPI) stored in the second nonvolatile memory device (120). As a more detailed example, the storage controller (110) may recognize that the program operation (PGM) for the second memory block (BLK2) corresponding to the second interruption address (ADDR2) has been interrupted based on the interruption information (SPI). In this case, the storage controller (110) may perform a remapping operation for the second memory block (BLK2).

That is, as described above, the storage controller (110) can process the second memory block (BLK2) as an invalid block (INV) and migrate data stored in the second memory block (BLK2) to the fifth memory block (BLK5). According to the migration operation described above, the storage controller (110) can remap or update the mapping table by mapping the second logical address (LA2) corresponding to the data stored in the second memory block (BLK2) to the fifth address (ADDR5) of the fifth memory block (BLK5) and processing the second address (ADDR2) of the second memory block (BLK2) as an invalid block (INV).

That is, later, when data corresponding to the second logical address (LA2) is accessed by the host (11), the storage controller (110) can access data stored in the fifth memory block (BLK5) based on the remapped mapping table.

As illustrated in FIG. 6c, the storage controller (110) may adjust the GC priority for a specific memory block based on the interruption information (SPI) stored in the second nonvolatile memory device (120). For example, the storage controller (110) may recognize that the erase operation (ERS) for the third memory block (BLK3) corresponding to the third interruption address (ADDR3) has been interrupted based on the interruption information (SPI) stored in the second nonvolatile memory device (130). In this case, as described above, the storage controller (110) may increase the GC priority for the third memory block (BLK3).

As a more detailed example, as illustrated in FIG. 6c, the sixth memory block (BLK6) may be a free memory block and the second memory block (BLK2) may be an invalid block. The storage controller (110) may determine the GC priority of the sixth memory block (BLK6) as the first priority (#1) and may determine the GC priority of the second memory block (BLK2) as the second priority (#2). In this state, when garbage collection is performed, the storage controller (110) may select the sixth memory block (BLK6) having a high priority as a target memory block and perform an erase operation on the sixth memory block.

In a sudden power-off situation, if an erase operation for a third memory block (BLK3) is interrupted and the storage device (100) is powered up thereafter, the storage controller (110) can recognize that the erase operation for the third memory block (BLK3) is interrupted based on the interruption information (SPI) stored in the second nonvolatile memory device (130). In this case, the storage controller (110) can determine the GC priority of the third memory block (BLK3) as the first priority (#1) and adjust or update the GC priorities for the sixth and second memory blocks (BLK6, BLK2) to the second and third priorities (#2, #3), respectively. In this state, if garbage collection is performed, the storage controller (110) can select the third memory memory block (BLK3) having the highest GC priority as a target memory block and perform an erase operation for the selected target memory block.

In an exemplary embodiment, the GC priority for a memory block treated as an invalid block may be additionally adjusted according to the P/E cycle of the memory block treated as an invalid block. For example, the storage controller (110) may perform wear-leveling on a plurality of memory blocks of the first nonvolatile memory device (120). That is, the storage controller (110) may make the GC priority of a memory block having a first P/E cycle higher than the GC priority of a memory block having a second P/E cycle greater than the first P/E cycle, and accordingly, during garbage collection, the memory block having the first P/E cycle may be first selected as a target memory block. In this case, if the memory block having the second P/E cycle is an erase stop memory block, the storage controller (110) may adjust the GC priority so that the memory block having the second P/E cycle is first selected as the target memory block. However, if the difference between the second P/E cycle and the first P/E cycle is greater than or equal to a reference value (i.e., if the second P/E cycle is greater than or equal to the reference value than the first P/E cycle), the storage controller (110) may adjust the GC priority so that a memory block having the first P/E cycle is first selected as a target memory block in order to manage the wear of the memory blocks.

As described above, in a sudden power-off situation, the storage device (100) can suspend the operation for the first nonvolatile memory device (120) and write information about the suspended operation as suspend information (SPI) to the second nonvolatile memory device (130). When the storage device (100) is powered-up thereafter, the remapping operation or the GC priority adjustment operation for the first nonvolatile memory device (120) can be performed based on the suspend information (SPI) stored in the second nonvolatile memory device (130).

FIGS. 7A and 7B are drawings for explaining an erase operation of a pre-verify-then-erase method. Referring to FIGS. 1, 7A, and 7B, as illustrated in FIG. 7A, each of the memory cells of a normal memory block among a plurality of memory blocks included in a first nonvolatile memory device (120) may have an erase state (E) and one of the first to fifteenth program states (P1 to P15). By performing a first erase operation (1st ERS) on the normal memory block, the memory cells of the normal memory block may have the erase state (E). For example, the storage device (100) may perform an erase operation on the normal memory block by performing a first erase operation (1st ERS) including a plurality of erase loops (EL1 to ELn), as illustrated in FIG. 7B. Each of the plurality of erase loops (EL1 to ELn) may include a step of applying an erase voltage to lower a threshold voltage of memory cells; and a step of applying an erase verification voltage (Vvfy_e) to verify whether the memory cells have been normally erased.

On the other hand, the memory cells of the memory block in which the erase operation is stopped (for example, the third memory block (BLK3) of FIG. 6c) (for convenience of explanation, referred to as an "erase-stop memory block") may have a threshold voltage distribution as illustrated in FIG. 7a. At this time, the upper limit value (Vth2) of the threshold voltage distribution of the memory cells of the erase-stop memory block may be lower than the upper limit value (Vth1) of the threshold voltage distribution of the memory cells of the normal memory block. In this case, by performing a second erase operation (2nd ERS) on the erase-stop memory block, the memory cells of the erase-stop memory block may have an erase state (E). For example, the storage device (100) may perform the second erase operation (2nd ERS) including an initial verification period (Int. VFY) and a plurality of erase loops (EL1 to ELk), as illustrated in FIG. 7b.

The initial verification interval (Int. VFY) may be a interval for detecting an upper limit value (i.e., Vth2) of a threshold voltage distribution of memory cells of an erase-stop memory block by applying multiple verification voltages to the erase-stop memory block. Depending on the result of the initial verification interval (Int. VFY), the storage device (100) may perform multiple erase loops (EL1 to ELk). At this time, the application time (Ters2) of the erase voltage applied in the multiple erase loops (EL1 to ELk), the number of the multiple erase loops (EL1 to ELk), and the size of the initial erase voltage (Vers2) may be determined based on the result of the initial verification interval (Int. VFY). For example, as the size of the upper limit value (Vth2) increases based on the result of the initial verification interval (Int. VFY), the application time (Ters2) of the erase voltage applied in the multiple erase loops (EL1 to ELk), the number of the multiple erase loops (EL1 to ELk), or the size of the initial erase voltage (Vers2) may increase.

In an exemplary embodiment, the application time (Ters2) of the erase voltage applied in the plurality of erase loops (EL1 to ELk), the number of the plurality of erase loops (EL1 to ELk), or the size of the initial erase voltage (Vers2) of the second erase operation (2nd ERS) may be smaller than the application time (Ters1) of the erase voltage applied in the plurality of erase loops (EL1 to ELn) of the second erase operation (1st ERS), the number of the plurality of erase loops (EL1 to ELn), or the size of the initial erase voltage (Vers1). That is, the execution time for the second erase operation (2nd ERS) may be shorter than the execution time for the first erase operation (1st ERS).

As described above, the storage controller (110) can perform different erase operations on the general memory block and the erase stop memory block, respectively. For example, the storage controller (110) can perform a first erase operation (1st ERS) on the general memory block and a second erase operation (2nd ERS) on the erase stop memory block. As described above, since the second erase operation (2nd ERS) has a shorter execution time than the first erase operation (1st ERS), the erase stop memory block is first selected as the target memory block and the second erase operation (2nd ERS) is performed, thereby reducing the overall garbage collection execution time.

FIGS. 8A and 8B are timing diagrams showing an operation of writing interrupt information to a second nonvolatile memory device. The timing diagrams shown in FIGS. 8A and 8B are exemplary timing diagrams for explaining the operation of the second nonvolatile memory device, and the scope of the present invention is not limited thereto. For example, the second nonvolatile memory device (130) may be configured to communicate with the storage controller (110) based on any one of various interfaces.

Referring to FIGS. 1, 3, 8A, and 8B, the second nonvolatile memory device (130) may operate in response to signals received from the nonvolatile memory manager (114). For example, as illustrated in FIG. 8A, the second nonvolatile memory device (130) may receive addresses (AD1 to AD4) and data (DT1 to DT4) from the nonvolatile memory manager (114) of the storage controller (110) in synchronization with a clock signal (CLK) during an active period (i.e., a logic low period) of a chip select signal (CS) and a write enable signal (WEN). The second nonvolatile memory device (130) may write the received data (DT1 to DT4) into areas corresponding to the received addresses (AD1 to AD4).

As illustrated in FIG. 8b, when a sudden power-off (SPO) occurs, the storage controller (110) can activate the SPO signal (i.e., lower the SPO signal to logic low) and, after a predetermined period of time has elapsed, provide a specific address (AD_pd) and interruption information (SPI) to the second nonvolatile memory device (130). The second nonvolatile memory device (130) can write the interruption information (SPI) to an area corresponding to the received specific address (AD_pd) in response to the SPO signal.

In an exemplary embodiment, the second nonvolatile memory device (130) may perform an operation of writing the interruption information (SPI) after a predetermined time (e.g., several cycles of the clock signal (CLK)) has elapsed from the time when the SPO signal is activated. In an exemplary embodiment, the specific address (AD_pd) may be an address corresponding to an area predetermined to write the interruption information (SPI) among the storage areas of the second nonvolatile memory device (130). In an exemplary embodiment, the second nonvolatile memory device (130) may operate in a burst mode in order to write the interruption information (SPI).

It will be understood that the operation of the second nonvolatile memory device (130) described above is exemplary, and the operation of the second nonvolatile memory device (130) may be variously modified without departing from the technical spirit of the present invention.

FIGS. 9, 10A, and 10B are diagrams for explaining the operation of a storage device according to an embodiment of the present invention. Referring to FIGS. 9, 10A, and 10B, in step S205, the storage device (200) may write operation information for the first nonvolatile memory device (220) to the second nonvolatile memory device (230) and manage it. For example, as illustrated in FIG. 10A, the storage device (200) may be performing a read operation (RD) for a first memory block (BLK1) of the first nonvolatile memory device (220), a program operation (PGM) for a second memory block (BLK2), an erase operation (ERS) for a third memory block (BLK3), and a program operation (PGM4) for a fourth memory block (BLK4). At this time, the storage device (200) can manage information about the operation being performed in the first nonvolatile memory device (220) by writing it as operation information into the second nonvolatile memory device (230).

The operation information stored in the second nonvolatile memory device (230) may include command information and corresponding address information for an operation being performed in the first nonvolatile memory device (220). In an exemplary embodiment, the operation information stored in the second nonvolatile memory device (230) may be a command queue for the first nonvolatile memory device (220) managed by the storage controller (210) or separately managed management information.

Thereafter, the storage device (200) can perform the operations of steps S210 and S220. The operations of steps S210 and S220 (i.e., sudden power-off detection and operation suspension of the first nonvolatile memory device) can be performed. The operations of steps S210 and S220 are similar to the operations of steps S110 and S120 of FIG. 4, and therefore, a detailed description thereof is omitted.

At step S230, the storage device (200) can write an SPO flag to the operation information corresponding to the suspended operation. For example, as illustrated in FIG. 10b, the storage controller (210) can suspend the operation being performed in the first nonvolatile memory device (220) in response to the SPO signal. At this time, the program operation (PGM) for the fourth memory block (BLK4) may be completed at the time the SPO signal is received, and the read operation (RD), the program operation (PGM), and the erase operation (ERS) being performed in the first to third memory blocks (BLK1 to BLK3) may be suspended.

The storage controller (210) may write an SPO flag to the operation information corresponding to the interrupted operation. For example, if a read operation (RD), a program operation (PGM), and an erase operation (ERS) being performed in the first to third memory blocks (BLK1 to BLK3) are interrupted, an SPO flag may be written to the operation information (i.e., CMD1/ADDR1, CMD2/ADDR2, CMD3/ADDR3) corresponding to the first to third memory blocks (BLK1 to BLK3) in the operation information stored in the second nonvolatile memory device (230). Since the program operation (PGM) for the fourth memory block (BLK4) is completed, a separate SPO flag may not be written to the operation information (CMD4/ADD4) corresponding to the fourth memory block (BLK4).

That is, the storage controller (210) stores and manages operation information (i.e., commands and addresses) regarding an operation being performed in the first nonvolatile memory device (220) in the second nonvolatile memory device (230), and when sudden power-off occurs, can write an SPO flag to the operation information corresponding to the operation stopped in the first nonvolatile memory device (220).

Subsequently, at step S240, the storage device (200) can be powered up.

At step S250, the storage device (200) can scan the SPO flag in the operation information stored in the second nonvolatile memory device (230). For example, the storage controller (210) can recognize an operation that has been interrupted in the first nonvolatile memory device (220) at the time of sudden power-off by scanning the SPO flag in the operation information stored in the second nonvolatile memory device (230).

Thereafter, at step S260, the storage device (200) can perform a block management operation based on the scanned SPO flag. For example, as described above, the storage controller (200) can recognize an operation interrupted in the first nonvolatile memory device (220) at the time of sudden power-off by scanning the SPO flag in the operation information stored in the second nonvolatile memory device (230). The storage controller (210) can perform a block management operation, such as a remapping operation or a GC priority adjustment operation described with reference to FIGS. 1 to 7B, based on the interrupted operation. Since the block management operation has been described with reference to the above drawings, a detailed description thereof will be omitted.

As described above, the storage device (200) can store and manage operation information about an operation being performed in the first nonvolatile memory device (220) in the second nonvolatile memory device (230). At this time, when a sudden power-off occurs, the storage device (200) can stop the operation being performed in the first nonvolatile memory device (220) and write an SPO flag in the operation information corresponding to the stopped operation in the second nonvolatile memory device (230). Therefore, when a sudden power-off occurs, the storage device (200) only needs to write an SPO flag in the second nonvolatile memory device (230) without having to complete the operation for the first nonvolatile memory device (220), and thus can respond to a sudden power-off using a small-capacity auxiliary power supply. In addition, when powering up after a sudden power-off, the storage device performs block management operations based on the operation information and SPO flag stored in the second nonvolatile memory device (230), so the reliability of data stored in the first nonvolatile memory device (220) can be guaranteed.

FIG. 11 is a block diagram showing a storage system according to an embodiment of the present invention. Referring to FIG. 11, the storage system (30) may include a host (31) and a storage device (300). The storage device (300) may include a storage controller (310), a first nonvolatile memory device (320), a second nonvolatile memory device (330), a power management circuit (PMIC), and a temperature sensor (340). Since the host (31), the storage device (300), the storage controller (310), the first nonvolatile memory device (320), the second nonvolatile memory device (330), and the power management circuit (PMIC) have been described above, a detailed description thereof will be omitted.

The temperature sensor (340) can detect the temperature of the storage device (300) and provide temperature information (TEMP) about the detected temperature to the storage controller (310). The storage controller (310) can be configured to control the operation of the second nonvolatile memory device (330) based on the temperature information (TEMP). For example, the second nonvolatile memory device (330) can adjust the number of rewrites for the second nonvolatile memory device (230) according to the temperature of the storage device (300). In an exemplary embodiment, the storage controller (310) can write the temperature information (TEMP) to the second nonvolatile memory device (330) when a sudden power-off occurs.

FIG. 12 is a block diagram showing a storage system according to an embodiment of the present invention. Referring to FIG. 12, the storage system (40) may include a host (41) and a storage device (400). The storage device (400) may include a storage controller (410), a first nonvolatile memory device (420), a second nonvolatile memory device (430), and a power management circuit (PMIC). Since the host (41), the storage device (400), the first nonvolatile memory device (420), and the power management circuit (PMIC) have been described above, a detailed description thereof will be omitted.

The second nonvolatile memory device (430) of FIG. 12 may be used as a data buffer of the storage device (400). For example, user data (UD) received from the host (41) may be stored in the second nonvolatile memory device (430), and the user data (UD) stored in the second nonvolatile memory device (430) may be selectively moved to the first nonvolatile memory device (420). Alternatively, the second nonvolatile memory device (430) may be configured to store user data (UD) read from the first nonvolatile memory device (420) and provide the stored user data (UD) to the host (41).

The storage controller (410) may, in response to an SPO signal from a power management circuit (PMIC), suspend an operation for the first nonvolatile memory device (420) and write an SPO flag for user data (UD) to be provided from the second nonvolatile memory device (430) to the first nonvolatile memory device (420). In an exemplary embodiment, the user data (UD) to be provided to the first nonvolatile memory device (420) may refer to user data not stored in the first nonvolatile memory device (420) or user data corresponding to a program operation that has been suspended in the first nonvolatile memory device (420).

After a sudden power-off, when the storage device (400) is powered-up, the storage controller (410) can migrate the user data (UD) from the second nonvolatile memory device (430) to the first nonvolatile memory device (420) based on the user data (UD) stored in the second nonvolatile memory device (430) and the SPO flag.

As described above, when a sudden power-off occurs, the storage device (400) can stop the operation for the first nonvolatile memory device (420) and write an SPO flag for the user data (UD) to be stored in the first nonvolatile memory device (420) to the second nonvolatile memory device (430). That is, when a sudden power-off occurs, the storage device (400) only needs to write an SPO flag to the second nonvolatile memory device (430) without having to complete the operation for the first nonvolatile memory device (420), so that the storage device (400) can respond to a sudden power-off situation using a reduced auxiliary power supply.

FIG. 13 is a flowchart showing the operation of the storage device of FIG. 12. FIGS. 14a to 14c are drawings for explaining the operation according to the flowchart of FIG. 13. Referring to FIGS. 12, 13, 14a, 14b, and 14c, the storage device (400) can perform the operations of steps S405 and S410. The operations of steps S405 and S410 are similar to the operations of steps S110 and S120 of FIG. 4, and therefore, a detailed description thereof is omitted.

At step S420, the storage device (400) can determine whether the interrupted operation in the first nonvolatile memory device (420) is a program operation (PGM). For example, as illustrated in FIG. 14a, the second nonvolatile memory device (430) can store first to third user data (UD1, UD2, UD3) and first to third addresses (ADDR1, ADDR2, ADDR3) corresponding thereto, respectively. The storage controller (410) can read the first to third user data (UD1 to UD3) from the second nonvolatile memory device (430) and program the read first to third user data (UD1 to UD3) into first to third memory blocks (BLK1 to BLK3) corresponding to the first to third addresses (ADDR1 to ADDR3), respectively. The embodiment of the storage device (400) illustrated in FIG. 14a shows a state in which the third user data (UD3) is programmed in the third memory block (BLK3), and the first and second user data (UD1, UD2) are being programmed in the first and second memory blocks (BLK1, BLK2).

In an exemplary embodiment, the ECC engine (413) of the storage controller (410) can correct errors in user data read from the second nonvolatile memory device (430), and the error-corrected user data can be programmed into the first nonvolatile memory device (420).

In the embodiment of the storage device (400) illustrated in FIG. 14a, when a sudden power-off occurs, the storage controller (410) can determine that the interrupted operation in the first nonvolatile memory device (420) is a program operation.

If the interrupted operation is a program operation, at step S425, the storage device (400) can determine whether the ECC operation for data to be programmed into the first nonvolatile memory device (420) is completed. For example, as illustrated in FIG. 14a, the storage controller (410) can read the first user data (UD1) from the second nonvolatile memory device (420), perform an ECC operation on the read first user data, and provide the first user data (UD1') with the corrected error to the first nonvolatile memory device (420). The first nonvolatile memory device (420) can program the first user data (UD1') with the corrected error into the first memory block (BLK1). At this time, a sudden power-off may occur.

That is, if a sudden power-off occurs while the ECC operation on the first user data (UD1) is completed and the first user data (UD1') with the error corrected is being programmed to the first nonvolatile memory device (420) (in other words, if the result of step S425 is "Yes"), then in step S430, the storage device (400) can rewrite the user data being programmed to the second nonvolatile memory device (430).

For example, as illustrated in FIG. 14b, the storage device (400) may write the first user data (UD1') whose error has been corrected into the second nonvolatile memory device (430). In an exemplary embodiment, the storage controller (410) may rewrite the first user data (UD1') whose error has been corrected into the area where the first user data (UD1) is stored or a separate area of the second nonvolatile memory device (430). That is, since the first user data (UD1') whose error has been corrected is rewritten into the second nonvolatile memory device (430), the reliability of the first user data may be improved.

If the result of step S425 is “No”, the storage device (400) may not perform a separate data write operation. For example, as illustrated in FIGS. 14a and 14b, at the time when sudden power-off occurs, the storage controller (410) may not have completed the ECC operation for the second user data (UD2) (i.e., the second user data (UD2) is read from the second nonvolatile memory device (430). In this case, since the second user data (UD2) is stored in the second nonvolatile memory device (430), a separate rewrite operation may not be performed.

Thereafter, at step S435, the storage device (400) may write an SPO flag to the second nonvolatile memory device (420). For example, as illustrated in FIG. 14b, the storage controller (410) may write an SPO flag to user data (UD1, UD2) corresponding to a program operation that was interrupted in the first nonvolatile memory device (420).

At step S440, the storage device (400) can be powered up.

At step S445, the storage device (400) can scan the SPO flag from the second nonvolatile memory device (430). For example, the storage device (400) can read the SPO flag stored in the second nonvolatile memory device (430) in an initialization operation following power-up. The storage device (400) can recognize user data (e.g., UD1', UD2) that is not stored in the first nonvolatile memory device (420) based on the SPO flag read from the second nonvolatile memory device (430).

At step S450, the storage device (400) may migrate user data from the second nonvolatile memory device (430) to the first nonvolatile memory device (420) based on the scanned SPO flag. For example, as illustrated in FIG. 14c, the second nonvolatile memory device (430) may include SPO flags for the first user data (UD1') and the second user data (UD2). The storage controller (410) may read the first user data (UD1') and the second user data (UD2) in which the SPO flags are written, and perform an error correction operation (performed by the ECC engine (413)) on the read first user data (UD1') and the second user data (UD2). The first and second user data (UD1', UD2') in which the errors are corrected may be written to the fifth and sixth memory blocks (BLK5, BLK6), respectively.

In an exemplary embodiment, before the sudden power-off, the first and second user data (UD1, UD2) are user data written to the first and second memory blocks (BLK1, BLK2). However, due to the sudden power-off, the program operation for the first and second memory blocks (BLK1, BLK2) is interrupted, and thus the first and second memory blocks (BLK1, BLK2) may be processed as invalid blocks. Since this invalid block processing operation has been described above, a detailed description thereof is omitted. Accordingly, the storage controller (110) may program the first and second user data (UD1', UD2) to other memory blocks (e.g., BLK5, BLK6) instead of the first and second memory blocks (BLK1, BLK2) processed as invalid blocks. In an exemplary embodiment, as the first and second user data (UD1', UD2) are programmed into different memory blocks (e.g., BLK5, BLK6), mapping information for the first and second user data (UD1', UD2) may be updated. In an exemplary embodiment, the mapping information may be managed by the storage controller (410) or stored in the second nonvolatile memory device (430) together with the first and second user data (UD1', UD2).

As described above, when the second nonvolatile memory device (430) is used as a data buffer of the storage device (400), when a sudden power-off occurs, the storage device (400) can stop the operation for the first nonvolatile memory device (420) and write an SPO flag for user data stored in the second nonvolatile memory device (430) that is not stored in the first nonvolatile memory device (420). When the storage device (400) is powered-up thereafter, the storage device (400) can scan the SPO flag of the second nonvolatile memory device (430) and migrate the user data from the second nonvolatile memory device (430) to the first nonvolatile memory device (420) based on the scanned result.

FIG. 15 is a block diagram showing a storage system according to an embodiment of the present invention. Referring to FIG. 15, the storage system (50) may include a host (51) and a storage device (500). The storage device (500) may include a storage controller (510), a first nonvolatile memory device (520), a second nonvolatile memory device (530), and a power management circuit (PMIC). Since the host (51), the storage device (500), the storage controller (510), the first nonvolatile memory device (520), and the power management circuit (PMIC) have been described above, a detailed description thereof will be omitted.

The second nonvolatile memory device (530) of FIG. 15 may be used as a data buffer of the storage device (500), similarly to what has been described with reference to FIGS. 12 to 14c. That is, the second nonvolatile memory device (530) may be configured to store user data (UD) to be programmed into the first nonvolatile memory device (520) or user data (UD) read from the first nonvolatile memory device (520). In addition, the second nonvolatile memory device (530) of FIG. 15 may be configured to store interruption information (SPI) or operation information for the first nonvolatile memory device (520), as has been described with reference to FIGS. 1 to 11. That is, the second nonvolatile memory device (530) may be used as a data buffer and a management buffer of the storage device (500).

In this case, the storage device (500) may, as described with reference to FIGS. 1 to 11, interrupt an operation being performed in the first nonvolatile memory device (520) when sudden power-off occurs, and write information about the interrupted operation as interruption information into the second nonvolatile memory device (530). In addition, the storage device (500) may, as described with reference to FIGS. 12 to 14c, write an SPO flag to user data corresponding to the interrupted program operation.

FIG. 16 is a block diagram showing a storage system according to an embodiment of the present invention. Referring to FIG. 16, the storage system (60) may include a host (61) and a storage device (600). The storage device (600) may include a storage controller (610), a first nonvolatile memory device (610), a second nonvolatile memory device (640), a power management circuit (PMIC), and a DRAM buffer (640). Since the host (61), the storage device (600), the storage controller (610), the first nonvolatile memory device (620), the second nonvolatile memory device (630), and the power management circuit (PMIC) have been described above, a detailed description thereof will be omitted.

The storage device (600) of FIG. 16 may include a DRAM buffer (640). The DRAM buffer (640) may be used as a data buffer of the storage device (600). That is, the DRAM buffer (640) may be configured to temporarily store user data received from the host (61) or user data read from the first nonvolatile memory device (620). Alternatively, the DRAM buffer (640) may be configured to store various meta information (e.g., a mapping table, FTL, etc.) required for the storage device (600) to operate.

In an exemplary embodiment, when a sudden power-off occurs, the storage controller (640) may suspend the operation of the first nonvolatile memory device (620) based on the method described with reference to FIGS. 1 to 11, and write suspend information (SPI) about the suspended operation to the second nonvolatile memory device (640). At this time, the storage controller (640) may write user data or meta information stored in the DRAM buffer (640) to the second nonvolatile memory device (640).

After a sudden power-off, when the storage device (600) is powered-up, the storage device (600) can perform block management operations based on information stored in the second nonvolatile memory device (640) according to the methods described with reference to FIGS. 1 to 15.

FIG. 17 is a block diagram exemplarily showing a storage system according to an embodiment of the present invention. Referring to FIG. 17, a storage system (1000) may include a host (1100) and a storage device (1200). The storage device (1200) may include a storage controller (1210), a plurality of nonvolatile memory devices (NVM), a plurality of nonvolatile memory controllers (1221 to 122n), a plurality of nonvolatile RAMs (1231 to 123n), a power management circuit (PMIC), and a RAM buffer (1240).

The storage controller (1210) may be configured to control overall operations of the storage device (1200) under the control of the host (1100). Each of a plurality of nonvolatile memory controllers (hereinafter, referred to as “NVM controllers”) (1221 to 122n) may be configured to control a plurality of nonvolatile memories (NVMs) and a plurality of nonvolatile RAMs (1231 to 123n), respectively. In an exemplary embodiment, the storage controller (1210) may communicate with each of the plurality of NVM controllers (1221 to 122n) through a plurality of channels.

In an exemplary embodiment, each of the NVM controllers (1221 to 122n) may control each of the plurality of nonvolatile memory devices (NVM) and each of the plurality of nonvolatile RAMs (1231 to 123n) based on the operating method described with reference to FIGS. 1 to 16. For example, each of the NVM controllers (1221 to 122n) may suspend the operation of the plurality of nonvolatile memory devices (NVM) when a sudden power-off occurs and write suspend information or an SPO flag to the plurality of nonvolatile RAMs (1231 to 123n). Upon power-up, each of the NVM controllers (1221 to 122n) may perform a block management operation or a data migration operation based on the suspend information or the SPO flag from the plurality of nonvolatile RAMs (1231 to 123n).

The RAM buffer (1240) may be configured to store various information required for the storage device (1200) to operate. Alternatively, the RAM buffer (1240) may be used as a data buffer of the storage device (1200).

The power management circuit (PMIC) can provide various powers required for the storage device (1200) to operate based on power from the host (1100). The power management circuit (PMIC) can detect sudden power-off occurring in the storage device (1200).

The above-described contents are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also embodiments that can be simply designed or easily changed. In addition, the present invention will also include technologies that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims described below as well as the equivalents of the claims of this invention.

Claims (20)

A method of operating a storage device including a first nonvolatile memory device, a second nonvolatile memory device, and a storage controller configured to control the first and second nonvolatile memory devices,
Steps to detect sudden power off;
In response to the detected sudden power-off, a step of stopping an operation being performed in the first non-volatile memory device;
A step of writing interruption information for the interrupted operation into the second non-volatile memory device;
Including a step of performing a block management operation for the first nonvolatile memory device based on the interruption information written to the second nonvolatile memory device upon power-up after the sudden power-off;
The above storage device:
An operating method further comprising a power management circuit configured to provide power to the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller, and to detect a sudden power-off for at least one of the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller, and to provide a sudden power-off signal to the storage controller.
In paragraph 1,
The above interruption information is an operation method including an interruption command and an interruption address corresponding to the interrupted operation. In the second paragraph,
The above block management operations include remapping operations and garbage collection (GC) priority adjustment operations.
If the above interrupt command is a program command, the remapping operation for the memory block corresponding to the interrupt address is performed,
An operating method in which the GC priority adjustment operation for the memory block corresponding to the stop address is performed when the above-mentioned stop command is an erase command.
In the third paragraph,
The above remapping operation:
An operation of processing the memory block corresponding to the above interrupt address as an invalid block;
An operation of migrating data stored in the above memory block to another memory block; and
An operating method including an operation of mapping a logical address corresponding to the migrated data with a physical address of the other memory block.
In the third paragraph,
The above GC priority adjustment operation includes an operation of increasing the GC priority of the memory block corresponding to the stop address,
The above method of operation of the above storage device is:
An operating method further comprising the step of performing a garbage collection operation for the first non-volatile memory device based on the GC priority. In paragraph 5,
An operating method wherein the GC priority of the above memory block is further adjusted based on the program and erase cycles of the above memory block. In the second paragraph,
Further comprising a step of performing an erase operation on the first nonvolatile memory device,
If the memory block that is the target of the above erase operation corresponds to the above interrupt address, the memory block is erased based on the pre-verify-then-erase method,
An operation method in which the memory block that is the target of the above erase operation does not correspond to the above interrupt address, wherein the memory block is erased based on a general erase method.
In paragraph 1,
The above sudden power-off is a method of operation for the first non-volatile memory device.
In paragraph 1,
An operating method wherein the operating speed of the second nonvolatile memory device is faster than the operating speed of the first nonvolatile memory device. In paragraph 1,
An operating method wherein the first nonvolatile memory device is a NAND flash memory device and the second nonvolatile memory device is an MRAM (Magnetic Random Access Memory) device. In storage devices,
A first nonvolatile memory device configured to store user data;
A second nonvolatile memory device configured to store operation information regarding the operation of the first nonvolatile memory device;
A storage controller configured to, when a sudden power-off occurs, suspend an operation being performed in the first nonvolatile memory device, write a sudden power-off flag in operation information corresponding to the suspended operation among the operation information stored in the second nonvolatile memory device, and, when powering up after the sudden power-off, perform a block management operation for the first nonvolatile memory device based on the sudden power-off flag written in the second nonvolatile memory device; and
A storage device including a power management circuit configured to provide power to the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller, and to detect a sudden power-off for at least one of the first nonvolatile memory device, the second nonvolatile memory device, and the storage controller, and to provide a sudden power-off signal to the storage controller.
In Article 11,
A storage device wherein the above operation information includes an operation command and an operation address for the operation of the first non-volatile memory device. In Article 12,
The above block management operations include remapping operations and garbage collection (GC) priority adjustment operations.
The above storage controller:
If the operation command corresponding to the sudden power off flag is a program command, the remapping operation is performed on a memory block corresponding to the operation address among a plurality of memory blocks of the first nonvolatile memory device,
A storage device that performs the GC priority adjustment operation for the memory block corresponding to the operation address when the above operation command is an erase command.
In Article 13,
The above remapping operation:
An operation of processing the memory block corresponding to the above operation address as an invalid block;
An operation of migrating data stored in the above memory block to another memory block; and
A storage device including an operation of mapping a logical address corresponding to the migrated data to a physical address of another memory block.
In Article 13,
The above GC priority adjustment operation includes an operation of increasing the GC priority of the memory block corresponding to the operation address,
A storage device wherein the storage controller is further configured to perform a garbage collection operation for the first non-volatile memory device based on the GC priority. In Article 11,
A storage device wherein the operating speed of the second nonvolatile memory device is faster than the operating speed of the first nonvolatile memory device.

delete delete delete delete

Images