KR102788409B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. A semiconductor device comprises a substrate in which a cell region and a contact region disposed on at least one side of the cell region in a first direction are defined, wherein the cell region includes a first cell region and a second cell region adjacent in a second direction perpendicular to the first direction, and the contact region includes a first contact region and a second contact region adjacent in the second direction, a first stack structure disposed on the first cell region and the first contact region, in which first insulating films and first gate electrodes are alternately laminated, and extending in the first direction, a second stack structure disposed on the second cell region and the second contact region, in which second insulating films and second gate electrodes are alternately laminated, and spaced apart from the first stack structure in the second direction and extending in the first direction, an interlayer insulating film disposed on the first and second stack structures, a first through via disposed on the first contact region and penetrating the interlayer insulating film in a third direction perpendicular to the first and second directions, a first gate contact disposed on the first contact region and penetrating the interlayer insulating film in the third direction and connected to the first stack structure, A second gate contact disposed on a second contact region and connected to a second stack structure by penetrating the interlayer insulating film in a third direction, a first electrode separation pattern disposed between the first stack structure and the second stack structure and extending in the first direction, a first channel hole disposed on a first cell region, penetrating the first stack structure in the third direction, and positioned most adjacent to the first contact region, and a second channel hole disposed on a second cell region, penetrating the second stack structure in the third direction, and positioned most adjacent to the second contact region, and spaced apart from the first channel hole in a fourth direction having an acute angle with the first direction.

Description

Semiconductor device

The present invention relates to a semiconductor device.

In order to meet the superior performance and low price demanded by consumers, the integration of semiconductor devices is required to increase. In the case of semiconductor devices, the integration is an important factor in determining the price of the product, so increased integration is particularly required. In the case of two-dimensional or planar semiconductor devices, the integration is mainly determined by the area occupied by the unit memory cell, so it is greatly affected by the level of fine pattern formation technology.

However, because ultra-expensive equipment is required for pattern miniaturization, the integration of two-dimensional semiconductor devices is increasing but still limited. Accordingly, three-dimensional semiconductor memory devices having memory cells arranged three-dimensionally are being proposed.

The problem to be solved by the present invention is to provide a semiconductor device with improved reliability by arranging stud contacts to reflect the misalignment of channel holes in the process of forming an electrode separation pattern, thereby effectively aligning the channel holes and stud contacts.

Another problem to be solved by the present invention is to provide a semiconductor device with improved reliability by effectively aligning gate contacts by arranging gate contacts to reflect misalignment of channel holes in a process of forming an electrode separation pattern.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

Some embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problem include a substrate in which a cell region and a contact region arranged on at least one side of the cell region in a first direction are defined, wherein the cell region includes a first cell region and a second cell region adjacent in a second direction perpendicular to the first direction, and the contact region includes a first contact region and a second contact region adjacent in the second direction, a first stack structure arranged on the first cell region and the first contact region, in which a first insulating film and a first gate electrode are alternately stacked, and extends in the first direction, a second stack structure arranged on the second cell region and the second contact region, in which a second insulating film and a second gate electrode are alternately stacked, and is spaced apart from the first stack structure in the second direction and extends in the first direction, an interlayer insulating film arranged on the first and second stack structures, a first through via arranged on the first contact region and penetrating the interlayer insulating film in a third direction perpendicular to the first and second directions, and a first contact via arranged on the first contact region and penetrating the interlayer insulating film in the third direction. A first gate contact penetrating and connected to the first stack structure, a second gate contact disposed on a second contact region and penetrating the interlayer insulating film in a third direction and connected to the second stack structure, a first electrode separation pattern disposed between the first stack structure and the second stack structure and extending in the first direction, a first channel hole disposed on the first cell region, penetrating the first stack structure in the third direction, and positioned most adjacent to the first contact region, and a second channel hole disposed on the second cell region, penetrating the second stack structure in the third direction, and positioned most adjacent to the second contact region, and spaced apart from the first channel hole in a fourth direction having an acute angle with the first direction.

Some other embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problem include a substrate defining a cell region and a contact region disposed on both sides of the cell region, a first stack structure disposed on the substrate, in which first insulating films and first gate electrodes are alternately stacked, and extending in a first direction, a second stack structure disposed on the substrate, in which second insulating films and second gate electrodes are alternately stacked, and spaced apart from the first stack structure in a second direction perpendicular to the first direction, and extending in the first direction, an interlayer insulating film disposed on the first and second stack structures, a first electrode separation pattern disposed between the first stack structure and the second stack structure, and extending in the first direction, a second electrode separation pattern crossing the first stack structure in the second direction and in contact with the first electrode separation pattern, a first channel hole penetrating the first stack structure in a third direction perpendicular to the first and second directions on the cell region, and being disposed most adjacent to the contact region in the first direction, a first channel hole penetrating the second stack structure in the third direction on the cell region, and spaced apart from the contact region in the first direction. It includes a second channel hole which is arranged most adjacently and spaced apart in a fourth direction having an acute angle with the first direction and the first channel hole, a first gate contact which penetrates the interlayer insulating film in the third direction on the contact area and is connected to the first stack structure, and a second gate contact which penetrates the interlayer insulating film in the third direction on the contact area and is connected to the second stack structure and is spaced apart from the first gate contact in the fourth direction.

Some other embodiments of a semiconductor device according to the technical idea of the present invention for solving the above problem include a substrate defining a cell region and a contact region disposed on both sides of the cell region, a first stack structure disposed on the substrate, in which first insulating films and first gate electrodes are alternately laminated, and extending in a first direction, a second stack structure disposed on the substrate, in which second insulating films and second gate electrodes are alternately laminated, and spaced apart from the first stack structure in a second direction perpendicular to the first direction, and extending in the first direction, an interlayer insulating film disposed on the first and second stack structures, a first electrode separation pattern disposed between the first stack structure and the second stack structure, and extending in the first direction, a second electrode separation pattern crossing the first stack structure in the second direction and in contact with the first electrode separation pattern, a first channel hole penetrating the first stack structure in a third direction perpendicular to the first and second directions on the cell region, and being disposed most adjacent to the contact region in the first direction, a first channel hole penetrating the second stack structure in the third direction on the cell region, and spaced apart from the contact region and the first A first stud contact is disposed most adjacent to the first channel hole in the direction, and is spaced apart in a fourth direction having an acute angle with the first direction, a first stud contact overlapping the first channel hole in the third direction, a second stud contact overlapping the second channel hole in the third direction and spaced apart from the first stud contact in the fourth direction, a first gate contact connecting to the first stack structure by penetrating the interlayer insulating film in the third direction on the contact region, and a second gate contact connecting to the second stack structure by penetrating the interlayer insulating film in the third direction on the contact region, and spaced apart from the first gate contact in the fourth direction.

Other specific details of the present invention are included in the detailed description and drawings.

FIG. 1 is a block diagram illustrating a semiconductor device according to some embodiments of the present invention.
FIG. 2 is a schematic perspective view illustrating a semiconductor device according to some embodiments of the present invention.
FIG. 3 is a circuit diagram illustrating one memory cell block among a plurality of memory cell blocks included in a semiconductor device according to some embodiments of the present invention.
FIG. 4 is a layout diagram illustrating a semiconductor device according to some embodiments of the present invention.
Figure 5 is an enlarged view of the R1 area of Figure 4.
Figure 6 is a cross-sectional view taken along line AA' of Figure 5.
Figure 7 is an enlarged view of the R2 area of Figure 5.
Figure 8 is a cross-sectional view taken along line BB' of Figure 5.
Figure 9 is a cross-sectional view taken along line CC' of Figure 5.
Fig. 10 is a cross-sectional view taken along line DD' of Fig. 4.
FIG. 11 is a layout diagram illustrating a semiconductor device according to some other embodiments of the present invention.
FIGS. 12 and 13 are cross-sectional views illustrating semiconductor devices according to still other embodiments of the present invention.
FIGS. 14 and 15 are cross-sectional views illustrating semiconductor devices according to still other embodiments of the present invention.
FIGS. 16 to 19 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

FIG. 1 is a block diagram illustrating a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 1, a semiconductor device (10) according to some embodiments of the present invention may include a memory cell array (20) and a peripheral circuit (30).

The memory cell array (20) may include a plurality of memory cell blocks (BLK1 to BLKn). Each of the memory cell blocks (BLK1 to BLKn) may include a plurality of memory cells. The memory cell blocks (BLK1 to BLKn) may be connected to a peripheral circuit (30) through bit lines (BL), word lines (WL), at least one string select line (SSL), and at least one ground select line (GSL).

Specifically, the memory cell blocks (BLK1 to BLKn) may be connected to a row decoder (33) via word lines (WL), at least one string select line (SSL), and at least one ground select line (GSL). Additionally, the memory cell blocks (BLK1 to BLKn) may be connected to a page buffer (35) via bit lines (BL).

The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from the outside of the semiconductor device (10), and can transmit and receive data (DATA) with a device outside of the semiconductor device (10). The peripheral circuit (30) can include a control logic (37), a row decoder (33), and a page buffer (35).

Although not shown, the peripheral circuit (30) may further include various sub-circuits such as an input/output circuit, a voltage generation circuit that generates various voltages necessary for the operation of the semiconductor device (10), and an error correction circuit for correcting errors in data (DATA) read from the memory cell array (20).

The control logic (37) can be connected to the row decoder (33), the voltage generator, and the input/output circuit. The control logic (37) can control the overall operation of the semiconductor device (10). The control logic (37) can generate various internal control signals used within the semiconductor device (10) in response to a control signal (CTRL).

For example, the control logic (37) can adjust the voltage levels provided to the word lines (WL) and bit lines (BL) when performing a memory operation such as a program operation or an erase operation.

The row decoder (33) can select at least one of a plurality of memory cell blocks (BLK1 to BLKn) in response to an address (ADDR), and can select at least one word line (WL), at least one string select line (SSL), and at least one ground select line (GSL) of the selected memory cell block (BLK1 to BLKn). The row decoder (33) can transmit a voltage for performing a memory operation to the word line (WL) of the selected memory cell block (BLK1 to BLKn).

The page buffer (35) can be connected to the memory cell array (20) via bit lines (BL). The page buffer (35) can operate as a writer driver or a sense amplifier. Specifically, during a program operation, the page buffer (35) can operate as a writer driver to apply a voltage according to data (DATA) to be stored in the memory cell array (20) to the bit lines (BL). Meanwhile, during a read operation, the page buffer (35) can operate as a sense amplifier to sense data (DATA) stored in the memory cell array (20).

FIG. 2 is a schematic perspective view illustrating a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 2, a semiconductor device according to some embodiments of the present invention may include a peripheral logic structure (PS) and a cell array structure (CS).

The cell array structure (CS) may be stacked on the peripheral logic structure (PS). That is, the peripheral logic structure (PS) and the cell array structure (CS) may overlap in a planar view. A semiconductor device according to some embodiments of the present invention may have a COP (Cell Over Peri) structure.

For example, the cell array structure (CS) may include the memory cell array (20) of Fig. 1. The peripheral logic structure (PS) may include the peripheral circuit (30) of Fig. 1.

A cell array structure (CS) may include a plurality of memory cell blocks (BLK1 to BLKn) arranged on a peripheral logic structure (PS).

FIG. 3 is a circuit diagram illustrating one memory cell block among a plurality of memory cell blocks included in a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 3, a memory cell block according to some embodiments of the present invention may include a common source line (CSL), a plurality of bit lines (BL), and a plurality of cell strings (CSTR) arranged between the common source line (CSL) and the bit lines (BL).

A plurality of cell strings (CSTR) may be connected in parallel to each of the bit lines (BL0-BL2). The plurality of cell strings (CSTR) may be commonly connected to a common source line (CSL). That is, a plurality of cell strings (CSTR) may be arranged between the plurality of bit lines (BL0-BL2) and one common source line (CSL). The common source lines (CSL) may be arranged two-dimensionally in plurality. Here, the same electrical voltage may be applied to the common source lines (CSL), or each of the common source lines (CSL) may be electrically controlled.

For example, each of the cell strings (CSTR) may be composed of series-connected string select transistors (SST1, SST2), series-connected memory cells (MCT), and a ground select transistor (GST). Additionally, each of the memory cells (MCT) includes a data storage element.

In some embodiments, each of the cell strings (CSTR) may include first and second string select transistors (SST1, SST2) connected in series, the second string select transistor (SST2) may be connected to a bit line (BL0-BL2), and the ground select transistor (GST) may be connected to a common source line (CSL). The memory cells (MCT) may be connected in series between the first string select transistor (SST1) and the ground select transistor (GST).

Additionally, each of the cell strings (CSTR) may further include a dummy cell (DMC) connected between the first string select transistor (SST1) and the memory cell (MCT). Although not shown in the drawing, the dummy cell (DMC) may also be connected between the ground select transistor (GST) and the memory cell (MCT). In some other embodiments, the ground select transistor (GST) in each of the cell strings (CSTR) may be composed of a plurality of series-connected MOS transistors, similar to the first and second string select transistors (SST1, SST2). In some other embodiments, each of the cell strings (CSTR) may include one string select transistor.

In some embodiments, the first string select transistor (SST1) may be controlled by the first string select line (SSL1), and the second string select transistor (SST2) may be controlled by the second string select line (SSL2). The memory cells (MCT) may be controlled by a plurality of word lines (WL0-WLn), and the dummy cells (DMC) may be controlled by a dummy word line (DWL). Additionally, the ground select transistor (GST) may be controlled by the ground select line (GSL). A common source line (CSL) may be commonly connected to the sources of the ground select transistors (GST).

A single cell string (CSTR) may be composed of a plurality of memory cells (MCT) having different distances from common source lines (CSL). In addition, a plurality of word lines (WL0-WLn, DWL) may be arranged between the common source lines (CSL) and bit lines (BL0-BL2).

Gate electrodes of memory cells (MCT) arranged at substantially the same distance from common source lines (CSL) may be commonly connected to one of the word lines (WL0-WLn, DWL) and thus may be in an equipotential state. Alternatively, even if the gate electrodes of memory cells (MCT) are arranged at substantially the same level from the common source lines (CSL), gate electrodes arranged in different rows or columns may be independently controlled.

The ground select lines (GSL0-GSL2) and the string select lines (SSL1, SSL2) may extend, for example, in the same direction as the word lines (WL0-WLn, DWL). The ground select lines (GSL0-GSL2) and the string select lines (SSL1, SSL2), which are arranged at substantially the same level from the common source lines (CSL), may be electrically isolated from each other.

Hereinafter, semiconductor devices according to some embodiments of the present invention will be described with reference to FIGS. 4 to 10.

FIG. 4 is a layout diagram for explaining a semiconductor device according to some embodiments of the present invention. FIG. 5 is an enlarged view of area R1 of FIG. 4. FIG. 6 is a cross-sectional view taken along line A-A' of FIG. 5. FIG. 7 is an enlarged view of area R2 of FIG. 5. FIG. 8 is a cross-sectional view taken along line B-B' of FIG. 5. FIG. 9 is a cross-sectional view taken along line C-C' of FIG. 5. FIG. 10 is a cross-sectional view taken along line D-D' of FIG. 4.

Referring to FIGS. 4 to 10, a semiconductor device according to some embodiments of the present invention includes a substrate (100), a transistor (TR), a plurality of wirings (101), a first interlayer insulating film (102), a lower support semiconductor layer (105), a common source plate (106), a contact support film (107), a filling insulating film (108), a first stack structure (110), a second stack structure (120), a first sacrificial insulating film (115), a second sacrificial insulating film (125), second to fourth interlayer insulating films (141, 142, 143), first to fifth electrode separation patterns (151, 152, 153, 154, 155), a channel insulating film (161), a channel film (162), a channel filling film (163), a conductive pad (164), a plurality of channel holes (CH), a plurality of stud contacts (SC), a plurality of gate contacts (GC), first and second through vias (V1, V2), gate contact connection wiring (171), first and second through-via connection wiring (172, 173), and bit line (180).

A cell region (I) and a contact region (II) may be defined on the substrate (100). The contact region (II) may be arranged on at least one side of the cell region (I) in the first direction (DR1). However, the technical idea of the present invention is not limited thereto. In some other embodiments, the contact region (II) may be arranged to surround the cell region (I).

The cell region (Ⅰ) may include a first cell region and a second cell region adjacent in a second direction (DR2) perpendicular to the first direction (DR1). The contact region (Ⅱ) may include a first contact region and a second contact region adjacent in the second direction (DR2).

The substrate (100) may be bulk silicon or a silicon-on-insulator (SOI). Alternatively, the substrate (100) may be a silicon substrate, or may include other materials, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, although the technical idea of the present invention is not limited thereto.

A transistor (TR) may be arranged on a substrate (100). A first interlayer insulating film (102) may be arranged to cover the transistor (TR) on the substrate (100). A plurality of wirings (101) may be arranged inside the first interlayer insulating film (102). At least one of the plurality of wirings (101) may be electrically connected to the transistor (TR).

The lower support semiconductor layer (105) may be disposed on the first interlayer insulating film (102). The lower support semiconductor layer (105) may have a flat plate shape. The lower support semiconductor layer (105) may be disposed in each of the cell region (I) and the contact region (II). The lower support semiconductor layer (105) may not be disposed in the region where the first through via (V1) and the second through via (V2) are formed.

The lower support semiconductor layer (105) may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof.

A common source plate (106) may be arranged on the lower support semiconductor layer (105). The common source plate (106) may have a flat plate shape. The common source plate (106) may be arranged in each of the cell region (I) and the contact region (II). The common source plate (106) may not be arranged in a region where the first through-via (V1) and the second through-via (V2) are formed.

The common source plate (106) can perform the function of the common source line (CSL) of FIG. 3.

The common source plate (106) may include, for example, polysilicon. However, the technical idea of the present invention is not limited thereto. That is, in some other embodiments, the common source plate (106) may include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or mixtures thereof.

The filling insulating film (108) may be disposed on the first interlayer insulating film (102). The filling insulating film (108) may be disposed on an area of the first interlayer insulating film (102) where the lower support semiconductor layer (105) and the common source plate (106) are not formed. For example, the upper surface of the filling insulating film (108) may be formed on the same plane as the upper surface of the common source plate (106). The filling insulating film (108) may include, for example, silicon oxide, but the technical idea of the present invention is not limited thereto.

The contact support film (107) may be arranged on the common source plate (106). The contact support film (107) may be arranged in each of the cell region (I) and the contact region (II). The contact support film (107) may be arranged to surround the sidewall of each of the plurality of channel holes (CH). The contact support film (107) may include a semiconductor material, such as, for example, silicon (Si), germanium (Ge), or a mixture thereof.

The first stack structure (110) may be disposed on the contact support film (107). The first stack structure (110) may be disposed in each of the first cell region and the first contact region. The first stack structure (110) may have a step-like sidewall profile in the first contact region. The first stack structure (110) may extend in the first direction (DR1).

The first stack structure (110) may include first insulating films (111) and first gate electrodes (112) that are alternately stacked. The first insulating film (111) may be arranged at the lowest portion of the first stack structure (110). The first gate electrode (112) may be arranged at the highest portion of the first stack structure (110). Although four first gate electrodes (112) are arranged in FIG. 6, this is only for convenience of explanation, and the technical idea of the present invention is not limited thereto.

The first insulating film (111) may include an insulating material, for example, at least one of a low-k material, an oxide film, a nitride film, and an oxynitride film. The first gate electrode (112) may include a conductive material. The first gate electrode (112) may include a conductive material, for example, tungsten (W), cobalt (Co), nickel (Ni), or a semiconductor material, such as silicon, but the technical idea of the present invention is not limited thereto.

The first stack structure (110) may include a first sacrificial insulating film (115). The first sacrificial insulating film (115) may be disposed on the filling insulating film (108) in the contact region (II). The first sacrificial insulating film (115) may overlap the first gate electrode (112) in the first direction (DR1).

At least a portion of the first sacrificial insulating film (115) may overlap the common source plate (106) in a third direction (DR3) perpendicular to the first and second directions (DR1, DR2). However, the technical idea of the present invention is not limited thereto.

The first sacrificial insulating film (115) may be a portion of the mold that remains without being removed during the process of forming the contact support film (107) and the first gate electrode (112). The first sacrificial insulating film (115) may include, for example, silicon nitride, but the technical idea of the present invention is not limited thereto.

The second stack structure (120) may be disposed on the contact support film (107). The second stack structure (120) may be disposed in each of the second cell region and the second contact region. The second stack structure (120) may have a step-like sidewall profile in the second contact region. The second stack structure (120) may be spaced apart from the first stack structure (110) in a second direction (DR2) that is perpendicular to the first direction (DR1). The second stack structure (120) may extend in the first direction (DR1).

The second stack structure (120) may include alternately stacked second insulating films (121) and second gate electrodes (122). Each of the second insulating films (121) and the second gate electrodes (122) may have a structure similar to that of the first insulating film (111) and the first gate electrode (112), respectively.

The second stack structure (120) may include a second sacrificial insulating film (125). The second sacrificial insulating film (125) may be disposed on the filling insulating film (108) in the cell region (I). The second sacrificial insulating film (125) may overlap the second gate electrode (122) in the first direction (DR1).

At least a portion of the second sacrificial insulating film (125) may overlap the common source plate (106) in the third direction (DR3). However, the technical idea of the present invention is not limited thereto.

The second sacrificial insulating film (125) may be a portion of the mold that remains without being removed during the process of forming the contact support film (107) and the second gate electrode (122). The second sacrificial insulating film (125) may include, for example, silicon nitride, but the technical idea of the present invention is not limited thereto.

A second interlayer insulating film (141) may be disposed on the first stack structure (110), the second stack structure (120), and the filling insulating film (108). The second interlayer insulating film (141) may include at least one of an insulating material, for example, a low-k material, an oxide film, a nitride film, and an oxynitride film.

The third interlayer insulating film (142) and the fourth interlayer insulating film (143) may be sequentially laminated on the second interlayer insulating film (141). Each of the third interlayer insulating film (142) and the fourth interlayer insulating film (143) may include at least one of an insulating material, for example, a low-k material, an oxide film, a nitride film, and an oxynitride film.

A first electrode separation pattern (151) may be arranged between a first stack structure (110) and a second stack structure (120). The first stack structure (110) and the second stack structure (120) may be separated by the first electrode separation pattern (151). The first electrode separation pattern (151) may extend in a first direction (DR1).

The first electrode separating pattern (151) can penetrate the third interlayer insulating film (142) and the second interlayer insulating film (141) in the third direction (DR3). The first electrode separating pattern (151) can penetrate the common source plate (106) in the third direction (DR3). The lower surface of the first electrode separating pattern (151) can be formed on the same plane as the lower surface of the common source plate (106). The upper surface of the first electrode separating pattern (151) can be formed on the same plane as the upper surface of the third interlayer insulating film (142). However, the technical idea of the present invention is not limited thereto.

The second electrode separation pattern (152) can cross the first stack structure (110) in the second direction (DR2) on the contact area (II). The second electrode separation pattern (152) can come into contact with the first electrode separation pattern (151).

The second electrode separating pattern (152) can penetrate the third interlayer insulating film (142), the second interlayer insulating film (141), the first stack structure (110), the contact support film (107), and the common source plate (106) in the third direction (DR3). The lower surface of the second electrode separating pattern (152) can be formed on the same plane as the lower surface of the common source plate (106). The upper surface of the second electrode separating pattern (152) can be formed on the same plane as the upper surface of the third interlayer insulating film (142). However, the technical idea of the present invention is not limited thereto.

The third electrode separation pattern (153) may be disposed on a second side of the first stack structure (110) opposite to the first side of the first stack structure (110) on which the first electrode separation pattern (151) is disposed. The third electrode separation pattern (153) may extend in the first direction (DR1). The third electrode separation pattern (153) may be in contact with the second electrode separation pattern (152). The third electrode separation pattern (153) may penetrate the third interlayer insulating film (142), the second interlayer insulating film (141), and the common source plate (106) in the third direction (DR3).

The fifth electrode separation pattern (155) may be arranged on a second side of the second stack structure (120) opposite to the first side of the second stack structure (120) on which the first electrode separation pattern (151) is arranged. The fifth electrode separation pattern (155) may extend in the first direction (DR1). The fifth electrode separation pattern (155) may penetrate the third interlayer insulating film (142), the second interlayer insulating film (141), and the common source plate (106) in the third direction (DR3).

The fourth electrode separation pattern (154) may extend in the first direction (DR1) between the first electrode separation pattern (151) and the fifth electrode separation pattern (155). The fourth electrode separation pattern (154) may not be positioned in an area where the second through via (V2) is formed. The fourth electrode separation pattern (154) may penetrate the third interlayer insulating film (142), the second interlayer insulating film (141), the second stack structure (120), the contact support film (107), and the common source plate (106) in the third direction (DR3).

Each of the first to fifth electrode separation patterns (151, 152, 153, 154, 155) may include, for example, at least one of an insulating material, for example, a low-k material, an oxide film, a nitride film, and an oxynitride film.

Each of the plurality of channel holes (CH) can penetrate the second interlayer insulating film (141), the first stack structure (110), the second stack structure (120), the contact support film (107), and the common source plate (106) in the third direction (DR3). Each of the plurality of channel holes (CH) can extend into the interior of the lower support semiconductor layer (105).

The plurality of channel holes (CH) may include, for example, first to eighteenth channel holes (CH1 to CH18).

Each of the first to eleventh channel holes (CH1 to CH11) can penetrate the first stack structure (110) in a third direction (DR3). The first to sixth channel holes (CH1 to CH6) can be sequentially spaced apart in the first direction (DR1). The seventh to eleventh channel holes (CH7 to CH11) can be sequentially spaced apart in the first direction (DR1). Each of the seventh to eleventh channel holes (CH7 to CH11) can be arranged adjacent to the first electrode separation pattern (151).

For example, the 11th channel hole (CH11) is a channel hole that is positioned closest to the first contact region in the first direction (DR1) among the channel holes that penetrate the first stack structure (110) in the third direction (DR3) on the first cell region. In addition, the 16th channel hole (CH16) is a channel hole that is positioned closest to the second contact region in the first direction (DR1) among the channel holes that penetrate the second stack structure (120) in the third direction (DR3) on the second cell region.

The seventh channel hole (CH7) can be spaced apart from the first channel hole (CH1) in a second direction (DR2). The eighth channel hole (CH8) can be spaced apart from the second channel hole (CH2) in a second direction (DR2). The ninth channel hole (CH9) can be spaced apart from the third channel hole (CH3) in a second direction (DR2). The tenth channel hole (CH10) can be spaced apart from the fourth channel hole (CH4) in a second direction (DR2). The eleventh channel hole (CH11) can be spaced apart from the fifth channel hole (CH5) in a second direction (DR2).

Each of the first to fourth channel holes (CH1 to CH4) and the seventh to eleventh channel holes (CH7 to CH10) may be arranged on the contact region (II). Each of the fifth, sixth, and eleventh channel holes (CH5, CH6, CH11) may be arranged on the cell region (I).

A second electrode separation pattern (152) may be arranged between the second channel hole (CH2) and the third channel hole (CH3) and between the eighth channel hole (CH8) and the ninth channel hole (CH9).

Each of the twelfth to eighteenth channel holes (CH12 to CH18) can penetrate the second stack structure (120) in a third direction (DR3). The twelfth to sixteenth channel holes (CH12 to CH16) can be sequentially spaced apart in a first direction (DR1). The seventeenth channel hole (CH17) can be spaced apart from the eleventh channel hole (CH11) in a second direction (DR2). The eighteenth channel hole (CH18) can be spaced apart from the seventeenth channel hole (CH17) in a first direction (DR1).

Each of the 12th to 16th channel holes (CH12 to CH16) may be positioned adjacent to the first electrode separation pattern (151).

Each of the 12th to 15th channel holes (CH12 to CH15) may be arranged on a contact area (II). Each of the 16th to 18th channel holes (CH16, CH17, CH18) may be arranged on a cell area (I).

On the contact region (II), the ninth channel hole (CH9) can be spaced apart from the fourteenth channel hole (CH14) in a fourth direction (DR4) having an acute angle (θ) with the first direction (DR1). On the contact region (II), the tenth channel hole (CH10) can be spaced apart from the fifteenth channel hole (CH15) in a fourth direction (DR4). On the cell region (I), the eleventh channel hole (CH11) can be spaced apart from the sixteenth channel hole (CH16) in a fourth direction (DR4).

The spacing (d1) in the first direction (DR1) between the 11th channel hole (CH11) and the 16th channel hole (CH16) on the cell region (Ⅰ) can be 1 nm to 30 nm. The spacing (d2) in the first direction (DR1) between the 10th channel hole (CH10) and the 15th channel hole (CH15) on the contact region (Ⅱ) can be 1 nm to 50 nm.

A channel insulating film (161), a channel film (162), a channel filling film (163), and a conductive pad (164) can be placed inside the fifth channel hole (CH5).

The channel insulating film (161) may be arranged along the sidewall and bottom surface of the fifth channel hole (CH5). As shown in FIG. 7, the channel insulating film (161) may include a blocking insulating film (161_1), a charge storage film (161_2), and a tunnel insulating film (161_3). The blocking insulating film (161_1), the charge storage film (161_2), and the tunnel insulating film (161_3) may be sequentially laminated on the sidewall and bottom surface of the fifth channel hole (CH5).

The tunnel insulating film (161_3) can allow charges to pass between, for example, the channel film (162) and the charge storage film (161_2). The charge storage film (161_2) can store charges that have passed through the tunnel insulating film (161_3), for example, between the blocking insulating film (161_1) and the tunnel insulating film (161_3). The blocking insulating film (161_1) can prevent charges captured in the charge storage film (161_2) from being released to the first gate electrode (112).

The channel film (162) may be arranged on the channel insulating film (161) inside the fifth channel hole (CH5). As illustrated in FIG. 7, the common source plate (106) may extend into the inside of the fifth channel hole (CH5) and come into contact with the channel film (162). In this case, a part of the common source plate (106) may extend into the inside of the fifth channel hole (CH5) along the channel film (162). The channel insulating film (161) may be separated by the common source plate (106).

The channel film (162) can function as a channel region. The channel film (162) can provide charges to be trapped or released by the channel insulating film (161). The channel film (162) can include a semiconductor material, such as silicon (Si), germanium (Ge), or a mixture thereof, for example. In addition, the channel film (162) can also include a metal oxide semiconductor material.

The channel filling film (163) may be positioned to fill the interior of the fifth channel hole (CH5) on the channel film (162). The channel filling film (163) may include an insulating material.

The conductive pad (164) may be arranged on the channel filling film (163) inside the fifth channel hole (CH5). The upper surface of the conductive pad (164) may be formed on the same plane as the upper surface of the channel film (162) and the upper surface of the channel insulating film (161), respectively. However, the technical idea of the present invention is not limited thereto. That is, in some other embodiments, the conductive pad (164) may be in contact with the sidewall of the fifth channel hole (CH5). The conductive pad (164) may function as a bit line pad.

Each of the first to fourth channel holes (CH1 to CH4) and the sixth to eighteenth channel holes (CH6 to CH18) may have a structure similar to the fifth channel hole (CH5).

Each of the plurality of gate contacts (GC) can penetrate the fourth interlayer insulating film (143), the third interlayer insulating film (142), and the second interlayer insulating film (141) in the third direction (DR3) on the contact area (II).

For example, the first gate contact (GC1) may be disposed on the first stack structure (110) of the first contact region. The first gate contact (GC1) may be disposed between the third channel hole (CH3), the fourth channel hole (CH4), the ninth channel hole (CH9), and the tenth channel hole (CH10). The first gate contact (GC1) may be electrically connected to the first gate electrode (112).

The second to fourth gate contacts (GC2, GC3, GC4) can be sequentially spaced apart in the first direction (DR1) on the second stack structure (120) of the second contact region. For example, the third gate contact (GC3) can be arranged between the twelfth channel hole (CH12) and the thirteenth channel hole (CH13). Also, for example, the fourth gate contact (GC4) can be arranged between the fourteenth channel hole (CH14) and the fifteenth channel hole (CH15).

The first gate contact (GC1) can be spaced apart from the fourth gate contact (GC4) in a fourth direction (DR4) having an acute angle (θ) with the first direction (DR1). A spacing (d3) in the first direction (DR1) between the first gate contact (GC1) and the fourth gate contact (GC4) can be 1 nm to 50 nm. Each of the plurality of gate contacts (GC) can include a conductive material.

Each of the plurality of stud contacts (SC) can penetrate the fourth interlayer insulating film (143) and the third interlayer insulating film (142) in the third direction (DR3) on the cell region (I). Each of the plurality of stud contacts (SC) can completely overlap the conductive pad (164) in the third direction (DR3).

For example, the first stud contact (SC1) may be disposed on a conductive pad (164) disposed inside the fifth channel hole (CH5). The second stud contact (SC2) may be disposed on a conductive pad (164) disposed inside the sixth channel hole (CH6). The third stud contact (SC3) may be disposed on a conductive pad (164) disposed inside the eleventh channel hole (CH11). The fourth stud contact (SC4) may be disposed on a conductive pad (164) disposed inside the sixteenth channel hole (CH16). The fifth stud contact (SC5) may be disposed on a conductive pad (164) disposed inside the seventeenth channel hole (CH17). The sixth stud contact (SC6) may be disposed on a conductive pad (164) disposed inside the eighteenth channel hole (CH18).

The third stud contact (SC3) can be spaced apart from the fourth stud contact (SC4) in a fourth direction (DR4) having an acute angle (θ) with the first direction (DR1). Each of the plurality of stud contacts (SC) can include a conductive material.

A first through-via (V1) can penetrate a fourth interlayer insulating film (143), a third interlayer insulating film (142), a second interlayer insulating film (141), a first sacrificial insulating film (115) of a first stack structure (110), and a filling insulating film (108) in a third direction (DR3) on a first contact area. The first through-via (V1) can be spaced apart from the first channel hole (CH1) in the first direction (DR1). The first through-via (V1) can extend into the first interlayer insulating film (102) and be electrically connected to at least one of a plurality of wirings (101).

The second through via (V2) can penetrate the fourth interlayer insulating film (143), the third interlayer insulating film (142), the second interlayer insulating film (141), the second sacrificial insulating film (125) of the second stack structure (120) and the filling insulating film (108) in the third direction (DR3) on the second cell region. The second through via (V2) can be arranged between the first electrode separation pattern (151) and the fifth electrode separation pattern (155). The second through via (V2) can extend into the first interlayer insulating film (102) and be electrically connected to at least one of the plurality of wires (101).

Each of the first through-via (V1) and the second through-via (V2) may include a conductive material.

The gate contact connection wiring (171) may be arranged, for example, on the upper surface of each of the first to fourth gate contacts (GC1, GC2, GC3, GC4). The gate contact connection wiring (171) may be electrically connected to each of the first to fourth gate contacts (GC1, GC2, GC3, GC4).

The first through-via connection wiring (172) may be arranged on the upper surface of the first through-via (V1). The first through-via connection wiring (172) may be electrically connected to the first through-via (V1). The second through-via connection wiring (173) may be arranged on the upper surface of the second through-via (V2). The second through-via connection wiring (173) may be electrically connected to the second through-via (V2).

Each of the plurality of bit lines (180) may be arranged on an upper surface of each of the plurality of stud contacts (SC). Each of the plurality of bit lines (180) may extend in the second direction (DR2). For example, each of the plurality of bit lines (180) may be arranged on an upper surface of each of the first to sixth stud contacts (SC1 to SC6). Each of the plurality of bit lines (180) may be electrically connected to each of the first to sixth stud contacts (SC1 to SC6).

A semiconductor device according to some embodiments of the present invention can effectively align between channel holes and stud contacts by arranging stud contacts to reflect misalignment of channel holes in a process of forming an electrode separation pattern.

In addition, semiconductor devices according to some embodiments of the present invention can effectively align gate contacts by arranging the gate contacts to reflect the misalignment of channel holes in the process of forming an electrode separation pattern.

Hereinafter, a semiconductor device according to some other embodiments of the present invention will be described with reference to FIG. 11. The description will focus on differences from the semiconductor devices illustrated in FIGS. 4 to 10.

FIG. 11 is a layout diagram illustrating a semiconductor device according to some other embodiments of the present invention.

Referring to FIG. 11, a semiconductor device according to some other embodiments of the present invention may have a fourth gate contact (GC4_1) aligned with the first gate contact (GC1) in the second direction (DR2). That is, the fourth gate contact (GC4_1) may be spaced apart from the first gate contact (GC1) in the second direction (DR2).

The second to fourth gate contacts (GC2, GC3_1, GC4_1) can be sequentially spaced in the first direction (DR1) on the second gate stack (120 in FIG. 8).

The 12th channel hole (CH12_1) can be aligned with the 7th channel hole (CH7) in the second direction (DR2). The 14th channel hole (CH14_1) can be aligned with the 9th channel hole (CH9) in the second direction (DR2). The 15th channel hole (CH15_1) can be aligned with the 10th channel hole (CH10) in the second direction (DR2). The 13th channel hole (CH13_1) can be arranged between the 12th channel hole (CH12_1) and the 14th channel hole (CH14_1).

Hereinafter, a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 12 and 13. The description will focus on differences from the semiconductor devices illustrated in FIGS. 4 to 10.

FIGS. 12 and 13 are cross-sectional views illustrating semiconductor devices according to still other embodiments of the present invention.

Referring to FIGS. 12 and 13, a semiconductor device according to still another embodiment of the present invention may have each of a plurality of electrode separation patterns formed as a double film. For example, a second electrode separation pattern (352) may include a first film (352_1) and a second film (352_2) formed along a sidewall and a bottom surface of the first film (352_1).

The first film (352_1) of the second electrode separating pattern (352) and the second film (352_2) of the second electrode separating pattern (352) may each include different materials. The first film (352_1) of the second electrode separating pattern (352) may include, for example, at least one of tungsten (W) and polysilicon. The second film (352_2) of the second electrode separating pattern (352) may include an insulating material, for example, at least one of a low-k material, an oxide film, a nitride film, and an oxynitride film. However, the technical idea of the present invention is not limited thereto.

Additionally, for example, the first electrode separation pattern (351) may include a first film (351_1) and a second film (351_2) formed along the sidewall and bottom surface of the first film (351_1).

Each of the first film (351_1) of the first electrode separating pattern (351) and the second film (351_2) of the first electrode separating pattern (351) may include different materials, similar to the second electrode separating pattern (352). Each of the third electrode separating pattern (353) and the fourth electrode separating pattern (354) may have a structure similar to the first electrode separating pattern (351).

Hereinafter, a semiconductor device according to still another embodiment of the present invention will be described with reference to FIGS. 14 and 15. The description will focus on differences from the semiconductor devices illustrated in FIGS. 4 to 10.

FIGS. 14 and 15 are cross-sectional views illustrating semiconductor devices according to still other embodiments of the present invention.

Referring to FIGS. 14 and 15, a semiconductor device according to still another embodiment of the present invention may have each of a plurality of electrode separation patterns formed as a double film. For example, a second electrode separation pattern (452) may include a first film (452_1) and a second film (452_2) formed along a sidewall of the first film (452_1).

Each of the first film (452_1) of the second electrode separating pattern (452) and the second film (452_2) of the second electrode separating pattern (452) may include different materials. The first film (452_1) of the second electrode separating pattern (452) may include, for example, at least one of tungsten (W) and polysilicon. The second film (452_2) of the second electrode separating pattern (452) may include an insulating material, for example, at least one of a low-k material, an oxide film, a nitride film, and an oxynitride film.

Additionally, for example, the first electrode separating pattern (451) may include a first film (451_1) and a second film (451_2) formed along a sidewall of the first film (451_1). Each of the first film (451_1) of the first electrode separating pattern (451) and the second film (451_2) of the first electrode separating pattern (451) may include different materials, similar to the second electrode separating pattern (452). Each of the third electrode separating pattern (453) and the fourth electrode separating pattern (454) may have a structure similar to the first electrode separating pattern (451).

The common source line (406) may be arranged inside the lower support semiconductor layer (405). The common source line (406) may be arranged under each of the first to fourth electrode separation patterns (451, 452, 453, 454).

For example, the common source line (406) may extend in the first direction (DR1) from the bottom of each of the first electrode separation pattern (451), the third electrode separation pattern (453), and the fourth electrode separation pattern (454). Additionally, the common source line (406) may extend in the second direction (DR2) from the bottom of the second electrode separation pattern (452).

Hereinafter, a method for manufacturing a semiconductor device according to some embodiments of the present invention will be described with reference to FIGS. 5 and 16 to 19.

FIGS. 16 to 19 are intermediate step drawings for explaining a method of manufacturing a semiconductor device according to some embodiments of the present invention.

Referring to FIG. 16, a stack structure including a first insulating film (111 of FIG. 6), a first sacrificial insulating film (115 of FIG. 6), a second insulating film (121 of FIG. 8), and a second sacrificial insulating film (125 of FIG. 8) can be formed on a substrate (100 of FIG. 6). Subsequently, a second interlayer insulating film (141 of FIG. 6) can be formed on the stack structure.

Next, through a subsequent process, first to tenth channel holes (CH1 to CH10) may be formed on an area where a first stack structure (110 in FIG. 6) is formed. In addition, through a subsequent process, twelfth to eighteenth channel holes (CH12 to CH18) may be formed on an area where a second stack structure (120 in FIG. 8) is formed.

For example, the second channel hole (CH2), the eighth channel hole (CH8), and the thirteenth channel hole (CH13) can be aligned in the second direction (DR2). The third channel hole (CH3), the ninth channel hole (CH9), and the fourteenth channel hole (CH14) can be aligned in the second direction (DR2). The fourth channel hole (CH4), the tenth channel hole (CH10), and the fifteenth channel hole (CH15) can be aligned in the second direction (DR2). The fifth channel hole (CH5), the eleventh channel hole (CH11), and the sixteenth channel hole (CH16) can be aligned in the second direction (DR2).

Next, a channel insulating film (161 in FIG. 6), a channel film (162 in FIG. 6), a channel filling film (163 in FIG. 6), and a conductive pad (164 in FIG. 6) can be formed inside each of the first to eighteenth channel holes (CH1 to CH18).

Referring to FIG. 17, a third interlayer insulating film (142 of FIG. 6) can be formed on a second interlayer insulating film (141 of FIG. 6).

Next, by forming first to fourth electrode separation patterns (151, 152, 153, 154), a first stack structure (110 in FIG. 6) and a second stack structure (120 in FIG. 8) separated by the first electrode separation pattern (151) can be formed.

Through the process of forming the first to fourth electrode separation patterns (151, 152, 153, 154), some channel holes may be misaligned.

For example, the second channel hole (CH2) and the eighth channel hole (CH8) may each be misaligned with the thirteenth channel hole (CH13) in the second direction (DR2). The third channel hole (CH3) and the ninth channel hole (CH9) may each be misaligned with the fourteenth channel hole (CH14) in the second direction (DR2). The fourth channel hole (CH4) and the tenth channel hole (CH10) may each be misaligned with the fifteenth channel hole (CH15) in the second direction (DR2). The fifth channel hole (CH5) and the eleventh channel hole (CH11) may each be misaligned with the sixteenth channel hole (CH16) in the second direction (DR2).

For example, the 11th channel hole (CH11) can be spaced apart from the 16th channel hole (CH16) in a fourth direction (DR4) having an acute angle (θ) with the first direction (DR1).

Referring to FIG. 18, a fourth interlayer insulating film (143 of FIG. 6) can be formed on a third interlayer insulating film (142 of FIG. 6).

Next, first to fourth gate contacts (GC1, GC2, GC3, GC4) can be formed. For example, the first gate contact (GC1) can be spaced apart from the fourth gate contact (GC4) in a fourth direction (DR4).

Referring to FIG. 19, first to sixth stud contacts (SC1 to SC6) may be formed on each of a plurality of channel holes formed on the cell region (I). For example, a third stud contact (SC3) formed on an eleventh channel hole (CH11) may be spaced apart from a fourth stud contact (SC4) formed on a sixteenth channel hole (CH16) in a fourth direction (DR4). In some other embodiments, the first to fourth gate contacts (GC1, GC2, GC3, GC4) and the first to sixth stud contacts (SC1 to SC6) may be formed through the same process.

Next, a first through-via (V1 in FIG. 6) may be formed to penetrate the filling insulating film (108) overlapping the first stack structure (110 in FIG. 6) in the third direction (DR3). In addition, a second through-via (V2 in FIG. 10) may be formed to penetrate the filling insulating film (108) overlapping the second stack structure (120 in FIG. 10) in the third direction (DR3).

Next, a gate contact connection wiring (171 in FIG. 8) may be formed on each of the first to fourth gate contacts (GC1, GC2, GC3, GC4). In addition, a first through-via connection wiring (172 in FIG. 6) may be formed on the first through-via (V1 in FIG. 6). In addition, a second through-via connection wiring (173 in FIG. 10) may be formed on the second through-via (V2 in FIG. 10). In addition, a plurality of bit lines (180) extending in the second direction (DR2) may be formed on each of the first to eighteenth channel holes (CH1 to CH18).

Through these processes, the semiconductor device illustrated in Fig. 5 can be manufactured.

Although the embodiments according to the technical idea of the present invention have been described with reference to the attached drawings, the present invention is not limited to the embodiments described above, but can be manufactured in various different forms, and a person having ordinary skill in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive.

100: Substrate 105: Lower support semiconductor layer
106: Common source plate 107: Contact support membrane
108: Filling insulation film 110: First stack structure
120: Second stack structure 141: Second interlayer insulating film
142: Third interlayer insulation film 143: Third interlayer insulation film
151 to 155: First to fifth electrode separation patterns
CH: Multiple channel holes SC: Multiple stud contacts
GC: Multiple gate contacts V1: First through-via
V2: 2nd through via 180: bit line

Claims (10)

A substrate having a cell region and a contact region arranged on at least one side of the cell region in a first direction, wherein the cell region includes a first cell region and a second cell region adjacent in a second direction perpendicular to the first direction, and the contact region includes a first contact region and a second contact region adjacent in the second direction;
A first stack structure disposed on the first cell region and the first contact region, in which a first insulating film and a first gate electrode are alternately laminated, and extending in the first direction;
A second stack structure disposed on the second cell region and the second contact region, in which a second insulating film and a second gate electrode are alternately laminated, is spaced apart from the first stack structure in the second direction, and extends in the first direction;
An interlayer insulating film disposed on the first and second stack structures;
A first through-via disposed on the first contact area and penetrating the interlayer insulating film in a third direction perpendicular to the first and second directions;
A first gate contact disposed on the first contact region, penetrating the interlayer insulating film in the third direction and connected to the first stack structure, and disposed most adjacent to the first cell region;
A second gate contact disposed on the second contact region, penetrating the interlayer insulating film in the third direction and connected to the second stack structure, disposed most adjacent to the second cell region, and spaced apart from the first gate contact in a fourth direction having an acute angle with the first direction;
A first electrode separation pattern disposed between the first stack structure and the second stack structure and extending in the first direction;
A first channel hole disposed on the first cell region, penetrating the first stack structure in the third direction, and disposed most adjacent to the first contact region; and
A semiconductor device comprising a second channel hole disposed on the second cell region, penetrating the second stack structure in the third direction, and disposed most adjacent to the second contact region. delete In paragraph 1,
A semiconductor device wherein a spacing between the first gate contact and the second gate contact in the first direction is 1 nm to 50 nm. In paragraph 1,
A semiconductor device further comprising a second electrode separation pattern disposed on the first contact region, crossing the first stack structure in the second direction, and in contact with the first electrode separation pattern. In paragraph 1,
A first stud contact overlapping the first channel hole and the third direction,
A semiconductor device further comprising a second stud contact overlapping the second channel hole in the third direction and spaced apart from the first stud contact in the fourth direction. In paragraph 1,
A semiconductor device wherein the spacing in the first direction between the first channel hole and the second channel hole is 1 nm to 30 nm. A substrate having a cell region and contact regions disposed on both sides of the cell region defined;
A first stack structure disposed on the substrate, in which a first insulating film and a first gate electrode are alternately laminated and extend in a first direction;
A second stack structure disposed on the substrate, in which a second insulating film and a second gate electrode are alternately laminated, and is spaced apart from the first stack structure in a second direction perpendicular to the first direction, and extends in the first direction;
An interlayer insulating film disposed on the first and second stack structures;
A first electrode separation pattern disposed between the first stack structure and the second stack structure and extending in the first direction;
A second electrode separation pattern crossing the first stack structure in the second direction and in contact with the first electrode separation pattern;
A first channel hole penetrating the first stack structure in a third direction perpendicular to the first and second directions on the cell area and positioned most adjacent to the contact area in the first direction;
A second channel hole penetrating the second stack structure in the third direction on the cell area, positioned most adjacent to the contact area in the first direction, and spaced apart from the first channel hole in a fourth direction having an acute angle with the first direction;
A first gate contact connected to the first stack structure by penetrating the interlayer insulating film in the third direction on the contact area; and
A semiconductor device comprising a second gate contact that penetrates the interlayer insulating film in the third direction on the contact area and is connected to the second stack structure, and is spaced apart from the first gate contact in the fourth direction. In Article 7,
A first through-via penetrating the first stack structure in the third direction on the contact area,
A semiconductor device further comprising a second through via penetrating the second stack structure in the third direction on the cell area. In Article 7,
A common source plate having a flat shape and disposed between the substrate and the first stack structure,
A semiconductor device further comprising a transistor and a plurality of wirings disposed between the substrate and the common source plate. A substrate having a cell region and contact regions disposed on both sides of the cell region defined;
A first stack structure disposed on the substrate, in which a first insulating film and a first gate electrode are alternately laminated and extend in a first direction;
A second stack structure disposed on the substrate, in which a second insulating film and a second gate electrode are alternately laminated, and is spaced apart from the first stack structure in a second direction perpendicular to the first direction, and extends in the first direction;
An interlayer insulating film disposed on the first and second stack structures;
A first electrode separation pattern disposed between the first stack structure and the second stack structure and extending in the first direction;
A second electrode separation pattern crossing the first stack structure in the second direction and in contact with the first electrode separation pattern;
A first channel hole penetrating the first stack structure in a third direction perpendicular to the first and second directions on the cell area and positioned most adjacent to the contact area in the first direction;
A second channel hole penetrating the second stack structure in the third direction on the cell area, positioned most adjacent to the contact area in the first direction, and spaced apart from the first channel hole in a fourth direction having an acute angle with the first direction;
A first stud contact overlapping the first channel hole and the third direction;
A second stud contact overlapping the second channel hole in the third direction and spaced apart from the first stud contact in the fourth direction;
A first gate contact connected to the first stack structure by penetrating the interlayer insulating film in the third direction on the contact area; and
A semiconductor device comprising a second gate contact that penetrates the interlayer insulating film in the third direction on the contact area and is connected to the second stack structure, and is spaced apart from the first gate contact in the fourth direction.

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