KR102792381B1 - Resistance variable memory device - Google Patents

Abstract

The present invention relates to a variable resistance memory device, comprising: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, wherein each of the memory cells comprises a variable resistor and a selection element connected in series between corresponding first and second conductive lines, wherein the selection element comprises chalcogen compound layers sequentially stacked and insulating blocks formed at an interface between the chalcogen compound layers, wherein each of the chalcogen compound layers comprises a quinary chalcogen compound in which 50 at% of a chalcogen element including tellurium (Te) and selenium (Se) is combined with 50 at% of a non-chalcogen element including silicon (Si), arsenic (As), and germanium (Ge), and wherein each of the insulating blocks comprises: tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and A variable resistance memory device comprising an oxide of germanium (Ge), a nitride of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), or a mixture of the oxides and the nitrides is provided.

Description

Resistance variable memory device

The present invention relates to a variable resistance memory device, and more particularly, to a variable resistance memory device having a cross-point structure.

Recently, with the spread of portable digital devices and the increasing need to store digital data, interest in nonvolatile memory devices that do not lose stored data even when power is turned off is increasing.

Among the semiconductor devices mentioned above, flash memory devices that can be manufactured at low cost by being based on a silicon process like DRAM memory devices are widely used. However, flash memory devices have the disadvantages of having a relatively low integration level, slow operating speed, and requiring a relatively high voltage to store data compared to DRAM memory devices, which are volatile memory devices.

To overcome the shortcomings of such flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) have been proposed. Such next-generation nonvolatile memory devices can operate at relatively low voltages and have fast access times, which significantly offsets the shortcomings of flash memory devices.

In particular, research on next-generation nonvolatile memory devices having a three-dimensional cross-point array structure has been actively conducted recently in response to high integration demands. The cross-point array structure is a structure in which multiple bit lines and multiple word lines are arranged to intersect each other and memory cells are arranged at the cross points of the bit and word lines, thereby enabling random access to each memory cell, making it easy to implement data storage (program) and reading (read).

Such a cross-point array structure can be easily formed into a three-dimensional structure by forming unit cells in a stacked structure along the vertical direction between word and bit lines, and stacking a plurality of single cross-point array structures along the vertical direction. Accordingly, next-generation non-volatile memory elements can be integrated at high density.

However, as the problem of high leakage current of memory in three-dimensional stacked structures arises, the need for memory with lower leakage current suitable for high density is increasing.

The background technology of this application is disclosed in Patent Publication No. 10-2018-0010790.

The technical problem to be solved by the present invention is to provide a variable resistance memory device with improved electrical characteristics and switching characteristics and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present invention for achieving the above object, a variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction intersecting the first direction, and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, each of the memory cells including a variable resistor and a selection element connected in series between corresponding first and second conductive lines, wherein the selection element includes chalcogen compound layers sequentially stacked and insulating blocks formed at an interface between the chalcogen compound layers, each of the chalcogen compound layers including a 5-element chalcogen compound in which 50 at% of a chalcogen element including tellurium (Te) and selenium (Se) is combined with 50 at% of a non-chalcogen element including silicon (Si), arsenic (As), and germanium (Ge), and each of the insulating blocks includes tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and oxides of germanium (Ge), nitrides of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), or mixtures of the oxides and nitrides.

According to one embodiment, the pentane chalcogen compound may include 50 at% of a chalcogen element composed of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 and 50 at% of a non-chalcogen element composed of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7.

According to one embodiment, the chalcogen compound layers include a first chalcogen compound layer, a second chalcogen compound layer, and a third chalcogen compound layer that are sequentially stacked, the insulating blocks include first insulating blocks formed at an interface between the first chalcogen compound layer and the second chalcogen compound layer, and second insulating blocks formed at an interface between the second chalcogen compound layer and the third chalcogen compound layer, the first to third chalcogen compound layers have a thickness of 10 nm to 100 nm, the first and second insulating blocks have a particle size of 1 nm to 5 nm, and the particle size of the second insulating blocks may be larger than the particle size of the first insulating blocks.

According to embodiments of the present invention, since chalcogen compound layers having ovonic threshold switching characteristics are composed of 50 at% of chalcogen elements consisting of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 and 50 at% of non-chalcogen elements consisting of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7, excellent phase change characteristics and excellent durability can be achieved. In addition, since insulating blocks functioning as traps that limit the movement of electrons are formed within the chalcogen compound layers, the flow of electrons moving under a low voltage can be effectively blocked, thereby reducing the leakage current of the selection element.

As a result, it may be possible to provide a variable resistance memory device with improved electrical characteristics and switching characteristics.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.
FIG. 2 is a conceptual diagram illustrating a selection element according to embodiments of the present invention.
FIG. 3 is a plan view showing a variable resistance memory element according to embodiments of the present invention.
Figures 4a and 4b are cross-sectional views taken along lines I-I' and II-II' of Figure 3, respectively.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the present embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In this specification, when it is said that an element is “on” another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. Also, in this specification, when it is said that a part “includes” a certain element, this does not mean that other elements are excluded, but rather that other elements can be included, unless otherwise specifically stated.

The terms “about,” “substantially,” and the like, as used throughout this specification, are used in a meaning that is at or near the numerical value when manufacturing and material tolerances inherent in the meanings referred to are presented, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure, which states precise or absolute values to aid understanding of this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.

Referring to FIG. 1, first conductive lines (CL1) extending in a first direction (D1) and second conductive lines (CL2) extending in a second direction (D2) intersecting the first direction (D1) may be provided. The second conductive lines (CL2) may be spaced apart from the first conductive lines (CL1) along a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2). A memory cell stack (MCA) may be provided between the first conductive lines (CL1) and the second conductive lines (CL2). The memory cell stack (MCA) may include memory cells (MC) provided at each of the intersections of the first conductive lines (CL1) and the second conductive lines (CL2). The memory cells (MC) may be arranged two-dimensionally to form rows and columns. Although one memory cell stack (MCA) is illustrated in the present embodiment, embodiments of the present invention are not limited thereto. Memory cell stacks (MCAs) can be provided in multiples and stacked vertically.

Each of the memory cells (MC) may include a variable resistor (VR) and a selection element (SW). The variable resistor (VR) and the selection element (SW) may be connected in series with each other between a pair of conductive lines (CL1, CL2) connected thereto.

For example, a variable resistor (VR) and a selection element (SW) included in each of the memory cells (MC) may be connected in series with each other between a corresponding first conductive line (CL1) and a corresponding second conductive line (CL2). Here, the first conductive line (CL1) may be a bit line, and the second conductive line (CL2) may be a word line, or vice versa. In addition, although FIG. 1 illustrates that the selection element (SW) is provided on the variable resistor (VR), embodiments of the present invention are not limited thereto. Unlike FIG. 1, the variable resistor (VR) may also be provided on the selection element (SW).

Voltage is applied to the variable resistor (VR) of the memory cell (MC) through the first challenge line (CL1) and the second challenge line (CL2), so that current can flow through the variable resistor (VR), and the resistance of the variable resistor (VR) of the selected memory cell (MC) can change depending on the applied voltage.

According to the change in resistance of the variable resistor (VR), the memory cell (MC) can store digital information such as "0" or "1", and the digital information can be erased from the memory cell (MC). For example, data can be written in the memory cell (MC) in a high resistance state "0" and a low resistance state "1". Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell (MC) according to the embodiments of the present invention is not limited to the digital information of the high resistance state "0" and the low resistance state "1" exemplified above, and can store various resistance states.

For example, the variable resistor (VR) may include a transition metal oxide layer, in which case at least one electrical path may be created or destroyed within the variable resistor (VR) by a program operation. When the electrical path is created, the variable resistor (VR) may have a low resistance value, and when the electrical path is destroyed, the variable resistor (VR) may have a high resistance value. By utilizing the difference in resistance value of the variable resistor (VR), the variable resistance memory element may store data.

As another example, the variable resistor (VR) may include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistor (VR) is not limited thereto, and may include any variable resistor whose resistance value changes depending on an applied voltage.

The selection element (SW) may be a device based on a threshold switching phenomenon having a nonlinear (e.g., S-shaped) I-V curve. For example, the selection element (SW) may be an OTS (Ovonic Threshold Switch) device having bi-directional characteristics. That is, the selection element (SW) may include a material having an ovonic threshold switching characteristic in which resistance can change depending on the magnitude of a voltage applied across both ends of the selection element (SW). Accordingly, when a voltage smaller than a threshold voltage is applied to the selection element (SW), the selection element (SW) is in a high-resistance state, and when a voltage larger than the threshold voltage is applied to the selection element (SW), it is in a low-resistance state and current starts to flow. In addition, when a current flowing through the selection element (SW) becomes smaller than a holding current, the selection element (SW) can change into a high-resistance state.

According to embodiments of the present invention, the selection element (SW) may include chalcogenide compound layers (CM1, CM2, CM3) that are sequentially stacked and insulating blocks (IB1, IB2) formed at interfaces between the chalcogenide compound layers (CM1, CM2, CM3). This will be described in detail later.

Any memory cell (MC) can be addressed by selecting a first challenge line (CL1) and a second challenge line (CL2), and by applying a predetermined signal between the first challenge line (CL1) and the second challenge line (CL2), the memory cell (MC) is programmed, and by measuring a current value through the first challenge line (CL1), information according to the resistance value of a variable resistor constituting the corresponding memory cell (MC) can be read.

Referring to FIG. 2 below, a selection element according to embodiments of the present invention will be described in more detail.

FIG. 2 is a conceptual diagram illustrating a selection element according to embodiments of the present invention.

Referring to FIG. 2, a selection element (SW) according to embodiments of the present invention may include chalcogen compound layers (CM1, CM2, CM3) including a chalcogen compound as a material having ovonic threshold switching characteristics, and insulating blocks (IB1, IB2) formed at an interface between the chalcogen compound layers (CM1, CM2, CM3).

In detail, the selection element (SW) may include first to third chalcogen compound layers (CM1, CM2, CM3) sequentially stacked on a substrate (100), first insulating blocks (IB1) formed at an interface between the first and second chalcogen compound layers (CM1, CM2), and second insulating blocks (IB2) formed at an interface between the second and third chalcogen compound layers (CM2, CM3).

Each of the first to third chalcogen compound layers (CM1, CM2, and CM3) may include a quinary chalcogen compound including a chalcogen element including tellurium (Te) and selenium (Se) and a non-chalcogen element including silicon (Si), arsenic (As), and germanium (Ge). For example, each of the first to third chalcogen compound layers (CM1, CM2, and CM3) may include a quinary chalcogen compound in which 50 at% of a chalcogen element including tellurium (Te) and selenium (Se) is combined with 50 at% of a non-chalcogen element including silicon (Si), arsenic (As), and germanium (Ge).

In the present invention, the chalcogen elements and non-chalcogen elements constituting the quinary chalcogen compound can be implemented to exhibit optimal effects in terms of voltage drift, threshold voltage (Vth), Vth distribution, off current (Ioff), endurance, etc., for improving the reliability of a variable resistance memory device, along with securing required switching characteristics.

According to one embodiment, the chalcogen elements of the quinary chalcogen compound may be composed of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 to control switching characteristics and sneak current, and the non-chalcogen elements may be composed of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7 to prevent deterioration of device characteristics such as durability deterioration, drift increase, Ioff increase, and Vth dispersion increase, and to improve switching characteristics.

That is, the pentagonal chalcogen compound of the present invention can be composed of 50 at% of chalcogen elements consisting of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 and 50 at% of non-chalcogen elements consisting of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7.

Each of the chalcogen compound layers (CM1, CM2, CM3) can have a thickness of about 10 nm to 100 nm. In FIG. 2, three chalcogen compound layers (CM1, CM2, CM3) are laminated, but embodiments of the present invention are not limited thereto. In other embodiments, three or more chalcogen compound layers (CM1, CM2, CM3) may be laminated.

The insulating blocks (IB1, IB2) may include oxides and/or nitrides of elements included in each of the chalcogenide layers (CM1, CM2, CM3).

For example, the insulating blocks (IB1, IB2) may include oxides of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), nitrides of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), or mixtures of the oxides and nitrides. That is, the insulating blocks (IB1, IB2) may include tellurium oxide, selenium oxide, silicon oxide, arsenic oxide, and germanium oxide, or may include tellurium nitride, selenium nitride, silicon nitride, arsenic nitride, and germanium nitride, or may include mixtures of these oxides and nitrides.

The insulating blocks (IB1, IB2) may be formed by gathering nanoparticles of oxides and/or nitrides of elements included in the chalcogenide compound layers (CM1, CM2, CM3). The insulating blocks (IB1, IB2) may have, for example, a size (e.g., average particle diameter) of about 1 nm to about 5 nm.

In the present invention, the insulating blocks (IB1, IB2) can perform the function of limiting the flow of electrons within the chalcogenide layers (CM1, CM2, CM3).

In detail, the insulating blocks (IB1, IB2) act as traps, and the binding energy thereof may be greater than that of intrinsic traps having relatively small binding energy among intrinsic traps of the chalcogenide material. Here, the binding energy of the trap may mean the minimum energy required for an electron bound in the trap to escape the trap. The chalcogenide material may include intrinsic traps having different binding energies, and when a voltage is applied to the chalcogenide material, electrons in the chalcogenide material can move by repeatedly being bound to and escaping from adjacent traps along the direction in which the voltage is applied. In other words, when a voltage is applied to the chalcogenide material, electrons in the chalcogenide material can move by hopping between adjacent traps along the direction in which the voltage is applied.

Some of the electron migration paths within the chalcogenide layers (CM1, CM2, CM3) may be composed of intrinsic traps with small binding energies. These paths can serve as electron migration paths even under relatively low voltages, and thus may be the cause of leakage current.

Insulating blocks (IB1, IB2) can be added within the paths of the chalcogenide material, whereby the paths composed of intrinsic traps of the chalcogenide material having relatively small binding energies can be reduced. Through this, the insulating blocks (IB1, IB2) can block the flow of electrons moving under low voltage within the chalcogenide compound layers (CM1, CM2, CM3). As a result, the leakage current of the selection element (SW) can be reduced.

According to one embodiment, the first insulating blocks (IB1) and the second insulating blocks (IB2) may have different particle sizes (e.g., average particle diameters). For example, the particle size of the second insulating blocks (IB2) may be larger than the particle size of the first insulating blocks (IB1). As the first insulating blocks (IB1) and the second insulating blocks (IB2) have different particle sizes, the leakage current reduction effect may be further enhanced.

According to embodiments of the present invention, the chalcogen compound layers (CM1, CM2, CM3) can be formed through an atomic layer deposition (ALD) method. For example, the chalcogen compound layers (CM1, CM2, CM3) can be formed by alternately and repeatedly supplying a first source gas including a chalcogen element of tellurium (Te) and selenium (Se), a second source gas including silicon (Si), arsenic (As), and germanium (Ge), and a purge gas including an inert gas such as Ar or N ₂ .

Insulating blocks (IB1, IB2) can be formed by surface treating chalcogenide layers (CM1, CM2, CM3).

Specifically, the first insulating blocks (IB1) can be formed by surface-treating the first chalcogen compound layer (CM1). For example, the first insulating blocks (IB1) can be formed by heat-treating the first chalcogen compound layer (CM1) in an oxygen and/or nitrogen atmosphere or irradiating a laser onto the surface of the first chalcogen compound layer (CM1) in an oxygen and/or nitrogen atmosphere. Accordingly, the first insulating blocks (IB1) can be formed to include at least one of oxides and/or nitrides of elements included in the first chalcogen compound layer (CM1). Similarly, the second insulating blocks (IB2) can be formed by surface-treating the second chalcogen compound layer (CM2) in the same or similar manner as described above.

According to other embodiments, the selection element (SW) may further include an impurity (for example, at least one of C, N, B, and O). For example, the selection element (SW) may further include carbon (C) doped within each of the chalcogenide layers (CM1, CM2, CM3).

According to embodiments of the present invention, since chalcogen compound layers (CM1, CM2, CM3) having ovonic threshold switching characteristics are composed of 50 at% of chalcogen elements consisting of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 and 50 at% of non-chalcogen elements consisting of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7, they can have excellent phase change characteristics and excellent durability. In addition, since insulating blocks (IB1, IB2) functioning as traps that limit the movement of electrons are formed within the chalcogen compound layers (CM1, CM2, CM3), the flow of electrons moving under a low voltage can be effectively blocked, thereby reducing the leakage current of the selection element (SW).

As a result, it may be possible to provide a variable resistance memory device with improved electrical characteristics and switching characteristics.

Referring to FIGS. 3, 4a, and 4b below, an example of a variable resistance memory element according to embodiments of the present invention will be described.

FIG. 3 is a plan view showing a variable resistance memory element according to embodiments of the present invention. FIGS. 4a and 4b are cross-sectional views taken along lines I-I' and II-II' of FIG. 3, respectively.

Referring to FIGS. 3, 4A, and 4B, first conductive lines (CL1) and second conductive lines (CL2) may be sequentially provided on a substrate (100). The first conductive lines (CL1) may extend in a first direction (D1) substantially parallel to a top surface of the substrate (100) and may be spaced apart from each other in a second direction (D2) substantially parallel to the top surface of the substrate (100) and intersecting the first direction (D1). The second conductive lines (CL2) may extend in the second direction (D2) and be spaced apart from each other in the first direction (D1). The first conductive lines (CL1) and the second conductive lines (CL2) may be spaced apart from each other in a third direction (D3) perpendicular to the top surface of the substrate (100).

The substrate (100) may include a semiconductor substrate (100) such as a Si substrate (100), a Ge substrate (100), a Si-Ge substrate (100), a Silicon-on-Insulator (SOI) substrate (100), a Germanium-On-Insulator (GOI) substrate (100), etc. The substrate (100) may also include a III-V group compound such as InP, GaP, GaAs, GaSb, etc. Meanwhile, although not shown, a p-type or n-type impurity may be injected into the upper portion of the substrate (100) to form a well.

Each of the first and second challenge lines (CL1, CL2) may include a metal (e.g., copper, tungsten, or aluminum) and/or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

Although not illustrated, an insulating film (not illustrated) may be interposed on the substrate (100). In this case, the first conductive line (CL1) may be formed on the insulating film. In addition, a peripheral circuit (not illustrated) including a transistor, a contact, a wiring, etc. may be formed on the substrate (100). In addition, a lower insulating film (not illustrated) that at least partially covers the peripheral circuit may be formed on the substrate (100).

Memory cells (MC) may be arranged between first conductive lines (CL1) and second conductive lines (CL2), and may be respectively positioned at intersections of the first conductive lines (CL1) and second conductive lines (CL2). The memory cells (MC) may be two-dimensionally arranged along the first direction (D1) and the second direction (D2). The memory cells (MC) may form one memory cell stack (MCA). For convenience of explanation, only one memory cell stack (MCA) is illustrated, but a plurality of memory cell stacks may be stacked on the substrate (100) along the third direction (D3). In this case, structures corresponding to the first conductive lines (CL1), the second conductive lines (CL2), and the memory cells (MC) may be repeatedly stacked on the substrate (100).

Each of the memory cells (MC) may include a first electrode (EL1), a variable resistor (VR), an intermediate electrode (MEL), a selection element (SW) and a second electrode (EL2) connected in series between a pair of conductive lines (CL1, CL2) connected thereto.

The first electrode (EL1) may be in contact with the first conductive line (CL1), and the second electrode (EL) may be in contact with the second conductive line (CL2). Each of the first electrode (EL1) and the second electrode (EL2) may be formed of a noble metal such as Ir, Ru, Pd, Au, Pt, a metal oxide such as IrO2, a non-noble metal such as W, Ni, Al, Ti, Ta, TiN, TiW, TaN, or a conductive oxide such as IZO or ITO. Each of the first electrode (EL1) and the second electrode (EL2) may be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process, but the present invention is not limited thereto. In addition, the first electrode (EL1) and the second electrode (EL2) may be formed of the same or different materials.

A variable resistor (VR) may include a material that stores information based on changes in resistance.

According to some embodiments, the variable resistor (VR) may include a material capable of a reversible phase change between a crystalline and an amorphous state depending on the temperature. That is, the variable resistor (VR) may include a compound in which at least one of the chalcogen elements Te and Se is combined with at least one of Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. As an example, the variable resistor (VR) may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe. As another example, the variable resistor (VR) may have a superlattice structure in which layers including Ge and layers not including Ge are repeatedly stacked (for example, a structure in which GeTe layers and SbTe layers are repeatedly stacked). In this case, the memory cell can be provided as a memory cell of a phase change memory device (PRAM).

According to other embodiments, the variable resistor (VR) may include at least one of perovskite compounds or conductive metal oxides. For example, the variable resistor (VR) may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, and barium-strontium-zirconium oxide. As another example, the variable resistor (VR) may have a dual structure of a conductive metal oxide film and a tunnel insulating film, or a triple structure of a first conductive metal oxide film, a tunnel insulating film, and a second conductive metal oxide film. In this case, the tunnel insulating film may include aluminum oxide, hafnium oxide, or silicon oxide. In this example, the memory cell may be provided as a memory cell of a resistive random access memory (ReRAM).

The intermediate electrode (MEL) can electrically connect the variable resistance layer (VR) and the selection element (SW), and can prevent direct contact between the variable resistance layer (VR) and the selection element (SW). The intermediate electrode (MEL) can include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

The selection element (SW) may include sequentially stacked chalcogenide compound layers (CM1, CM2, CM3) and insulating insulating blocks (IB1, IB2) formed within the chalcogenide compound layers (CM1, CM2, CM3). Since the selection element (SW) has been described with reference to FIG. 3, a detailed description thereof will be omitted.

A laminated structure including a first electrode (EL1), a variable resistor (VR), an intermediate electrode (MEL), a selection element (SW), and a second electrode (EL2) laminated in sequence can be arranged at intersections between conductive lines (CL1, CL2) to form a two-dimensional array, as illustrated in FIGS. 3, 4a, and 4b.

A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover first electrodes (EL1), a variable resistance layer (VR), and intermediate electrodes (MEL) included in first conductive lines (CL1) and memory cells (MC). A second interlayer insulating film (120) may be provided on the first interlayer insulating film (110). The second interlayer insulating film (120) may cover selection elements (SW) and second electrodes (EL2) included in the memory cells (MC). The first and second interlayer insulating films (110, 120) may include at least one of silicon oxide, silicon nitride, and/or silicon oxynitride.

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments and application examples described above are exemplary in all respects and are not limiting.

Claims (3)

First challenge lines extending in the first direction;
Second challenge lines extending in a second direction intersecting the first direction; and
Including memory cells provided at each intersection between the first challenge lines and the second challenge lines,
Each of the above memory cells includes a variable resistor and a selection element connected in series between corresponding first and second conductive lines,
The above selection element comprises sequentially stacked chalcogen compound layers and insulating blocks formed at the interface between the chalcogen compound layers,
Each of the above chalcogen compound layers comprises a quinary chalcogen compound in which 50 at% of a chalcogen element including tellurium (Te) and selenium (Se) is combined with 50 at% of a non-chalcogen element including silicon (Si), arsenic (As) and germanium (Ge).
A variable resistance memory element, wherein each of the insulating blocks comprises an oxide of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), a nitride of tellurium (Te), selenium (Se), silicon (Si), arsenic (As), and germanium (Ge), or a mixture of the oxides and the nitrides. In the first paragraph,
The above pentagonal chalcogen compound is a variable resistance memory device including 50 at% of chalcogen elements consisting of tellurium (Te) and selenium (Se) in an atomic ratio of 1:4 to 5 and 50 at% of non-chalcogen elements consisting of silicon (Si), arsenic (As), and germanium (Ge) in an atomic ratio of 1:3 to 4:5 to 7. In the first paragraph,
The above chalcogen compound layers include a first chalcogen compound layer, a second chalcogen compound layer, and a third chalcogen compound layer, which are sequentially stacked,
The insulating blocks include first insulating blocks formed at an interface between the first chalcogen compound layer and the second chalcogen compound layer and second insulating blocks formed at an interface between the second chalcogen compound layer and the third chalcogen compound layer,
The first to third chalcogen compound layers have a thickness of 10 nm to 100 nm,
A variable resistance memory element wherein the first and second insulating blocks have a particle size of 1 nm to 5 nm, and the particle size of the second insulating blocks is larger than the particle size of the first insulating blocks.