KR102805119B1 - Device and method for staggered timing of skipped refresh operations - Google Patents

Abstract

Embodiments of the present disclosure relate to an apparatus and method for staggering the timing of skipped refresh operations on a memory. Memory cells of the memory must perform refresh operations periodically. In some cases, the auto-refresh operation may be skipped periodically when the charge retention characteristics of the memory cells of the memory exceed an auto-refresh frequency. To reduce peak current consumption during the refresh operation, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operations may be staggered in time across memory dies of the memory to limit the number of memory dies performing the auto-refresh operation to a maximum number. In another example, the skipped refresh operations may be staggered in time across memory banks of a single memory array to limit the number of memory banks performing the auto-refresh operation to a maximum number.

Description

Device and method for staggered timing of skipped refresh operations

Cross-reference to related application(s)

This application claims the benefit of U.S. Patent Application No. 16/432,604, filed June 5, 2019, under 35 U.S.C. § 119, which is incorporated herein by reference in its entirety for all purposes.

Information may be stored in individual memory cells of the memory as a physical signal (e.g., a charge on a capacitive element). The memory may be a volatile memory and the physical signal may decay over time (which may deteriorate or destroy the information stored in the memory cells). For example, the information in the memory cells may need to be refreshed periodically by rewriting the information to restore the physical signal to its initial value.

As the size of memory components decreases, the density of memory cells has increased significantly. An automatic refresh operation may be performed in which a sequence of memory cells is periodically refreshed. Repeated accesses to a particular memory cell or group of memory cells (often referred to as 'row hammer') may increase the data degradation rate of surrounding memory cells. In addition to the automatic refresh operation, it may be desirable to identify and refresh memory cells affected by the row hammer in a target refresh operation. The target refresh operation may occur with timing interspersed between the automatic refresh operations.

An exemplary device is described herein. The exemplary device includes a first memory die configured to receive a refresh signal and to perform an automatic refresh operation in response to a first activation of the refresh signal and to skip the automatic refresh operation in response to a second activation of the refresh signal, and a second memory die configured to receive the refresh signal and to skip the automatic refresh operation in response to the first activation of the refresh signal and to perform the automatic refresh operation in response to the second activation of the refresh signal. Additionally or alternatively, both the first memory die and the second memory die can be configured to simultaneously perform a target refresh operation in response to a third activation of the refresh signal. Additionally or alternatively, the first memory die can be configured to perform the automatic refresh operation on a plurality of rows of memory cells in response to a first activation of the refresh signal, and the second memory die can be configured to perform the automatic refresh operation on a plurality of rows of memory cells in response to a second activation of the refresh signal. Additionally or alternatively, the exemplary device can further include a memory package comprising a first memory die and a second memory die. Additionally or alternatively, the exemplary device can further include a memory module comprising the first memory die and the second memory die. Additionally or alternatively, the first memory die can be configured to determine whether to perform an automatic refresh operation or skip the refresh operation in response to activation of the refresh signal based on an internal setting. Additionally or alternatively, the internal setting is determined based on a value programmed in a fuse bank. Additionally or alternatively, the first memory die includes a refresh address control circuit configured to determine a pattern of the automatic refresh operation and the skipped refresh operation based on the internal setting.

Another exemplary device may include a memory array having a first memory bank and a second memory bank, and a refresh control circuit configured to receive a refresh signal. In response to a first activation of the refresh signal, the refresh control circuit may be configured to cause an auto-refresh operation to be performed on a group of rows of memory cells of the first memory bank and to cause the auto-refresh operation to be skipped for the second memory bank. In response to a second activation of the refresh signal, the refresh control circuit may be configured to cause the auto-refresh operation to be skipped on the first memory bank and to cause the auto-refresh operation to be performed on the group of rows of memory cells of the second memory bank. Additionally or alternatively, the refresh control circuit may be configured to cause the auto-refresh operation to be skipped on both the first bank and the second bank at the same frequency and different phases determined based on activation of the reset signal. Additionally or alternatively, the refresh control circuit can be configured to cause an auto refresh operation to be skipped for the first bank based on a first count value of a first counter having a predetermined value, and to cause an auto refresh operation to be skipped for the second bank based on a second count value of a second counter having the predetermined value. Each of the first counter and the second counter can be adjustable in response to a respective activation of the refresh signal. Additionally or alternatively, the refresh control circuit can be configured to initialize the first counter to a different count value than the second counter. Additionally or alternatively, in response to a third activation of the refresh signal, the refresh control circuit can be configured to cause a target refresh operation to be performed for row hammer attack victim rows of memory cells of the first memory bank, and to cause a target refresh operation to be performed for row hammer attack victim rows of memory cells of the second memory bank. Additionally or alternatively, in response to a third activation of the refresh signal, the refresh control circuit can be configured to cause an automatic refresh operation to be performed for a second group of rows of memory cells of the first memory bank and to cause a target refresh operation to be performed for a second group of rows of memory cells of the second memory bank.

An exemplary memory is described herein. The exemplary memory can include a plurality of memory cells, an interface configured to provide a refresh signal in response to a refresh command, a first refresh control circuit configured to receive the refresh signal, and a second refresh control circuit configured to receive the refresh signal. In response to a first activation of the refresh signal, the first refresh control circuit can be configured to cause a first type of refresh operation to be performed on a row of a first group of the plurality of memory cells, and in response to a second activation of the refresh signal, the first refresh control circuit can be configured to cause all refresh operations to be skipped for the first group of the plurality of memory cells. Additionally, in response to the first activation of the refresh signal, the second refresh control circuit can be configured to cause all refresh operations to be skipped for the second group of the plurality of memory cells, and further, in response to the second activation of the refresh signal, the second refresh control circuit can be configured to cause the first type of refresh operation to be performed for the rows of the second group of the plurality of memory cells. Additionally or alternatively, the memory can further include a memory die including a first memory bank and a second memory bank. The first memory bank can include a first group of the plurality of memory cells, and the second memory bank can include a second group of the plurality of memory cells. Additionally or alternatively, the memory can further include a first memory die including the first group of the plurality of memory cells and a second memory die including the second group of the plurality of memory cells. Additionally or alternatively, in response to a third activation of the refresh signal, the first refresh control circuit can be configured to cause a second type of refresh operation to be performed on a second row of the first group of the plurality of memory cells, and in response to a third activation of the refresh signal, the second refresh control circuit can be configured to cause a second type of refresh operation to be performed on a second row of the second group of the plurality of memory cells. Additionally or alternatively, the first type of refresh operation is an automatic refresh operation and the second type of refresh operation is a target refresh operation. Additionally or alternatively, the first refresh control circuit can be configured to cause all refresh operations to be skipped on the first group of the plurality of memory cells at the same frequency with respect to the activation of the refresh signal, such that the second refresh control circuit is configured to skip all refresh operations on the second group of the plurality of memory cells.

FIG. 1 is a block diagram of a semiconductor device according to one embodiment of the present disclosure.
FIG. 2 is a block diagram of a master/slave configuration of a memory package according to one embodiment of the present disclosure.
FIG. 3 is a block diagram of a memory array according to one embodiment of the present disclosure.
FIG. 4 is a block diagram of a memory module according to one embodiment of the present disclosure.
FIG. 5 is a block diagram of a refresh control circuit according to one embodiment of the present disclosure.
FIG. 6 is a block diagram of a row decoder according to one embodiment of the present disclosure.
FIG. 7 is an exemplary timing diagram of a refresh operation in a memory device according to an embodiment of the present disclosure.
FIG. 8 is an exemplary timing diagram of a refresh operation in a memory package or module according to an embodiment of the present disclosure.
FIG. 9 is a flowchart of a method for staggering refresh operations according to an embodiment of the present disclosure.

The following description of specific embodiments is merely illustrative in nature and is in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings, which form a part hereof and which illustrate, by way of illustration, specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the systems and methods disclosed herein, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Also, for the sake of clarity, detailed descriptions of certain features will not be discussed when they would be obvious to those skilled in the art so as not to obscure the description of embodiments of the present disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

A memory device may include a plurality of memory cells. The memory cells may store information and may be configured at the intersection of word lines (rows) and bit lines (columns). The word lines and bit lines may be configured as memory banks, and the memory device may include a single memory die or multiple memory dies. Each memory die may include multiple memory banks. In some examples, one or more memory dies may be configured as a memory package. In some embodiments, the memory dies of a memory package may be stacked on top of each other. In some embodiments, the multiple memory packages or multiple single die memory devices may be configured as a memory module. The memory device may receive one or more command signals that may indicate an operation on one or more of the dies of the one or more memory packages. The memory dies may be commonly coupled to the command signals, may receive commands from a master die and/or an interface chip, and/or may receive commands individually. For example, the memory dies in the package may receive a refresh signal that can control the timing of refresh operations on the memory dies.

In some instances, information in memory cells may decay over time. Memory cells may be refreshed on a row-by-row basis. During a refresh operation, information in one or more rows may be read and written back to each row. A refresh command (e.g., an auto refresh command (AREF)) may control the timing of the refresh operations. In some embodiments, the memory device may generate one or more "pumps," which may be activation of an internal refresh signal in response to receiving activation of a refresh command. The memory dies may perform more than one type of refresh operation in response to the refresh command and/or the refresh pumps. For example, the memory dies may skip all refresh operations (e.g., perform no refresh operations), perform an automatic refresh operation, or perform a targeted refresh operation. The memory die may have internal logic configured to determine the type of refresh operation to perform and/or may receive a signal (e.g., from an interface and/or a controller) indicating the type of refresh operation to be performed. In some examples, the memory dies may perform a combination of different operations during a single refresh command.

During an auto-refresh operation (e.g., initiated by activation of the auto-refresh command AREF and/or activation of the pump), the memory die may refresh groups of rows of the memory array. From one auto-refresh operation to the next, the groups of rows to be refreshed may be selected according to a predetermined sequence or pattern. The auto-refresh operation may cycle through and refresh all of the rows of the memory array of the memory die within a specified period of time to prevent data loss (e.g., each row may be refreshed within a specified maximum refresh time period). The specified maximum refresh time period may be based on a normal data degradation rate of the memory cells.

During a target refresh operation, a particular row or rows of memory cells in a memory array may be refreshed in response to detection of an attack on a particular row. Repeated accesses to a particular row of memory (e.g., an aggressor row) may increase the decay rate of adjacent rows (e.g., victim rows) due to, for example, electromagnetic coupling between the rows. Information within the victim rows may decay at a rate such that data may be lost if not refreshed until the next automatic refresh operation for those rows. To prevent information from being lost, it may be necessary to identify the aggressor row and then perform a target refresh operation on one or more associated victim rows. In some embodiments, the target refresh operation may "steal" a timeslot that would otherwise be used for an automatic refresh operation (e.g., by activating a pump, activating the AREF of an automatic refresh command).

In some examples, the auto-refresh commands AREF may be provided to the memory die at a higher frequency than is necessary to reliably maintain information stored in the memory cells of the memory die. Thus, in some examples, the charge retention characteristic of the memory cells of the memory die may allow refresh operations to be skipped periodically, which may reduce power consumption during such refresh cycles.

It may be important to control the amount of current consumed by a memory device during a refresh operation. Typically, an auto-refresh operation may consume more current than a target refresh operation, because more rows may be refreshed during a given auto-refresh operation than can be refreshed during a given target refresh operation. Therefore, if all memory banks in a memory die, or all memory dies in a group of memory dies in a memory package or module, perform auto-refresh operations simultaneously, the current consumed may in some instances exceed the defined current limit. As discussed above, one way to reduce current consumption is to periodically skip refreshes when possible. However, if all memory banks in a memory die, or all memory dies in a group of memory dies in a memory package or module, both skip refresh operations and perform auto-refresh operations simultaneously, the problem of excessive current consumption may persist.

The present disclosure relates to devices, systems and methods for staggering the timing of different types of refresh operations. Since skipped and target refresh operations use less current than automatic refresh operations, it may be desirable to reduce the number of memory dies (or memory banks of a single memory die) that simultaneously perform automatic refresh operations by having a first subset of memory dies (or a first subset of memory banks) perform an automatic refresh operation while a second subset of memory dies (or a second subset of memory banks) skips the refresh operation and performs the target refresh operation, or a combination thereof. For example, when a maximum number of memory dies (or memory banks) are performing refresh operations, some of the memory dies (or memory banks) may skip the refresh operation and/or some of the memory dies (or memory banks) may perform the target refresh operation rather than the automatic refresh operation. In an exemplary implementation, each of the memory dies can skip the refresh operation upon different activations of the refresh timing command (e.g., the auto-refresh command AREF and/or PUMP). Thus, a first memory die can skip the refresh operation and a second die can perform the auto-refresh operation in response to a first activation of the refresh timing signal, and the first memory die can perform the auto-refresh operation and the second die can skip the refresh operation in response to a second activation of the refresh timing signal.

FIG. 1 is a block diagram of a semiconductor device according to at least one embodiment of the present disclosure. The semiconductor device (100) may be a semiconductor memory device, such as a DRAM device, integrated into a single semiconductor chip. The exemplary device (100) of FIG. 1 may include a memory package, such as a stack (125) of memory dies positioned on a substrate (123), which may function (and may be referred to) as an interface. Although certain components are shown on the dies of the stack (125) and certain components are shown on the substrate (123), other arrangements of the components of the device (100) between the stack (125) and the substrate (123) are possible in other exemplary embodiments. In some embodiments, the stack (125) of the device (100) may include multiple dies. In other embodiments, the stack (125) may include a single die.

For simplicity and clarity of illustration, only components of one memory die of the stack (125) are illustrated in FIG. 1. In general, each of the different memory dies of the stack (125) may have similar components to one another. In some embodiments, each memory die of the stack (125) may be physically identical to one another. The substrate (123) may act as an interface, allowing the memory dies of the stack (125) to transmit and receive information (e.g., data, commands) to and from the outside while communicating with the components of the substrate. As described herein, commands and other signals transmitted by the substrate (123) may be transmitted to all of the memory dies of the stack (125) or may be individually addressed to individual memory dies of the stack (125).

The semiconductor device (100) includes a memory array (118). The memory array (118) may be positioned on a memory die of the stack (125). The memory array (118) is illustrated as including a plurality of memory banks BANK0-N, wherein the total count of the memory banks is 2, 4, 8, 16, etc., including any number therebetween and any number greater than 16. Each of the memory banks BANK0-N may include a plurality of word lines WL, a plurality of bit lines BL, /BL, and a plurality of memory cells MC arranged at the intersections of the plurality of word lines WL and the plurality of bit lines BL, /BL. Selection of the word line WL is performed by a row decoder (108), and selection of the bit lines BL and /BL is performed by a column decoder (110). Row and column decoders (108, 110) may also be located in the memory dies of the stack (125). In the embodiment of FIG. 1, the row decoder (108) includes a separate row decoder for each memory bank and the column decoder (110) includes a separate column decoder for each memory bank. The bit lines BL and /BL are connected to their respective sense amplifiers (SAMPs). Data read from the bit lines BL or /BL are amplified by the sense amplifiers SAMPs and transmitted to the read/write amplifiers (120) via complementary local data lines (LIOT/B), transmission gates (TG) and complementary main data lines (MIOT/B). Conversely, the write data output from the read/write amplifier (120) is transmitted to the sense amplifier SAMP through the complementary main data lines MIOT/B, the transmission gate TG, and the complementary local data lines LIOT/B, and is written to the memory cell MC connected to the bit line BL or /BL.

A semiconductor device (100) may employ a plurality of external terminals including a command and address (C/A) terminal connected to a command and address bus for receiving a command and address, a chip select (CS) terminal configured to receive a CS signal, a clock terminal for receiving clocks CK and /CK, a data terminal DQ for providing data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may be located on a substrate (123).

The clock terminal is provided with external clocks CK and /CK which are provided to the input circuit (112). The external clocks may be complementary. The input circuit (112) generates an internal clock ICLK based on the CK and /CK clocks. The ICLK clock is provided to the command decoder (110) and the internal clock generator (114). The internal clock generator (114) provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks may be used for timing operations of various internal circuits. The internal data clocks LCLK are provided to the input/output circuit (122) to time the operation of circuits included in the input/output circuit (122) for, for example, a data receiver, thereby timing the reception of write data.

The C/A terminals may be provided with memory addresses. The memory addresses provided to the C/A terminals are transmitted to the address decoder (104) via the command/address input circuit (102). The address decoder (104) receives the address and provides a decoded row address XADD to the row decoder (108) and a decoded column address YADD to the column decoder (110). The address decoder (104) may also provide a decoded bank address BADD, which may indicate a bank of the memory array (118) including the decoded row address XADD and the column address YADD. In some embodiments, the address decoder (104) may also indicate a particular memory die of the stack (125) for activation. The C/A terminals may be provided with a command. Examples of commands may include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, as well as other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD for indicating memory cell(s) to be accessed.

A command may be provided as an internal command signal to a command decoder (106) via a command/address input circuit (102). The command decoder (106) includes a circuit that decodes the internal command signal and generates various internal signals and commands for performing an operation. For example, the command decoder (106) may provide a row command signal for selecting a word line and a column command signal for selecting a bit line.

A semiconductor device (100) can receive an access command, which is a read command. When a read command is received and a bank address, a row address, and a column address (and an optional die address) are provided in time with the read command, read data is read from memory cells of a memory array (118) corresponding to the row address and the column address. The read command is received by a command decoder (106) which provides an internal command so that read data from the memory array (118) is provided to read/write amplifiers (120). The read data is output to the outside from data terminals DQ through an input/output circuit (122).

A semiconductor device (100) can receive an access command (e.g., a write command). When a write command is received and a bank address, a row address, and a column address (and an optional memory die address) are provided in time with the write command, write data supplied to the data terminal DQ is written to memory cells of the memory array (118) corresponding to the row address and the column address. The write command is received by the command decoder (106), and in response, the command decoder (106) can provide an internal command that causes the write data to be received by data receivers of the input/output circuit (122). A write clock can also be provided to an external clock terminal to time the reception of the write data by the data receivers of the input/output circuit (122). The recording data is supplied to the read/write amplifier (120) through the input/output circuit (122), and supplied to the memory array (118) by the read/write amplifier (120) and written to the memory cell MC.

The semiconductor device (100) may also receive a command to perform a refresh operation. The refresh signal AREF may be a pulse signal that is activated when the command decoder (106) receives the refresh command. In some embodiments, the refresh command may be issued externally to the memory device (100). In some embodiments, the refresh command may be generated periodically by a component of the device. In some embodiments, the refresh signal AREF may also be activated when the external signal indicates a self-refresh entry command. The refresh signal AREF may be activated once immediately after the command input and then periodically activated at a desired internal timing cycle. Accordingly, the refresh operations may be automatically continued according to a predefined period. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and return to an IDLE state.

A refresh signal AREF is supplied to the refresh address control circuit (116). In some examples, each memory die of the stack (125) may include a separate refresh address control circuit (116) for each memory bank of the memory banks BANK0-N. In other examples, each memory die may include a single refresh address control circuit (116). In anticipation of a refresh operation, the refresh address control circuit (116) supplies a refresh row address RXADD to a row decoder (108) capable of refreshing a word line WL indicated by the refresh row address RXADD. The refresh address control circuit (116) controls the timing of the refresh operation and may select and provide the refresh address RXADD. The refresh address control circuit (116) can be controlled to change the details of the refresh address RXADD (e.g., the method of calculating the refresh address, the timing of the refresh address) or can operate based on internal logic.

During a refresh cycle, the memory die may skip a refresh operation, perform an auto refresh operation, perform a target refresh operation, or some combination thereof. Accordingly, during a skipped refresh operation, the refresh address control circuit (116) may not provide a refresh address RXADD. During an auto refresh operation or a target refresh operation, the refresh address control circuit (116) may provide one or more auto refresh addresses (e.g., auto refresh addresses) or target refresh addresses (e.g., victim addresses), respectively, as the refresh address RXADD. The auto refresh addresses may be part of a sequence of addresses provided based on activation of the auto refresh signal AREF. The refresh address control circuit (116) may cycle through the sequence of auto refresh addresses at a rate determined by the activation rate of the auto refresh signal AREF. As part of the automatic refresh operation, multiple addresses may be provided as refresh address RXADD. In some embodiments, a group or block of addresses may be entirely pointed to by refresh address RXADD, and the row decoder (108) may refresh the entire group or block of addresses.

The refresh address control circuit (116) may also determine target refresh addresses, which are addresses that need to be refreshed (e.g., victim addresses corresponding to victim rows) based on the access pattern of nearby addresses within the memory array (118) (e.g., attacker addresses corresponding to attacker rows). The refresh address control circuit (116) may selectively use one or more signals of the device (100) to calculate the target refresh address RXADD. For example, the refresh address RXADD may be calculated based on row addresses XADD provided by the address decoder. In some embodiments, the refresh address control circuit (116) may sample the current value of the row address XADD provided by the address decoder (104) and determine the target refresh address based on one or more of the sampled addresses.

The target refresh address may be based on the time-dependent characteristics of the row addresses XADD received from the address decoder (104). The refresh address control circuit (116) may sample the current row address XADD to determine its time-dependent characteristics. The sampling may occur intermittently with each sample collected based on random or semi-random timing. The refresh address control circuit (116) may use different methods to calculate the target refresh address based on the sampled row address XADD. For example, the refresh address control circuit (116) may determine whether a given row is an aggressor address and may calculate addresses corresponding to victim addresses of the aggressor address and provide them as the target refresh address. In some embodiments, more than one victim address may correspond to a given aggressor address. In this case, the refresh address control circuit may queue multiple target refresh addresses and provide them sequentially when it determines that a target refresh address should be provided. The refresh address control circuit (116) may provide the target refresh address immediately, or may queue the target refresh address to be provided later (e.g., the next time slot available for target refresh).

The refresh address RXADD may be provided with a timing corresponding to the timing of the refresh signal AREF. The refresh address control circuit (116) may have time slots corresponding to the timing of the refresh signal AREF, and may provide none, one or more refresh addresses RXADD during each time slot. In some embodiments, a refresh may be skipped, or a target refresh address may be issued (e.g., "steal") during a time slot that would otherwise be assigned to an automatic refresh address. In some embodiments, multiple refresh operations may be performed in response to activation of the refresh signal AREF. In this example, certain time slots may be reserved for certain types of refresh operations according to some predefined pattern. Based on the predefined pattern, the refresh address control circuit (116) may determine whether to provide the target refresh address, not provide the refresh address (e.g., a skipped refresh), or provide the automatic refresh address during a particular time slot. In some examples, the refresh address control circuit (116) may be configured to ignore the pattern, for example in response to a detected row hammer attack.

In some embodiments, the refresh address control circuit (116) may include logic, such as a state machine and/or a counter, that is used to determine whether to initiate a skipped refresh operation, an automatic refresh operation, or a targeted refresh operation. For example, the refresh address control circuit (116) may count the number of times the refresh signal AREF is activated with a counter, and may skip the refresh operation when the counter reaches a maximum value and 'rolls back' to a minimum value. The logic may also be coupled to settings, such as fuse settings, that may be used to change the operation of the logic in a given memory die. In other embodiments, the refresh operation sequence may occur over a number of refresh operation cycles.

Since more addresses may be provided as refresh address RXADD during an auto refresh operation than during a target refresh operation or a skipped refresh operation, the auto refresh operation may consume more current (e.g., more power) than the target refresh operation or the skipped refresh operation. To reduce the peak current consumed by the semiconductor device (100) at any particular point in time during a refresh operation, the skipped refresh and/or the target refresh operation may be staggered in time with the auto refresh operations between different memory dies of the stack (125) (and/or between different memory banks BANK0-N of the memory array (118) of a particular memory die). The different memory dies of the stack (125) may have a configuration that causes the skipped refresh operation and the auto refresh operation to occur at different times in the different memory dies (or in the different memory banks BANK0-N of the memory die). In one exemplary implementation, the refresh address control circuits (116) of different memory dies of the stack (125) may indicate a skipped refresh operation at a frequency based on a refresh signal (e.g., the skipped refresh operation may be performed in response to every nth activation of the refresh signal AREF). In another exemplary implementation, the refresh address control circuits (116) of a particular die of the stack (125) may indicate a skipped refresh operation for a corresponding memory bank of the memory banks BANK0-N at a frequency based on the refresh signal (e.g., the skipped refresh operation may be performed in response to every nth activation of the refresh signal AREF). Each of the memory dies (e.g., memory banks BANK0-N of the memory die) can perform skipped refresh operations at the same frequency, but the configuration (e.g., fuse settings) of each of the memory dies (or memory banks BANK0-N) can offset the phase of the skipped refresh operations.

As previously described, the timings of the skipped refresh operations may be staggered in time to reduce peak power consumed by the memory device (100) during a refresh operation. The configuration of the different memory dies (or the different memory banks BANK0-N of the memory dies) of the stack (125) may be configured such that when a maximum number of simultaneous refresh operations occur in one or more of the memory dies (or one or more of the memory banks BANK0-N), at least one of the memory dies (or at least one of the memory banks BANK0-N) performs a skipped refresh operation rather than an automatic refresh operation.

Power supply potentials VDD and VSS are supplied to the power terminals. Power supply potentials VDD and VSS are supplied to the internal voltage generation circuit (124). The internal voltage generation circuit (124) generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals. The internal potential VPP is mainly used in the row decoder (108), the internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array (118), and the internal potential VPERI is used in many peripheral circuit blocks.

Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. Power supply potentials VDDQ, VSSQ are supplied to the input/output circuit (122). The power supply potentials VDDQ, VSSQ supplied to the power supply terminals may be the same potentials as the power supply potentials VDD, VSS supplied to the power supply terminals in one embodiment of the present disclosure. The power supply potentials VDDQ, VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD, VSS supplied to the power supply terminals in another embodiment of the present disclosure. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input/output circuit (122) to prevent power noise generated in the input/output circuit (122) from being transmitted to other circuit blocks.

FIG. 2 is a block diagram of a master/slave configuration of a memory package (200) according to one embodiment of the present disclosure. The memory package (200) may be an implementation of the semiconductor device (100) and memory stack (125) of FIG. 1 in some embodiments. The memory package (200) is an example of one possible configuration of a memory die (and substrate/interface) for use in a memory device. The memory package (200) includes a package substrate (227) having terminals configured to transmit and receive information to and from other components external to the memory package (200). The memory package (200) may also include a master memory die (master die or master DRAM) (228) and a plurality of slave memory dies (slave die or slave DRAMs) (229a-c). The master die (228) transmits and receives signals to and from the substrate (227), and in turn provides and receives signals to and from the slave dies (229a-c). Although only a single stack of dies (228, 229a-c) is shown, in some embodiments the package substrate (227) may include multiple stacks of dies.

Embodiments that are generally similar in structure to the memory package (200) may be referred to as 3DS packages, and each die may generally be referred to as a logical rank. The memory package (200) of FIG. 2 illustrates an exemplary embodiment having four different memory dies connected by wire bonds (e.g., a master die (228) and three slave dies (229a-c)). In other exemplary embodiments, more or fewer memory dies may be used. For example, some memory stacks may include more than eight memory dies. In some examples, multiple memory dies in a stack may be bonded using through silicon vias (TSVs) or other techniques.

Each of the master die (228) and the slave memory dies (229a-c) may include one or more memory arrays (e.g., the memory array (118) of FIG. 1). The memory dies (228, 229a-c) may also include other components of the memory device, such as refresh address control circuits (e.g., the refresh address control circuit (116) of FIG. 1) and row and column decoders (e.g., 108 and 110 of FIG. 1), respectively. The other components of the memory device (e.g., components of the memory device (100) of FIG. 1, illustrated on the substrate (123)) may be distributed between the substrate (227) and the memory dies (228, 229a-c). In some embodiments, each of the master die (228) and the slave dies (229a-c) may be physically identical to one another.

A master die (228) may be coupled to a substrate (227) and a first slave die (229a). The first slave die (229a) may be coupled to the master die (228) and a subsequent slave die (229b), etc. The dies (228, 229a-c) may be coupled to each other (and to the substrate (227)) in a variety of ways. In some embodiments, the dies may be coupled together with wire bonds. In some embodiments, the dies may be coupled together using through-silicon vias (TSVs). In a 3DS package, there may be additional power constraints based on the peak power (and/or current) that can be drawn through the coupling between the dies (e.g., wire bonds and/or TSVs).

The substrate (227) may receive a refresh command configured to place the memory package (200) in a refresh state. In some embodiments, the command may specify which of the memory dies (228, 229a-c) are to be placed in the refresh state. While in the refresh state, each of the memory dies (228, 229a-c) may perform refresh operations (e.g., a skipped refresh operation, an auto refresh operation, and/or a targeted refresh operation). In some embodiments, in response to the refresh command, the memory package (200) may place only a subset or group (e.g., defined by logical rank) of the memory dies (228, 229a-c) into the refresh state at the same time. In some examples, a minimum amount of time may elapse after a logical rank begins performing a refresh operation before a subsequent logical rank may begin performing a refresh operation. Therefore, there may be at least a minimum timing offset between the first refresh operation of the first logical rank and the first refresh operation of the second logical rank.

While the memory package (200) is in a refresh mode, the substrate (227) may receive a refresh command and provide it to the master die (228). The master die (228) may decode the refresh command and provide a refresh signal AREF to the slave dies (229a-c) (as well as internal components of the master die (228)). The refresh signal may be activated periodically (e.g., raised to a high logic level). Each of the logical ranks may receive a refresh signal (e.g., AREF) from the substrate, which may be used to control the timing of refresh operations of the logical ranks. In some embodiments, the logical ranks (e.g., groups of memory dies (228 and 229a-c)) may perform one or more refresh operations in response to respective activations of the refresh signal. In some embodiments, the logical ranks may begin providing activation of the refresh pump signal in response to receiving the refresh signal, and may perform a refresh operation in response to activation of the refresh pump signal.

In some embodiments, each of the logical ranks may have at least one refresh address control circuit (e.g., 116 of FIG. 1 ) configured to determine whether an auto-refresh operation, a target refresh operation, or a skipped refresh operation will occur in each of the memory dies (228 and 229a-c) or in each of the individual memory banks of the memory dies (228 and 229a-c). Each of the logical ranks may include settings used to determine the timing of the skipped refresh, auto-refresh, and target refresh operations. For example, respective fuses of the memory dies (228, 229a-c) may be used to control the timing and/or pattern of different types of refresh operations of each of the memory dies (228, 229a-c) (or of the respective memory banks of the respective memory dies (228 and 229a-c)). For example, each of the memory dies (228 and 229a-c) (or each of the memory banks of the memory dies (228 and 229a-c)) can have a counter such that after a certain number of activations of the refresh signal (and/or the refresh pump signal), the memory dies (228, 229a-c) (or each of the memory banks of the memory dies (228, 229a-c)) can perform a skipped refresh operation or a targeted refresh operation instead of an automatic refresh operation. In some embodiments, the memory dies (228, 229a-c) (or each memory bank of the memory dies (228, 229a-c)) may perform skipped refresh operations at the same skipped refresh frequency (e.g., after counting the same number of activations of the refresh signal) and may perform target refresh operations at the same target refresh frequency (e.g., after counting the same number of activations of the refresh signal). However, each of the memory dies (228, 229a-c) (or each memory bank of the memory dies (228, 229a-c)) may be configured to offset the skipped refresh operations or the target refresh operations in time using a programmed configuration or setting (e.g., such as by changing an initial value of a count). Other embodiments may use other methods to timely stagger skipped refresh operations and/or timely stagger targeted refresh operations. The stagger may be relative to different memory dies of a logical rank, or the stagger may be relative to different memory banks within a single memory die.

In some embodiments, the master die (228) may determine the timing of the skipped refresh, auto refresh, and target refresh operations on the master die (228) and each of the slave dies (229a-c). For example, the master die (228) may provide a separate skipped refresh signal and a separate target refresh signal (e.g., low hammer refresh (RHR)) to each of the slave dies (229a-c). The master die (228) may include internal logic and may time when it provides each of the individual target refresh signals to their respective die. As an exemplary operation, when the master die (228) receives a first activation of a refresh signal, it may transmit a skipped refresh signal to the slave die (229a). When the master die (228) receives a second activation of the refresh signal, it can transmit the skipped refresh signal to the slave die (229b). When the master die (228) receives a third activation of the refresh signal, it can transmit the skipped refresh signal to the slave die (229c). Upon subsequent activations of the refresh signal, the master die (228) can repeat the cycle again. In other exemplary embodiments, other operating methods and/or skipped refresh patterns may be used. In other embodiments, each of the memory dies (228, 229a-c) may include control logic for selecting a group of memory banks within the memory dies (e.g., the master die (228) and the slave dies (229a-c)) at which to perform the skipped refresh operation during each cycle.

In some embodiments, refresh timing settings that control the timing of the skipped refresh, auto-refresh, and target refresh operations may be determined when the memory package (200) is assembled. In some embodiments, the timing settings may be determined based on the placement of the memory dies (228, 229a-c) relative to one another (e.g., a slave die (229a) may have a particular timing setting based on a count of the memory dies it is away from the master die (228), etc.). In some other exemplary architectures, the memory dies (228, 229a-c) of the memory package (200) may each receive all commands directly from the package substrate (227), without going through the master die (228). The operation of these memory packages may be similar to the operation of the described memory package (200), with the individual memory dies being configured (e.g., programmed) to stagger the skipped refresh operations across other memory dies or across other banks within a memory die. Staggering the skipped refresh operations and the auto-refresh operations across multiple memory dies or across memory banks within a memory die may reduce peak current consumption compared to performing the auto-refresh operation simultaneously across all memory dies or across all memory banks within a memory die.

FIG. 3 is a block diagram of a memory array (300) according to an embodiment of the present disclosure. In some embodiments, the memory array (300) may implement the memory array (112) of FIG. 1. The memory array (300) includes a plurality of memory banks (332 (0)-(15)) arranged in memory bank groups (330 (0)-(3)). The memory bank groups (330 (0)-(3)) may be physically separated from each other by a peripheral area of a memory device (334). The exemplary memory array (300) of FIG. 3 includes four memory bank groups (330(0)-(3)), each of which includes individual memory banks of the memory banks (332(0)-(15)) (e.g., a total of sixteen total memory banks (332(0)-(15))), although other embodiments may have more or fewer memory banks (332(0)-(15)), and the memory banks may be organized into more or fewer memory bank groups (330(0)-(3)) with more or fewer memory banks per memory group. The memory banks (332(0)-(15)) and/or the memory bank groups (330(0)-(3)) may or may not be physically located next to one another.

Each of the memory banks (332 (0)-(15)) includes a number of wordlines and bitlines, and a number of memory cells are arranged at intersections. In some embodiments, additional configurations of rows (wordlines) and columns (bitlines) may exist within the memory banks (332 (0)-(15)). For example, each of the memory banks (332 (0)-(15)) may include a number of memory mats, each of which includes a number of rows and columns. The memory mats may be organized into sets of memory mats. In some embodiments, during an auto-refresh operation, an address may be provided that causes a wordline in a particular memory mat of each of the sets in each of the memory banks (332 (0)-(15)) to be refreshed.

In some embodiments, the refresh command may be issued commonly to all memory banks (332(0)-(15)), and all memory banks (332(0)-(15)) may perform refresh operations simultaneously. In some embodiments, the refresh command may be issued to direct a subset of the memory banks (332(0)-(15)). For example, a particular memory bank group (or groups) (330(0)-(3)) of the memory banks (332(0)-(15)) may initiate a refresh. In another example, some of the memory banks (332(0)-(15)) of each of the memory bank groups (330(0)-(3)) (or a subset of the groups) may initiate a refresh (e.g., the first memory banks (332(00), 332(10), 332(20), 332(30)) of each of the memory bank groups (330(0)-(3)). When a refresh command is issued to one or more of the memory banks (332(0)-(15)), each of the indicated memory banks of the memory banks (332(0)-(15)) may perform one or more refresh operations concurrently. The timing of the skip and auto refresh operations may be staggered across the indicated memory banks of the memory banks (332(0)-(15)), such that the memory Some of the indicated memory banks of the banks (332(0)-(15)) perform the skipped refresh operation simultaneously with some of the indicated banks of the memory banks (332(0)-(15)) performing the automatic refresh operation.

The indicated memory banks of the refreshed memory banks (332(0)-(15)) may have logic and/or programming configured to cause a first subset of the indicated memory banks to perform an automatic refresh operation while a second subset of the memory banks skip the refresh operation. In some embodiments, the logic/programming may be unique to the design of the memory array (300) rather than being based on settings programmed after the memory device is assembled.

Each of the memory banks (332(0)-(15)) may be associated with a refresh control circuit (e.g., 116 of FIG. 1) configured to issue a refresh address to the respective memory banks (332(0)-(15)). Each refresh control circuit may receive an activation of the refresh signal AREF and use internal logic to determine whether the provided refresh address should indicate an auto refresh operation, a target refresh operation, or a skipped refresh operation. For example, each refresh control circuit may count the number of auto refresh operations and perform the target refresh operation or the skipped refresh operation after a particular number of auto refresh operations have been performed. The counters of different refresh control circuits may be initialized to different values to stagger the skipped refresh operations across different memory banks.

FIG. 4 is a block diagram of a memory module (400) according to one embodiment of the present disclosure. One or more memory packages (e.g., or memory dies) (425 (0)-(8)) may be configured together as a memory module (400). The memory packages (425 (0)-(8)) may be included on one or both sides of the memory module (400). Each of the memory packages (425 (0)-(8)) may be any arrangement of memory packages, such as one or more of the memory device (100) of FIG. 1 , the memory package (200) of FIG. 2 , and/or the memory array (300) of FIG. 3 . In some embodiments, the memory packages (425 (0)-(8)) may all be the same type of memory package. In other embodiments, the memory packages (425 (0)-(8)) may include a mix of different types of memory packages that may be used. The controller (426) can provide various command signals to the memory packages (425(0)-(8)). In some examples, the memory module (400) can be configured as a dual in-line memory module (DIMM). In other examples, the memory module (400) can be configured as a non-volatile DIMM (NVDIMM) that includes a combination of volatile memory devices (e.g., DRAM) and non-volatile memory devices (e.g., flash memory) (not shown).

The memory module (400) illustrated in FIG. 4 has nine memory packages (425(0)-(8)), although more or fewer packages (425(0)-(8)) may be used in other embodiments. For example, in some embodiments, the memory packages (425(0)-(8)) may be organized into different physical ranks. For example, there may be a first physical rank on a first side of the module (400) (e.g., the nine memory packages (425(0)-(8)) shown in FIG. 4) and a second physical rank on a back side of the module (400) (e.g., nine additional memory packages on the back side of the module (400)). In some embodiments, there may be eighteen packages (425(0)-(8)) per physical rank, and the memory module (400) may have more than one physical rank. The memory module (400) may include a serial presence detect (SPD) chip (427) configured to provide information about the memory module (400), such as the number, rank, and memory type of memory packages (425(0)-(8)). The memory module (400) may further include a register (428) configured to store configuration information about the memory module (400), and a phase-locked loop (PLL) circuit (429) configured to control clock timing for the memory module (400).

Similar to spacing out the auto refresh, target refresh, and skipped refresh operations within the memory packages (425(0)-(8)) as described herein, it may also be desirable to manage refresh timing between the memory packages (425(0)-(8)) of the module (400). For brevity, similar components, structures, and/or operations to those previously described are not repeated. For example, one or more of the memory packages (425(0)-(8)) may enter a refresh mode in which one or more of the respective memory dies perform one of the auto refresh operation, the target refresh operation, or the skipped refresh operation. In addition to being staggered between memory dies of a given memory package (425(0)-(8)) or memory banks of a die of a given memory package, the target refresh operations and the skipped refresh operations may also be staggered between different packages (425(0)-(8)) of the memory module (400) to reduce peak current consumption.

FIG. 5 is a block diagram of a refresh address control circuit (516) according to an embodiment of the present disclosure. Specific internal components and signals of the refresh address control circuit (516) are shown to illustrate the operation of the refresh address control circuit (516). The dashed lines (532) are shown to indicate that in a particular embodiment, each of the components (e.g., the refresh address control circuit (516) and the row decoder (508)) may correspond to a particular bank of the memory array and that such components may be repeated for each of the memory banks of the memory array. In some embodiments, the components shown within the dashed lines (532) may be located in each of the memory banks. Thus, there may be multiple refresh address control circuits (516) and row decoders (508). For brevity, only components for a single memory bank will be described. In some embodiments, the refresh address control circuit (516) may implement the refresh address control circuit (116) of FIG. 1 and may be located in each memory die of the memory package.

An interface (531) (e.g., an external memory controller interface or a command decoder interface) may provide one or more signals to an address refresh control circuit (516) and a row decoder (508). The refresh address control circuit (516) may include a sample timing generator (538), an address sampler (537), a row hammer refresh (RHR) state controller (536), and a refresh address generator (539). The interface (531) may provide one or more control signals, such as an auto refresh signal AREF and a row address XADD. The refresh state control (536) may determine whether a skipped refresh operation, an auto refresh operation, or a target refresh operation is to be performed. The refresh state control (536) can represent different refresh operations in different memory banks or memory dies to stagger the skip, target, and auto refresh operations between the memory banks or memory dies. The refresh stagger circuit (535) can control the refresh state control (536) to stagger the skip, target, and auto refresh operations.

The refresh address control circuit (516) illustrates components associated with a particular implementation for detecting an attacker address by sampling incoming values of row address XADD at random or semi-random timing. Other methods for detecting an attacker address may be used in other embodiments, and other components may be provided in the refresh address control circuit (516).

The address sampler (537) may sample (e.g., latch) the current row address XADD in response to activation of ArmSample. The address sampler (537) may also provide one or more of the latched addresses as a matching address HitXADD to the refresh address generator (539). The refresh state control (536) may provide a RHR signal to indicate that a row hammer refresh (e.g., a refresh of victim rows corresponding to the identified attacker row) operation should occur. The refresh state control (536) may also provide an internal refresh signal IREF to indicate that an automatic refresh operation should occur and a no signal (or skip signal SKIP) when a refresh operation should not occur. The refresh state control (536) may be used to control the timing of the skipped refresh operations, the target refresh operations, and the automatic refresh operations. Activation of the SKIP, IREF and RHR signals may indicate activation of the pump signal. FIG. 5 shows the SKIP signal for clarity, and an actual implementation may not include this signal. Rather, for a skipped refresh operation, the refresh state control (536) may keep the IREF and RHR signals inactive to indicate a skipped refresh operation.

There may be a refresh state control (536) for each of the different banks. Each refresh state control (536) may include internal logic configured to determine the timing of providing signals (e.g., SKIP, IREF, or RHR) to indicate whether a skipped, automatic, or targeted refresh operation is to be performed on the associated memory bank. In some embodiments, each refresh state control (536) may include one or more counters and may provide the SKIP or RHR signal based on the number of occurrences of the refresh signal AREF (and/or the number of occurrences of the IREF signal). In an example where the skipped refresh operations or the targeted refresh operations are staggered across the memory dies of a memory package or module, each of the different memory banks of a single memory die may be initialized to the same value to align the refresh operations for the single memory die, with some memory dies being initialized to different values. Thus, each refresh state control (536) can generate the same pattern of skipped, target and auto refresh operations, but these patterns can be out of phase with one another so as to be staggered in time. In some examples, the refresh state control (536) can be coupled to (and/or can include) settings, such as fuse settings that are memory die specific. In some embodiments, the refresh state control (536) can include a counter and can provide a SKIP signal or an RHR signal based on the number of times the refresh signal AREF has been activated. In some embodiments, the fuse setting can control the initial value of the counter in the refresh state control (536). In this manner, different patterns of SKIP, RHR, and IREF signals can be generated in different memory dies (and/or different packages of the module) to stagger the timing of the target refresh operations.

In an example where skipped refresh operations or target refresh operations are staggered across memory banks of a single die of memory, a counter in each of the different memory banks' respective refresh state controls (536) may be initialized to a different value to stagger the refresh operations. Thus, each refresh state control (536) may generate the same pattern of target and auto refresh operations, but these patterns may be out of phase with each other so as to be staggered in time. In some embodiments, the refresh stagger circuit (535) may provide a signal to the refresh state control circuit (536) to control the staggering. For example, the refresh stagger circuit (535) may provide a signal to each of the different memory banks' respective refresh state controls (536) that may indicate when a target refresh operation should be performed. In some embodiments, there may be a single refresh stagger circuit (535) connected to all refresh address control circuits (516) for different banks. The refresh stagger circuit (535) may include internal logic (e.g., counters initialized to different values) that allows for directing staggering between different memory banks.

In response to activation of RHR, the refresh address generator (539) may provide a refresh address RXADD, which may be an automatic refresh address or one or more victim addresses corresponding to victim rows of an attacker row corresponding to the match address HitXADD. The row decoder (508) may perform a refresh operation in response to the refresh address RXADD and the row hammer refresh RHR signal. The row decoder (508) may perform the automatic refresh operation based on the refresh address RXADD and the internal refresh signal IREF. The row decoder (508) may not perform the refresh operation in response to a SKIP signal (e.g., in response to deactivation of both the RHR and IREF signals).

In some embodiments, the refresh address control circuit (516) may determine whether a refresh operation is not currently required (e.g., skip), or whether one or more target refresh operations are currently required. If a refresh is not currently required, the refresh address control circuit (516) may provide a SKIP signal (e.g., disable both the IREF and RHR signals). If a target refresh operation is currently required, the refresh address control circuit (516) may provide a target refresh address and enable the RHR signal.

Refresh address control circuits (516) associated with different banks may determine the number of target refresh operations to perform based on characteristics (e.g., number, frequency, and/or pattern) of accesses to the row addresses XADD. For example, a first refresh address control circuit (516) associated with a first bank that includes multiple rows being hammered may determine that more target refresh operations are needed than a second refresh address control circuit (516) associated with a second bank that includes fewer rows being hammered. In some embodiments, refresh operations may occur in cycles (e.g., a particular number of pumps and/or a particular number of AREF occurrences), and the refresh address control circuit (516) may determine the number of skipped refresh operations or the number of target refresh operations to perform in each cycle. The remaining refresh operations in the cycle may be used for automatic refresh operations. Different banks may determine a different number of skipped refresh operations to perform or a different number of target refresh operations, but in some examples, the skipped refresh operations may still be staggered across different banks and the target refresh operations may still be staggered across different banks. In another example, the skipped refresh operations may be aligned across all banks of a single die, but staggered across different dies.

The interface (531) may represent one or more components configured to provide signals to components of a memory bank (or banks). For example, the interface (531) may represent components such as the command address input circuit (102), the address decoder (105), and/or the command control (106) of FIG. 1. The interface (531) may provide a row address XADD, an auto-refresh signal AREF, an enable signal ACT, and a precharge signal PRE. The auto-refresh signal AREF may be a periodic signal that may indicate when an auto-refresh operation is to occur. The enable signal ACT may be provided to activate a given bank of memory. The precharge signal PRE may be provided to precharge a given bank of memory. The row address XADD may be a signal comprising multiple bits (which may be transmitted serially or in parallel) and may correspond to a particular row of the activated memory bank.

A sample timing generator (538) provides a sampling signal ArmSample. ArmSample can alternate between a low logic level and a high low level. Activation of ArmSample can be a 'pulse', where ArmSample rises to a high logic level and then falls back to a low logic level. The interval between pulses of ArmSample can be random, pseudo-random, and/or based on one or more signals of the device (e.g., AREF).

The address sampler (537) may receive a row address XADD from the interface (531) and an ArmSample from the sample timing generator (538). The row address XADD may change as the interface (531) directs access operations (e.g., read and write operations) to different rows of a memory cell array (e.g., the memory cell array (112) of FIG. 1). Whenever the address sampler (537) receives an activation (e.g., a pulse) of the ArmSample, the address sampler (537) may sample a current value of XADD. In some embodiments, the address sampler (532) may provide the currently sampled XADD value as a match address HitXADD. The refresh address generator (539) may provide one or more victim addresses associated with the match address HitXADD as a refresh address RXADD.

In some embodiments, in response to activation of ArmSample, the address sampler (537) may determine whether one or more rows are attacker rows based on the sampled row address XADD, and may provide the identified attacker rows as a match address HitXADD. As part of this determination, the address sampler (537) may record the current value of XADD (e.g., by latching and/or storing it in a register) in response to activation of ArmSample. The current value of XADD may be compared to addresses previously recorded to the address sampler (537) (e.g., addresses stored in latches/registers) to determine the access pattern of the sampled address over time. If the address sampler (537) determines that the current row address XADD is being accessed repeatedly (e.g., is an attacker row), activation of ArmSample may also cause the address sampler (537) to provide the address of the attacker row as a match address HitXADD. In some embodiments, the match address (e.g., the attacker address) HitXADD may be stored in a latch circuit for later retrieval by the refresh address generator (539). For example, the values of one or more match addresses HitXADD may be stored until the RHR signal indicates a target refresh operation.

The refresh state control (536) may receive an auto refresh signal AREF and provide a row hammer refresh RHR signal, an internal refresh signal IREF, or a SKIP signal (e.g., disabling both the RHR and IREF signals). The RHR signal may indicate that a target refresh operation should occur (e.g., one or more victim rows associated with the identified attacker HitXADD should be refreshed). The IREF signal may indicate that an auto refresh operation should occur. The SKIP signal (e.g., disabling both the RHR and IREF signals) may indicate that a skipped refresh operation should occur. The refresh state control (536) may use internal logic to provide the RHR signal. In some embodiments, the refresh state control (536) may include a counter and may provide the SKIP signal or the RHR signal based on a particular number of activations of the AREF. In some examples, the SKIP and RHR signals are associated with different counters. A counter (or counters) may be initialized to a particular value (e.g., when the memory is powered on). The particular value may vary from refresh control circuit to refresh control circuit between banks of memory dies and/or between different memory dies in a memory package or memory module.

The refresh state control (536) may provide an IREF signal to control the timing of the refresh operations. In some embodiments, the refresh state control (536) may activate the IREF signal multiple times for each activation of the refresh signal AREF. In some embodiments, the IREF signal may be used as a refresh pump signal to control activation of the refresh pumps. In some embodiments, each activation of the AREF signal may be associated with multiple activations of the IREF signal, which may be associated with multiple refresh operations, including a mix of target refresh operations, skipped refresh operations, and automatic refresh operations. For example, each activation of the IREF signal may be associated with a refresh operation for the refresh address RXADD, while the state of the RHR signal may determine whether the refresh address RXADD is associated with an auto refresh operation or a target refresh operation, and the state of the SKIP signal may determine whether the refresh address RXADD is associated with an auto refresh operation or a skipped refresh operation. In some embodiments, the IREF signal may be used to indicate that an auto refresh operation should occur, the RHR signal may be used to indicate that a target refresh operation should occur, and the SKIP signal may be used to indicate that no refresh operation should occur. For example, the SKIP, RHR and IREF signals can be generated such that they are not simultaneously active (e.g., not all (ALL) at a high logic level simultaneously), each activation of the SKIP signal can be associated with a skipped refresh operation, each activation of the IREF signal can be associated with an automatic refresh operation, and each activation of the RHR signal can be associated with a target refresh operation.

In some embodiments, the refresh state control (536) may count the activations of the IREF signal and use the activation (e.g., pump) count of the IREF signal to determine when the SKIP signal or the RHR signal should be provided. The counter may be initialized to different values for different refresh control circuits (516) in some examples. In other examples, the counter may be initialized to the same value within the die. In some embodiments, the refresh state control (536) may receive one or more signals from the refresh stagger circuit (535) configured to direct the different refresh state controllers (536) to provide the SKIP signal or the RHR signal. In this manner, the skipped or targeted refresh operations and the auto refresh operations may be staggered between banks of a die or between dies of a memory package.

The refresh address generator (539) may receive a row hammer refresh RHR signal and a match address HitXADD. The match address HitXADD may represent an aggressor row. The refresh address generator (539) may determine the location of one or more victim rows based on the match address HitXADD and provide the locations as refresh address RXADD. In some embodiments, the victim rows may include rows physically adjacent to the aggressor row (e.g., HitXADD+1 and HitXADD-1). In some embodiments, the victim rows may also include rows physically adjacent to rows physically adjacent to the aggressor row (e.g., HitXADD+2 and HitXADD-2). Other relationships between the victim rows and the identified aggressor rows may be used in other examples.

The refresh address generator (539) can determine the value of the refresh address RXADD based on the RHR signal and, in some examples, the SKIP signal. In some embodiments, when the RHR signal (and the SKIP signal) are not active, the refresh address generator (539) can provide one of the sequences of automatic refresh addresses as the refresh address RXADD. When the RHR signal is active (and the SKIP signal is not active), the refresh address generator (539) can provide a target refresh address, such as a victim address, as the refresh address RXADD.

The row decoder (508) may perform one or more operations on the memory array (not shown) based on the received signals and addresses. For example, in response to an enable signal ACT and a row address XADD (and IREF, SKIP and/or RHR signals being at a low logic level), the row decoder (508) may direct one or more access operations (e.g., a read operation) to the specified row address XADD. In response to an active RHR signal, the row decoder (508) may refresh a refresh address RXADD.

FIG. 6 is a block diagram of a row decoder (600) according to one embodiment of the present disclosure. The row decoder (600) may be included in the row decoder (108) of FIG. 1 in some embodiments of the present disclosure. The row decoder (600) may determine whether to activate a word line of a memory bank (e.g., a bank of the memory array (118) of FIG. 1) corresponding to a row address XADD or a refresh address RXADD.

As illustrated in FIG. 6, the row decoder (600) has a row enable timing generator (642), which receives an internal refresh signal IREF and a row hammer refresh RHR signal, an enable signal ACT and a pre-charge signal Pre, and provides a status signal RefPD, a word line enable signal wdEn, a sense amplifier enable signal saEn and a bit line equalization signal BLEQ. In some embodiments, the signals IREF and RHR may be an auto-refresh signal AREF. The status signal RefPD is supplied to a multiplexer (640), which selects one of the row address XADD or the refresh address RXADD. The address XADDi selected by the multiplexer (640) is supplied to a row redundancy control circuit (644). When a word line indicated by the address XADDi is replaced with a redundant word line, a hit signal RedMatch is activated, and a row address XADDd1 to be replaced is generated. Addresses XADDi and XADDd1 are supplied to a multiplexer (646); here, if the hit signal RedMatch is not activated, the address XADDi is selected; and if the hit signal RedMatch is activated, the address XADDd1 is selected. The selected address XADD2 is supplied to an X address decoder (648). The X address decoder (648) controls operations of a word line indicated by the address XADD2, a sense amplifier, an equalization circuit, and the like corresponding thereto, based on a word line enable signal wdEn, a sense amplifier enable signal saEn, and a bit line equalization signal BLEQ.

FIG. 7 is an exemplary timing diagram of refresh operations in a memory device according to an embodiment of the present disclosure. Timing diagram (700) shows refresh operations over time (along the x-axis) for memory banks BANK0-15. The memory banks may be memory banks BANK0-N described with reference to memory array (112) of FIG. 1 or memory banks 332(0)-(15) of FIG. 3. Timing diagram (700) illustrates an example of how skipped refresh operations may be staggered between memory banks BANK0-15. Other patterns of staggering skipped refresh operations between more or fewer banks may be used in other examples.

Timing diagram (700) illustrates an exemplary embodiment in which four refresh operations are performed in response to each activation of the refresh signal AREF. In particular, there may be three pumps in response to each activation of the AREF (e.g., activation of the pump signal in each refresh control circuit). Each of the pumps may be associated with a skipped refresh operation, an auto refresh operation, or a target refresh operation. The pumps are represented in the timing diagram (700) by vertical lines, and the line patterns identify the type of refresh operation. The pumps are grouped into three to represent three pumps per AREF activation. Thus, there is an activation of the AREF for each group of pumps. A solid line represents an auto refresh operation, a middle dotted line represents a skipped refresh operation, and a long dashed line represents a target refresh operation. As discussed herein, more wordlines in a bank may be refreshed simultaneously during an auto refresh operation than during a target refresh operation, and thus the auto refresh operation may consume more power than the target refresh operation. No wordlines may be refreshed during a skipped refresh operation.

A given bank can perform refresh operations in response to its respective pumps. Since the banks generate pumps in response to a commonly received refresh signal (e.g., AREF), the pumps can generally be synchronized. Thus, each of the memory banks BANK0-15 can perform a first pump simultaneously, then a second pump, etc. simultaneously. In response to each of the pumps, each of the banks can generally perform one of a skipped refresh operation, an auto refresh operation, or a target refresh operation. In the example illustrated in timing diagram (700), two different refresh operation sequences are illustrated for AREF activation. In a first exemplary sequence, the auto refresh operation is performed in response to the first pump, the first target refresh operation is performed in response to the second pump, and the second target refresh operation is performed in response to the third pump. In a second exemplary sequence, the skipped refresh operation is performed in response to the first pump, the first target refresh operation is performed in response to the second pump, and the second target refresh operation is performed in response to the third pump.

In the exemplary timing diagram (700), each of the memory banks BANK0-15 may alternate between the first exemplary sequence and the second exemplary sequence with each AREF activation. However, during a single AREF activation, the skipped and auto refresh operations among the memory banks BANK0-15 are staggered between the banks such that a first group of memory banks of the memory banks BANK0-15 performs the auto refresh operation concurrently with a second group of memory banks of the memory banks BANK0-15 performing the skipped refresh operation. For example, during an AREF activation received at time T0, memory banks BANK0-7 can perform a first exemplary sequence (e.g., auto refresh, first target refresh, second target refresh) and memory banks BANK8-15 can perform a second exemplary sequence (e.g., skipped refresh, first target refresh, second target refresh). During an AREF activation received at time T1, memory banks BANK0-7 can perform a second exemplary sequence (e.g., skipped refresh, first target refresh, second target refresh) and memory banks BANK8-15 perform the first exemplary sequence (e.g., auto refresh, first target refresh, second target refresh). These two AREF activation cycles or patterns can be repeated in the exemplary timing diagram (700) for every two AREF activations (e.g., starting at time T2, etc.). By performing auto-refresh on only half of the memory banks BANK0-15 at a given time, peak current consumption can be reduced compared to an implementation where all memory banks perform auto-refresh operations simultaneously.

The memory banks BANK0-15 of FIG. 7 are illustrated as having a refresh cycle with the same number of pumps generated in response to each AREF. In some embodiments, the refresh cycle may be longer or shorter than the number of pumps generated in response to each AREF. Similarly, the exemplary timing diagram (700) of FIG. 7 shows that each group of pumps includes a mixture of target refresh operations and skip or auto refresh operations. In some embodiments, a bank may perform only one type of refresh operation in response to a given AREF. The first and second exemplary sequences illustrated in FIG. 7, and the repeating cycle of every two AREF activations, are exemplary. Without departing from the scope of the present disclosure, more than two refresh operation sequences (e.g., any number such as 3, 4, 6, 8, 16, 32, etc.) may be implemented for a given AREF activation, each AREF activation may include more than three pumps (e.g., 4, 5, 6, etc.), and/or a repeat cycle may be implemented to occur after more than two AREF activations (e.g., after any number such as 3, 4, 6, 8, 16, 32, etc.).

FIG. 8 is an exemplary timing diagram (800) of a refresh operation in a memory package or module according to an embodiment of the present disclosure. The timing diagram (800) shows refresh operations over time (along the x-axis) for memory dies DIE0-7. The memory dies DIE0-7 may be dies of the stack (125) described with reference to the semiconductor device (100) of FIG. 1, the master die (228) and/or the slave dies (229a-c) of FIG. 2, and/or the memory packages (425(0)-(8)) of the memory module (400) of FIG. 4. The timing diagram (800) illustrates an example of how skipped refresh operations may be staggered between the memory dies DIE0-7. Other patterns of staggering the skipped refresh operations between more or fewer memory dies may be used in other examples.

The timing diagram (800) illustrates an exemplary embodiment in which three refresh operations are performed in response to each activation of the refresh signal AREF. In particular, there may be three pumps (e.g., pump signal activations in each refresh control circuit) in response to each activation of the AREF, and each of the pumps may be associated with a skipped refresh operation, an auto refresh operation, or a target refresh operation. The pumps are represented in the timing diagram (800) as vertical lines, and the line patterns identify the type of refresh operation. The pumps are grouped into three to represent three pumps per AREF activation. Thus, there is an activation of the AREF for each group of pumps. The solid lines represent an auto refresh operation, the middle dashed lines represent a skipped refresh operation, and the long dashed lines represent a target refresh operation. As discussed herein, more wordlines in the banks may be refreshed simultaneously during an auto refresh operation than during a target refresh operation, and thus the auto refresh operation may consume more power than the target refresh operation. No wordlines are refreshed during a skipped refresh operation.

A given memory die of the memory dies DIE0-7 may perform a refresh operation in response to each of the pumps. Since the memory dies DIE0-7 generate pumps in response to a commonly received refresh signal (e.g., AREF), the pumps may generally be synchronized. Thus, each of the memory dies DIE0-7 may perform a first pump concurrently and then a second pump concurrently. In response to each of the pumps, each of the memory dies DIE0-7 may generally perform one of a skipped refresh operation, an auto refresh operation, or a target refresh operation. In the example illustrated in timing diagram (800), two different refresh operation sequences are illustrated for AREF activation. In a first exemplary sequence, the auto refresh operation is performed in response to a first pump, a first target refresh operation is performed in response to a second pump, and a second target refresh operation is performed in response to a third pump. In a second exemplary sequence, the skipped refresh operation is performed in response to the first pump, the first target refresh operation is performed in response to the second pump, and the second target refresh operation is performed in response to the third pump.

In the exemplary timing diagram (800), each of the memory dies DIE0-7 can alternate between the first exemplary sequence and the second exemplary sequence with each AREF activation. However, during a single AREF activation, among the memory dies DIE0-7, the skipped and auto refresh operations are staggered among the memory dies DIE0-7 such that a first group of memory dies of the memory dies DIE0-7 perform the auto refresh operation concurrently with the second group of memory dies of the memory dies DIE0-7 performing the skipped refresh operation. For example, during an AREF activation received at time T0, memory dies DIE0-3 can perform the first exemplary sequence (e.g., auto refresh, first target refresh, second target refresh) and memory dies DIE4-7 can perform the second exemplary sequence (e.g., skipped refresh, first target refresh, second target refresh). During an AREF activation received at time T1, memory dies DIE0-3 may perform a second exemplary sequence (e.g., skipped refresh, first target refresh, second target refresh) and memory dies DIE4-7 may perform a first exemplary sequence (e.g., auto refresh, first target refresh, second target refresh). These two AREF activation cycles or patterns may be repeated every two AREF activations in the exemplary timing diagram (800) (e.g., starting at time T2, etc.). By performing the auto refresh for only a subset of memory dies DIE0-7 at a given time, peak current consumption may be reduced compared to an implementation where all memory banks perform the auto refresh operation simultaneously.

The memory dies DIE0-7 of FIG. 8 are illustrated as having a refresh cycle with an equal number of pumps generated in response to each AREF. In some embodiments, the refresh cycle may be longer or shorter than the number of pumps generated in response to each AREF. Similarly, the exemplary timing diagram (800) of FIG. 8 shows that each group of pumps includes a mixture of target refresh operations and skip or auto refresh operations. In some embodiments, a memory die may perform only one type of refresh operation in response to a given AREF. The first and second exemplary sequences illustrated in FIG. 8, and the cycle that repeats for every two AREF activations, are exemplary. Without departing from the scope of the present disclosure, it will be appreciated that for a given AREF activation, more than two refresh operation sequences may be implemented (e.g., any number such as 3, 4, 6, 8, 16, 32, etc.), each AREF activation may include more than three pumps (e.g., 4, 5, 6, etc.), and/or a repeat cycle may be implemented to occur after more than two AREF activations (e.g., after any number such as 3, 4, 6, 8, 16, 32, etc.).

While this application has described a method for reducing peak current consumption during a refresh operation within a non- volatile memory architecture, it should be appreciated that similar approaches may be implemented in other types of semiconductor devices and in other situations that include non-volatile memory devices. For example, the configuration of other types of periodic maintenance functions within a memory device/package/module may be staggered in a similar manner to reduce peak power within each device or set of devices. Other types of periodic maintenance functions may include error correcting code maintenance (e.g., ECC error checking and scrub procedures), wear leveling, or other targeted restoration of data within a set of storage array containers following a destructive access other than row hammer.

FIG. 9 is a flowchart of a method (900) for staggering refresh operations according to an embodiment of the present disclosure. The method (900) may be performed by a circuit of the semiconductor device (100) of FIG. 1, the memory package (200) of FIG. 2, the memory array (300) of FIG. 3, the memory module (400) of FIG. 4, the refresh stagger circuit (535) and/or the refresh address control circuit (516) of FIG. 5, the row decoder (600) of FIG. 6, or a combination thereof. Note that the method (900) may be performed to stagger auto-refresh operations across different memory dies (e.g., of a memory package or module), to stagger auto-refresh operations across different memory banks within a single memory die, or a combination thereof.

The method (900) may include receiving a refresh signal at a first memory die (or bank) and a second memory die (or bank) at 910. In some examples, the first and second memory dies include any of the memory dies of the stack (125) of FIG. 1, any of the master memory die (228) or the slave memory dies (229a-c) of FIG. 2, any of the memory packages (425(0)-(8)) of FIG. 4, or any combination thereof. In some examples, the first and second memory dies may be included in a memory package, such as the memory package (200) of FIG. 2. In some examples, the first and second memory dies may be included in a memory module, such as the memory module (400) of FIG. 4. In embodiments where the method (900) is performed with first and second memory banks, the first and second memory banks may correspond to any of the memory banks BANK0-N (or individual groups of memory cells) of the memory array (118) of FIG. 1, each memory bank of any one of the master memory die (228) or the slave memory dies (229a-c) of FIG. 2, any of the memory banks (332(0)-(15)) of FIG. 3, each memory bank of a memory die of any of the memory packages (425(0)-(8)) of FIG. 4, or a combination thereof.

In some examples, the method (900) may include determining, in the first memory die (or the second memory die), whether to perform an automatic refresh operation or skip a refresh operation in response to activation of a refresh signal based on internal settings. In an example, the internal settings are programmed into a fuse bank. In some examples, the determination may include determining a pattern of automatic refresh operations and skipped refresh operations based on the internal settings. The determination may be made via a refresh stagger circuit or a refresh address control circuit, such as the refresh stagger circuit (535) and/or the refresh address control circuit (516) of FIG. 5.

The method (900) may include, at 920, performing an automatic refresh operation on a first memory die (or bank) and skipping an automatic refresh operation on a second memory die (or bank), in response to a first activation of the refresh signal. In some examples, performing the automatic refresh operation on the first memory die includes performing the automatic refresh operation on a plurality of rows of memory cells.

The method (900) may include, at 930, in response to a second activation of the refresh signal, skipping an auto-refresh operation on the first memory die (or bank) and performing an auto-refresh operation on the second memory die (or bank). In some examples, performing the auto-refresh operation on the second memory die includes performing the auto-refresh operation on a plurality of rows of memory cells. In some examples, the method (900) may further include, in response to a third activation of the refresh signal, performing target refresh operations simultaneously on both the first memory die and the second memory die. The method (900) illustrated in FIG. 9 is exemplary and may include additional steps, and the steps may be performed in a different order than illustrated.

Of course, it will be appreciated that any one of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and/or processes, or may be separated and/or performed between separate devices or device portions according to the present systems, devices and methods.

The foregoing description of specific embodiments is illustrative in nature and is in no way intended to limit the scope of the present disclosure or its application or uses. In this detailed description of embodiments of the present systems and methods, reference is made to the accompanying drawings, which form a part hereof and which illustrate, by way of illustration, specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, and it is to be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the sake of clarity, the detailed description of certain features may not be discussed when they would be apparent to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. Accordingly, the foregoing detailed description is not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

Finally, the above discussion is intended to be illustrative only of the present system and should not be construed as limiting the scope of the appended claims to any particular embodiment or group of embodiments. Accordingly, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader spirit and scope of the present system as set forth in the following claims. Accordingly, the specification and drawings are to be regarded in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims (20)

In the device,
A first memory die including a first refresh control circuit, wherein the first refresh control circuit is configured to receive a refresh signal and, in response to a first activation of the refresh signal, cause an auto-refresh operation to be performed for the first memory die and, in response to a second activation of the refresh signal, cause the auto-refresh operation to be skipped for the first memory die, and the first memory die is further configured to perform a targeted refresh operation in response to a third activation of the refresh signal; and
A device comprising a second memory die including a second refresh control circuit, the second refresh control circuit being configured to receive the refresh signal and, in response to the first activation of the refresh signal, cause an auto refresh operation to be skipped for the second memory die and, in response to the second activation of the refresh signal, cause an auto refresh operation to be performed for the second memory die, the second memory die being further configured to perform a target refresh operation in response to a third activation of the refresh signal, the target refresh operation being performed simultaneously in the first and second memory dies. delete A device in accordance with claim 1, wherein the first memory die is configured to perform the automatic refresh operation on a plurality of rows of memory cells in response to the first activation of the refresh signal, and the second memory die is configured to perform the automatic refresh operation on a plurality of rows of memory cells in response to the second activation of the refresh signal. A device according to claim 1, further comprising a memory package including the first memory die and the second memory die. A device according to claim 1, further comprising a memory module including the first memory die and the second memory die. A device in accordance with claim 1, wherein the first memory die is configured to determine whether to perform the automatic refresh operation or skip the refresh operation in response to activation of the refresh signal based on an internal setting. A device in accordance with claim 6, wherein the internal settings are determined based on values programmed in a fuse bank. A device in accordance with claim 6, wherein the first memory die includes a refresh address control circuit configured to determine a pattern of automatic refresh operations and skipped refresh operations based on the internal settings. In the device,
A memory array having a first memory bank and a second memory bank;
A device comprising a refresh control circuit configured to receive a refresh signal, wherein in response to a first activation of the refresh signal, the refresh control circuit is configured to cause an automatic refresh operation to be performed for a group of rows of memory cells of the first memory bank and an automatic refresh operation to be skipped for the second memory bank, wherein in response to a second activation of the refresh signal, the refresh control circuit is configured to cause the automatic refresh operation to be skipped for the first memory bank and an automatic refresh operation to be performed for the group of rows of memory cells of the second memory bank, and wherein in response to a third activation of the refresh signal, the refresh control circuit is configured to cause a target refresh operation to be performed for a row hammer attack victim row of memory cells of the first memory bank and a target refresh operation to be performed for a row hammer attack victim row of memory cells of the second memory bank. In the 9th paragraph, the refresh control circuit is configured to skip the automatic refresh operation for both the first memory bank and the second memory bank at the same frequency and in different phases determined based on the activations of the reset signal. In the 10th paragraph, the refresh control circuit is configured to skip an automatic refresh operation for the first memory bank based on a first count value of a first counter having a predetermined value, and to skip an automatic refresh operation for the second memory bank based on a second count value of a second counter having the predetermined value, wherein each of the first counter and the second counter is adjustable in response to a respective activation of the refresh signal. In the 11th paragraph, the device is configured to initialize the first counter to a count value different from that of the second counter. delete A device in accordance with claim 9, wherein in response to the third activation of the refresh signal, the refresh control circuit is configured to cause an automatic refresh operation to be performed for a second group of rows of memory cells of the first memory bank, and to cause a target refresh operation to be performed for a second group of rows of memory cells of the second memory bank. In memory,
multiple memory cells;
An interface configured to provide a refresh signal in response to a refresh command;
a first refresh control circuit configured to receive the refresh signal, wherein in response to a first activation of the refresh signal, the first refresh control circuit is configured to cause a first type of refresh operation to be performed on a row of a first group of the plurality of memory cells, wherein in response to a second activation of the refresh signal, the first refresh control circuit is configured to cause all refresh operations to be skipped on the first group of the plurality of memory cells, and wherein in response to a third activation of the refresh signal, the first refresh control circuit is configured to cause a target refresh operation to be performed on the row of the first group of the plurality of memory cells; and
A memory comprising a second refresh control circuit configured to receive the refresh signal, wherein in response to the first activation of the refresh signal, the second refresh control circuit is configured to cause all refresh operations to be skipped for the second group of the plurality of memory cells, wherein in response to the second activation of the refresh signal, the second refresh control circuit is configured to cause the first type of refresh operation to be performed for the rows of the second group of the plurality of memory cells, and wherein in response to a third activation of the refresh signal, the second refresh control circuit is configured to cause a target refresh operation to be performed for the rows of the second group of the plurality of memory cells. A memory in accordance with claim 15, further comprising a memory die including a first memory bank and a second memory bank, wherein the first memory bank includes a first group of the plurality of memory cells, and the second memory bank includes a second group of the plurality of memory cells. A memory in claim 15, further comprising a first memory die including the first group of the plurality of memory cells and a second memory die including the second group of the plurality of memory cells. A memory in accordance with claim 15, wherein, in response to a third activation of the refresh signal, the first refresh control circuit is configured to cause a second type of refresh operation to be performed on a second row of the first group of the plurality of memory cells, and in response to the third activation of the refresh signal, the second refresh control circuit is configured to cause a second type of refresh operation to be performed on a second row of the second group of the plurality of memory cells. A memory in claim 18, wherein the first type of refresh operation is an automatic refresh operation, and the second type of refresh operation is a target refresh operation. In the 15th paragraph, the memory is configured to cause all refresh operations for the first group of the plurality of memory cells to be skipped at the same frequency for activations of the refresh signal according to the second refresh control circuit being configured to cause all refresh operations for the second group of the plurality of memory cells to be skipped.