KR102843697B1 - Power module - Google Patents

Abstract

The present invention relates to a power module, and includes a ceramic substrate (300') including a ceramic substrate (301) and a metal layer (302', 303') bonded to at least one surface of the ceramic substrate (301), wherein the metal layer (302', 303') has a curvature slope (350, 350', 350") formed at an edge, and the curvature slope (350, 350', 350") protrudes in the outer circumferential direction of the ceramic substrate (301). The present invention has an advantage in that it can secure a long lifespan and further improve the reliability of the power module by forming a curvature slope at the edge of the ceramic substrate to alleviate stress concentration.

Description

Power Module {POWER MODULE}

The present invention relates to a power module, and more particularly, to a power module whose performance is improved by applying a high-output power semiconductor chip.

Power modules are used to supply high-voltage current to drive motors in hybrid vehicles, electric vehicles, etc.

Among power modules, double-sided cooling power modules install substrates on the upper and lower sides of a semiconductor chip, each with a heat sink on its outer surface. Double-sided cooling power modules offer superior cooling performance compared to single-sided cooling power modules, which feature heat sinks on one side, and their use is gradually increasing.

Double-sided cooling power modules used in electric vehicles, etc., have power semiconductor chips such as silicon carbide (SiC) and gallium nitride (GaN) mounted between two substrates. Therefore, high heat generation and vibration during driving are generated due to high voltage. Therefore, it is important to satisfy both high strength and high heat dissipation characteristics to resolve these issues.

Patent Document 1: Patent Publication No. 1836658 (registered on March 2, 2018)

The purpose of the present invention is to provide a power module having high strength and high heat dissipation characteristics, excellent bonding characteristics, a reduced volume by minimizing the current path, and improved efficiency and performance.

Another object of the present invention is to provide a power module that secures long life and reliability by forming a curvature slope at the edge of a ceramic substrate to alleviate stress concentration.

According to a feature of the present invention for achieving the above-mentioned purpose, the present invention includes a lower ceramic substrate and an upper ceramic substrate spaced apart from each other on the upper side of the lower ceramic substrate and having a semiconductor chip mounted on the lower side, the upper ceramic substrate includes a ceramic substrate and a metal layer bonded to at least one surface of the ceramic substrate, the metal layer has a curvature slope formed at an edge, and the curvature slope protrudes in the outer circumferential direction of the ceramic substrate.

The curvature slope is formed in a concave shape in the direction of the ceramic substrate, and the protrusion length increases as it goes in the direction of the ceramic substrate.

The curvature slope may be a multi-stage structure in which multiple concave portions are formed and protrusions are formed at the points where the concave portions meet.

The protrusion may be pointed in shape.

The curvature slope may be a two-stage structure in which two concave portions are formed and a protrusion is formed at the point where the concave portions meet.

The curvature slope formed at the edge of the metal layer may be a combination of a single-stage structure formed in a concave shape in the direction of the ceramic substrate and a multi-stage structure formed with two or more concave portions in the direction of the ceramic substrate.

The curvature slope is formed by placing a photomask on one side of the metal layer and etching the metal layer exposed by the photomask.

The multi-stage structure of the curvature slope is formed by placing a photomask in which two or more holes are continuously formed on one side of the metal layer and etching the metal layer exposed by the photomask.

The ceramic substrate can be one of an AMB (Active Metal Brazing) substrate, a DBC (Direct Bonding Copper) substrate, a DBA (Direct Brazed Aluminum) substrate, and a TPC (Thick Printing Copper) substrate.

In addition, the ceramic substrate is a lower ceramic substrate and an upper ceramic substrate that is placed on top of the lower ceramic substrate and has a semiconductor chip mounted on the lower surface.

The present invention has high strength and high heat dissipation characteristics, excellent bonding characteristics, can reduce volume by minimizing the current path, and is optimized for high-speed switching, thereby improving efficiency and performance.

In addition, the present invention forms a single-stage or multi-stage curved slope at the edge of the ceramic substrate to alleviate stress concentration due to heat and stress concentration due to electrical shock, thereby securing a long lifespan of the ceramic substrate and further improving the reliability of the power module.

Figure 1 is a perspective view showing the shape of a power module according to an embodiment of the present invention.
Figure 2 is an exploded perspective view showing the shape of a power module according to an embodiment of the present invention.
Figure 3 is a cross-sectional side view of a power module according to an embodiment of the present invention.
Figure 4 is a perspective view showing a housing according to an embodiment of the present invention.
Fig. 5 is a perspective view for explaining a lower ceramic substrate according to an embodiment of the present invention.
Fig. 6 is a drawing showing the upper and lower surfaces of a lower ceramic substrate according to an embodiment of the present invention.
Fig. 7 is a perspective view for explaining an upper ceramic substrate according to an embodiment of the present invention.
Fig. 8 is a drawing showing the upper and lower surfaces of an upper ceramic substrate according to an embodiment of the present invention.
Fig. 9 is a perspective view showing a state in which a connecting pin is coupled to an upper ceramic substrate according to an embodiment of the present invention.
Fig. 10 is a plan view of a PCB substrate according to an embodiment of the present invention.
Figure 11 is an internal configuration diagram for explaining the power module structure according to an embodiment of the present invention.
Figure 12 is an internal configuration diagram for explaining the power module structure according to another embodiment of the present invention.
Fig. 13 is a cross-sectional view showing an upper ceramic substrate according to another embodiment of the present invention.
Figures 14 and 15 are process diagrams for explaining a method for manufacturing an upper ceramic substrate according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

Fig. 1 is a perspective view showing the shape of a power module according to an embodiment of the present invention, and Fig. 2 is an exploded perspective view showing the shape of a power module according to an embodiment of the present invention.

As illustrated in FIGS. 1 and 2, a power module (10) according to an embodiment of the present invention is an electronic component in the form of a package formed by accommodating various components forming the power module in a housing (100). The power module (10) is formed in a form in which a substrate and components are placed and protected within the housing (100).

A power module (10) may include a plurality of substrates and a plurality of semiconductor chips. The power module (10) according to an embodiment includes a housing (100), a lower ceramic substrate (200), an upper ceramic substrate (300), a PCB substrate (400), and a heat sink (500).

The housing (100) has a centrally opened, vertically open space, and a first terminal (610) and a second terminal (620) are positioned on both sides. In the centrally opened space, the housing (100) has a heat sink (500), a lower ceramic substrate (200), an upper ceramic substrate (300), and a PCB substrate (400) sequentially stacked at a predetermined vertical interval, and a support bolt (630) for connecting an external terminal to the first terminal (610) and the second terminal (620) on both sides is fastened. The first terminal (610) and the second terminal (620) are used as input/output terminals of a power source.

As illustrated in FIG. 2, the power module (10) sequentially accommodates a lower ceramic substrate (200), an upper ceramic substrate (300), and a PCB substrate (400) in the central empty space of the housing (100). Specifically, a heat sink (500) is placed on the lower surface of the housing (100), a lower ceramic substrate (200) is attached to the upper surface of the heat sink (500), an upper ceramic substrate (300) is placed at a certain interval on top of the lower ceramic substrate (200), and a PCB substrate (400) is placed at a certain interval on top of the upper ceramic substrate (300).

The PCB substrate (400) placed on the housing (100) can be fixed by guide grooves (401, 402) formed to be recessed into the edge of the PCB substrate (400) and guide ribs (101) and catches (102) formed on the housing (100) corresponding to the guide grooves (401, 402). The PCB substrate (400) according to the embodiment has a plurality of guide grooves (401, 402) formed around the edge, and some of the guide grooves (401) are guided by guide ribs (101) formed on the inner surface of the housing (100), and the remaining some of the guide grooves (402) are caught by passing through catches (102) formed on the inner surface of the housing (100).

Alternatively, the heat sink (500), lower ceramic substrate (200), and upper ceramic substrate (300) are accommodated in the central empty space of the housing (100), and the PCB substrate (400) is placed on the upper surface thereof and may be fixed with a fastening bolt (not shown). However, fixing the PCB substrate (400) to the housing (100) with a catch structure reduces the assembly time and simplifies the assembly process compared to fixing it with a fastening bolt.

The housing (100) has fastening holes (103) formed at four corners. The fastening holes (103) are connected to the communication holes (501) formed in the heat sink (500). A fixing bolt (150) is fastened by penetrating the fastening holes (103) and the communication holes (501), and an end of the fixing bolt (150) penetrating the fastening holes (103) and the communication holes (501) can be fastened to a fixing hole of a fixing jig to be placed on the lower surface of the heat sink (500).

A bus bar (700) is connected to the first terminal (610) and the second terminal (620). The bus bar (700) connects the first terminal (610) and the second terminal (620) to the upper ceramic substrate (300). Three bus bars (700) are provided, one of which connects the + terminal of the first terminal (610) to the first electrode pattern (a) of the upper ceramic substrate (300), another of which connects the - terminal of the first terminal (610) to the third electrode pattern (c), and the remaining one of which connects the second terminal (620) to the second electrode pattern (b). The first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) refer to FIG. 7, which will be described later.

Figure 3 is a cross-sectional side view of a power module according to an embodiment of the present invention.

As illustrated in FIG. 3, the power module (10) has a multi-layer structure of a lower ceramic substrate (200) and an upper ceramic substrate (300), and a semiconductor chip (G) is positioned between the lower ceramic substrate (200) and the upper ceramic substrate (300). The semiconductor chip (G) may be any one of a GaN (Gallium Nitride) chip, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), a JFET (Junction Field Effect Transistor), and a HEMT (High Electric Mobility Transistor), but preferably, the semiconductor chip (G) uses a GaN chip. The GaN (Gallium Nitride) chip (G) is a semiconductor chip that functions as a high-power (300 A) switch and a high-speed (~1 MHz) switch. The GaN chip (G) has the advantage of being more heat-resistant than a conventional silicon-based semiconductor chip and of being able to reduce the size of the chip.

Furthermore, GaN chips (G) are power semiconductor chips optimized for high performance and efficiency, as they feature high electron mobility and high electron density, enabling high-speed switching and miniaturization. Furthermore, GaN chips (G) operate stably even at high temperatures and possess high output characteristics, enabling high efficiency.

The lower ceramic substrate (200) and the upper ceramic substrate (300) are formed as ceramic substrates including a metal layer brazed to at least one surface of the ceramic substrate to increase the heat dissipation efficiency of heat generated from the semiconductor chip (G).

The ceramic substrate can be, for example, alumina (Al ₂ O ₃ ), AlN, SiN, or Si ₃ N ₄ . The metal layer is formed as an electrode pattern for mounting a semiconductor chip (G) and an electrode pattern for mounting a driving element, respectively, by a metal foil brazed on the ceramic substrate. For example, the metal layer is formed as an electrode pattern in an area where a semiconductor chip (G) or peripheral components are to be mounted. The metal foil is, for example, an aluminum foil or a copper foil. The metal foil is, for example, sintered at 780°C to 1100°C on the ceramic substrate and brazed to the ceramic substrate. Such a ceramic substrate is called an AMB (Active Metal Brazing) substrate. The embodiment describes an AMB substrate as an example, but a DBC (Direct Bonding Copper) substrate, a TPC (Thick Printing Copper) substrate, and a DBA (Direct Brazed Aluminum) substrate can also be applied. However, an AMB substrate is most suitable in terms of durability and heat dissipation efficiency. For the above reasons, the lower ceramic substrate (200) and the upper ceramic substrate (300) are, as an example, AMB substrates.

The PCB substrate (400) is placed on top of the upper ceramic substrate (300). That is, the power module (10) is composed of a three-layer structure of a lower ceramic substrate (200), an upper ceramic substrate (300), and a PCB substrate (400). A semiconductor chip (G) for high-power control is placed between the upper ceramic substrate (200) and the lower ceramic substrate (300) to increase heat dissipation efficiency, and a PCB substrate (400) for low-power control is placed at the top to prevent damage to the PCB substrate (400) due to heat generated from the semiconductor chip (G). The lower ceramic substrate (200), the upper ceramic substrate (300), and the PCB substrate (400) can be connected or fixed with pins.

A heat sink (500) is placed on the lower portion of the lower ceramic substrate (200). The heat sink (500) is for dissipating heat generated from the semiconductor chip (G). The heat sink (500) is formed in the shape of a square plate having a predetermined thickness. The heat sink (500) is formed with an area corresponding to the housing (100) and may be formed of copper or aluminum to increase heat dissipation efficiency.

Hereinafter, the features of each component of the power module of the present invention will be described in more detail. In the drawings explaining the features of each component of the power module, some parts of the drawings are enlarged or exaggerated to emphasize the features of each component, and therefore, there may be some parts that do not match the basic drawing illustrated in Fig. 1.

Figure 4 is a perspective view showing a housing according to an embodiment of the present invention.

As illustrated in Fig. 4, the housing (100) has a hollow space formed in the center, and a first terminal (610) and a second terminal (620) are positioned at both ends. The housing (100) can be formed by insert injection molding so that the first terminal (610) and the second terminal (620) are integrally fixed at both ends.

Conventional power modules use insert injection molding to insert connecting pins into the housing to connect separate circuits. However, the present embodiment has a shape manufactured by excluding the connecting pins during the manufacturing of the housing (100). This simplifies the shape by not positioning the connecting pins inside the housing (100), thereby improving the flexibility of the power module in terms of torsional moment.

The housing (100) has fastening holes (103) formed at four corners. The fastening holes (103) are connected to the communication holes (501) formed in the heat sink (500). Support holes (104) are formed in the first terminal (610) and the second terminal (620). Support bolts (630) are fastened to the support holes (104) to connect the first terminal (610) and the second terminal (620) to external terminals such as a motor.

The housing (100) is formed of an insulating material. The housing (100) may be formed of an insulating material so that heat generated from the semiconductor chip (G) is not transmitted to the upper PCB substrate (400) through the housing (100).

Alternatively, the housing (100) may be formed of a heat-dissipating plastic material. The housing (100) may be formed of a heat-dissipating plastic material so that heat generated from the semiconductor chip (G) can be dissipated to the outside through the housing (100). For example, the housing (100) may be formed of an engineering plastic material. Engineering plastic has high heat resistance, excellent strength, chemical resistance, and wear resistance, and can be used for a long time at temperatures above 150°C. The engineering plastic may be made of one of polyamide, polycarbonate, polyester, and modified polyphenylene oxide.

The semiconductor chip (G) performs repeated operations as a switch, and as a result, the housing (100) is subjected to stress due to high temperature and temperature changes. However, since engineering plastic has excellent high temperature stability, it is relatively stable to high temperature and temperature changes compared to general plastic, and has excellent heat dissipation properties.

An example embodiment may be a housing (100) manufactured by insert-injecting an aluminum or copper terminal into an engineering plastic material. The housing (100) made of an engineering plastic material dissipates heat by transmitting it to the outside. The housing (100) can be made of a high-heat-conductivity engineering plastic that has higher thermal conductivity than general engineering plastic materials by filling a high-heat-conductivity filler into the resin and is lighter than aluminum.

Alternatively, the housing (100) may be made of an engineering plastic or high-strength plastic material with a graphene heat-dissipating coating applied to the inside and outside to provide heat-dissipating properties.

Fig. 5 is a perspective view for explaining a lower ceramic substrate according to an embodiment of the present invention.

As illustrated in FIGS. 3 and 5, the lower ceramic substrate (200) is attached to the upper surface of the heat sink (500). Specifically, the lower ceramic substrate (200) is placed between the semiconductor chip (G) and the heat sink (500). The lower ceramic substrate (200) transfers heat generated from the semiconductor chip (G) to the heat sink (500) and serves to insulate between the semiconductor chip (G) and the heat sink (500) to prevent short circuits.

The lower ceramic substrate (200) can be soldered to the upper surface of the heat sink (500). The heat sink (500) is formed with an area corresponding to the housing (100) and can be formed of a copper material to increase heat dissipation efficiency. The solder may be SnAg, SnAgCu, etc.

Fig. 6 is a drawing showing the upper and lower surfaces of a lower ceramic substrate according to an embodiment of the present invention.

As illustrated in FIGS. 5 and 6, the lower ceramic substrate (200) includes a ceramic substrate (201) and metal layers (202, 203) brazed to the upper and lower surfaces of the ceramic substrate (201). For example, the lower ceramic substrate (200) may have a thickness of 0.68t for the ceramic substrate (201) and a thickness of 0.8t for the metal layers (202, 203) formed on the upper and lower surfaces of the ceramic substrate (201).

The metal layer (202) of the upper surface (200a) of the lower ceramic substrate (200) may be an electrode pattern for mounting a driving element. The driving element mounted on the lower ceramic substrate (200) may be an NTC temperature sensor (210). The NTC temperature sensor (210) is mounted on the upper surface of the lower ceramic substrate (200). The NTC temperature sensor (210) is for providing temperature information within the power module due to heat generation of the semiconductor chip (G). The metal layer (203) of the lower surface (200b) of the lower ceramic substrate (200) may be formed on the entire lower surface of the lower ceramic substrate (200) to facilitate heat transfer to the heat sink (500).

An insulating spacer (220) is bonded to the lower ceramic substrate (200). The insulating spacer (220) is bonded to the upper surface of the lower ceramic substrate (200) and defines a distance between the lower ceramic substrate (200) and the upper ceramic substrate (300).

The insulating spacer (220) regulates the distance between the lower ceramic substrate (200) and the upper ceramic substrate (300), thereby increasing the heat dissipation efficiency of the heat generated from the semiconductor chip (G) mounted on the lower surface of the upper ceramic substrate (300), and prevents interference between the semiconductor chips (G), thereby preventing electrical shocks such as short circuits.

A plurality of insulating spacers (220) are bonded at a predetermined interval around the upper edge of the lower ceramic substrate (200). The interval between the insulating spacers (220) is utilized as a space to increase heat dissipation efficiency. In the drawing, the insulating spacers (220) are arranged around the edge based on the lower ceramic substrate (200), and for example, eight are arranged at a predetermined interval.

The insulating spacer (220) can be applied to check the alignment when the upper ceramic substrate (300) is placed on the lower ceramic substrate (200) by being integrally bonded to the lower ceramic substrate (200). When the upper ceramic substrate (300) with the semiconductor chip (G) mounted thereon is placed in a state where the insulating spacer (220) is bonded to the lower ceramic substrate (200), the insulating spacer (220) can be applied to check the alignment of the upper ceramic substrate (300). In addition, the insulating spacer (220) supports the lower ceramic substrate (200) and the upper ceramic substrate (300), thereby contributing to preventing warping of the lower ceramic substrate (200) and the upper ceramic substrate (300).

The insulating spacer (220) may be formed of a ceramic material for insulation between the chip mounted on the lower ceramic substrate (200) and the chip and components mounted on the upper ceramic substrate (300). For example, the insulating spacer may be formed of one selected from among Al ₂ O ₃ , ZTA, Si ₃ N ₄ , and AlN, or an alloy in which two or more of these are mixed. Al ₂ O ₃ , ZTA, Si ₃ N ₄ , and AlN are insulating materials with excellent mechanical strength and heat resistance.

The insulating spacer (220) is brazed to the lower ceramic substrate (200). If the insulating spacer (220) is soldered to the lower ceramic substrate (200), the substrate may be damaged by thermal and mechanical shock during soldering or pressurized firing, so brazing is used. The brazing bonding can utilize a brazing bonding layer including an AgCu layer and a Ti layer. The heat treatment for brazing can be performed at 780°C to 900°C. After brazing, the insulating spacer (220) is formed integrally with the metal layer (202) of the lower ceramic substrate (200). The thickness of the brazing bonding layer is 0.005 mm to 0.08 mm, which is thin enough not to affect the height of the insulating spacer, and the bonding strength is high.

A conductive spacer (230) is installed between the lower ceramic substrate (200) and the upper ceramic substrate (300). The conductive spacer (230) can perform electrical connection between electrode patterns in place of a connecting pin in a substrate having an upper and lower multi-layer structure. By directly connecting the substrates while preventing electrical loss and short-circuiting, the bonding strength can be increased and the electrical characteristics can also be improved. One end of the conductive spacer (230) can be bonded to the electrode pattern of the lower ceramic substrate (200) by a brazing bonding method. In addition, the other end of the conductive spacer (230) can be bonded to the electrode pattern of the upper ceramic substrate (300) by a brazing bonding method or a soldering bonding method. The conductive spacer (230) can be made of Cu or a Cu+CuMo alloy.

Fig. 7 is a perspective view for explaining an upper ceramic substrate according to an embodiment of the present invention, and Fig. 8 is a drawing showing the upper and lower surfaces of the upper ceramic substrate according to an embodiment of the present invention.

As shown in FIGS. 7 and 8, the upper ceramic substrate (300) is placed on top of the lower ceramic substrate (200).

The upper ceramic substrate (300) is an intermediate substrate of a laminated structure. The upper ceramic substrate (300) has a semiconductor chip (G) mounted on its lower surface and configures a high-side circuit and a low-side circuit for high-speed switching.

The upper ceramic substrate (300) includes a ceramic substrate (301) and metal layers (302, 303) brazed to the upper and lower surfaces of the ceramic substrate (301). As an example, the upper ceramic substrate (300) has a ceramic substrate thickness of 0.38t and an electrode pattern formed on the upper surface (300a) and lower surface (300b) of the ceramic substrate thickness of 0.3t. The pattern thicknesses of the upper and lower surfaces of the ceramic substrate must be the same to prevent warping during brazing.

The electrode pattern formed by the metal layer (302) on the upper surface of the upper ceramic substrate (300) is divided into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c). The electrode pattern formed by the metal layer (303) on the lower surface of the upper ceramic substrate (300) corresponds to the electrode pattern on the upper surface of the upper ceramic substrate (300). The reason the electrode patterns on the upper surface of the upper ceramic substrate (300) are divided into the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) is to separate the high side circuit and the low side circuit for high-speed switching.

The semiconductor chip (G) is provided in a flip chip form on the lower surface (300b) of the upper ceramic substrate (300) by a bonding layer such as solder or silver paste. Since the semiconductor chip (G) is provided in a flip chip form on the lower surface of the upper ceramic substrate (300), wire bonding is omitted, so that the inductance value can be reduced as much as possible, thereby improving heat dissipation performance.

As illustrated in Fig. 8, semiconductor chips (G) can be connected in parallel in pairs for high-speed switching. Two semiconductor chips (G) are arranged at positions connecting the first electrode pattern (a) and the second electrode pattern (b) among the electrode patterns of the upper ceramic substrate (300), and the remaining two are arranged in parallel at positions connecting the second electrode pattern (b) and the third electrode pattern (c). For example, the capacity of one semiconductor chip (G) is 150 A. Therefore, two semiconductor chips (G) are connected in parallel so that the capacity becomes 300 A.

The purpose of a power module using GaN chips as semiconductor chips (G) is high-speed switching. To achieve high-speed switching, it is important to have a very short connection between the Gate driver IC terminal and the Gate terminal of the semiconductor chip (G). Therefore, the connection distance between the Gate driver IC and the Gate terminal is minimized by connecting the semiconductor chips (G) in parallel. In addition, for the semiconductor chips (G) to switch at high speed, it is important to maintain the same distance between the Gate terminal and the Source terminal of the semiconductor chip (G). To achieve this, the Gate terminal and the Source terminal can be arranged so that the connection pin is connected to the center between the semiconductor chips (G). Problems may occur if the Gate terminal and the Source terminal do not maintain the same distance or if the pattern lengths are different.

The Gate terminal is a terminal that turns the semiconductor chip (G) on/off using a low voltage. The Gate terminal can be connected to the PCB substrate (400) through a connection pin. The Source terminal is a terminal through which a high current flows in and out. The semiconductor chip (G) includes a Drain terminal, and the Source terminal and the Drain terminal are divided into N type and P type to change the direction of the current. The Source terminal and the Drain terminal are responsible for inputting and outputting the current through the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c), which are electrode patterns for mounting the semiconductor chip (G). The Source terminal and the Drain terminal are connected to the first terminal (610) and the second terminal (620) of FIG. 1, which are responsible for inputting and outputting power.

The first terminal (610) illustrated in FIG. 1 includes a + terminal and a - terminal, and the power supplied from the first terminal (610) to the + terminal is output to the second terminal (620) through the first electrode pattern (a) of the upper ceramic substrate (300) illustrated in FIG. 8, the semiconductor chip (G) disposed between the first electrode pattern (a) and the second electrode pattern (b), and the second electrode pattern (b). In addition, the power supplied to the second terminal (620) illustrated in FIG. 1 is output to the - terminal of the first terminal (610) through the second electrode pattern (b), the semiconductor chip (G) disposed between the second electrode pattern (b) and the third electrode pattern (c) illustrated in FIG. 8. For example, power supplied from the first terminal (610), passed through the semiconductor chip (G), and outputted to the second terminal (620) is referred to as the high side, and power supplied from the second terminal (620), passed through the semiconductor chip (G), and outputted to the first terminal (610) is referred to as the low side.

As illustrated in FIG. 7, a cutting portion (310) may be formed in a portion of the upper ceramic substrate (300) corresponding to the NTC temperature sensor (210). The NTC temperature sensor (210) is mounted on the upper surface of the lower ceramic substrate (200). The NTC temperature sensor (210) is intended to provide temperature information within the power module due to heat generation of the semiconductor chip (G). However, since the thickness of the NTC temperature sensor (210) is thicker than the gap between the lower ceramic substrate (200) and the upper ceramic substrate (300), interference occurs between the NTC temperature sensor (210) and the upper ceramic substrate (300). To resolve this, the upper ceramic substrate (300) in the portion interfering with the NTC temperature sensor (210) is cut to form the cutting portion (310).

Silicone liquid or epoxy for molding can be injected into the space between the upper ceramic substrate (300) and the lower ceramic substrate (200) through the cutting portion (310). The silicone liquid or epoxy must be injected to insulate the space between the upper ceramic substrate (300) and the lower ceramic substrate (200). In order to inject the silicone liquid or epoxy into the upper ceramic substrate (300) and the lower ceramic substrate (200), one side of the upper ceramic substrate (300) can be cut to form the cutting portion (310), and the cutting portion (310) can be formed at a position corresponding to the NTC temperature sensor (210) to prevent interference between the upper ceramic substrate (300) and the NTC temperature sensor (210). Silicone fluid or epoxy can be filled in the space between the lower ceramic substrate (200) and the upper ceramic substrate (300) and the space between the upper ceramic substrate (300) and the PCB substrate (400) for the purpose of protecting the semiconductor chip (G), mitigating vibration, and insulating it.

A through hole (320) is formed in the upper ceramic substrate (300). The through hole (320) is for connecting the semiconductor chip (G) mounted on the upper ceramic substrate (300) with the driving element mounted on the PCB substrate (400) at the shortest distance in the upper and lower multi-layer substrate structure, and for connecting the NTC temperature sensor (210) mounted on the lower ceramic substrate (200) with the driving element mounted on the PCB substrate (400) at the shortest distance.

Through holes (320) can be formed in a total of 10, with 2 holes each formed at locations where semiconductor chips (G) are installed, and 2 holes each formed at locations where NTC temperature sensors are installed. In addition, multiple through holes (320) can be formed in the upper ceramic substrate (300) at the portion where the first electrode pattern (a) and the third electrode pattern (c) are formed.

A plurality of through holes (320) formed in the first electrode pattern (a) allows the current flowing into the first electrode pattern (a) on the upper surface of the upper ceramic substrate (300) to move to the first electrode pattern (a) formed on the lower surface of the upper ceramic substrate (300) and to flow into the semiconductor chip (G). A plurality of through holes (320) formed in the third electrode pattern (c) allows the current flowing into the semiconductor chip (G) to move to the third electrode pattern (c) on the upper surface of the upper ceramic substrate (300) through the third electrode pattern (c) on the lower surface of the upper ceramic substrate (300).

The diameter of the through hole (320) may be 0.5 mm to 5.0 mm. A connecting pin is installed in the through hole (320) to be connected to the electrode pattern of the PCB substrate, and through this, the driving element mounted on the PCB substrate (400) can be connected. In the upper and lower multi-layer substrate structure, the connection between the electrode patterns through the through hole (320) and the connecting pin installed in the through hole (320) can contribute to improving the constraints according to the size of the power module by eliminating various output losses through the shortest distance connection.

A plurality of via holes (330) may be formed in the electrode pattern of the upper ceramic substrate (300). The via holes (330) may be processed to at least 50% of the substrate area. The area of the via holes (330) described above has been described as being applied to at least 50% of the substrate area, but is not limited thereto and may be processed to less than 50%.

For example, 152 via holes may be formed in the first electrode pattern (a), 207 via holes may be formed in the second electrode pattern (b), and 154 via holes may be formed in the third electrode pattern (c). The multiple via holes formed in each electrode pattern are for conducting and distributing large currents. If the electrode patterns on the upper surface and the lower surface of the upper ceramic substrate (300) are connected in the form of a single slot, high current may flow only in one direction, which may cause problems such as short circuits and overheating.

A conductive material is filled into the via hole (330). The conductive material may be Ag or an Ag alloy. The Ag alloy may be an Ag-Pd paste. The conductive material filled into the via hole (330) electrically connects the electrode pattern on the upper surface of the upper ceramic substrate (300) to the electrode pattern on the lower surface. The via hole (330) may be formed by processing the PCB substrate (400).

Fig. 9 is a perspective view showing a state in which a connecting pin is coupled to an upper ceramic substrate according to an embodiment of the present invention.

As illustrated in Fig. 9, the connecting pin (800) is fitted into a through hole (320) formed at a position adjacent to the semiconductor chip (G) in the upper ceramic substrate (300). The connecting pin (800) fitted into the through hole (320) formed at a position adjacent to the semiconductor chip (G) is fitted into a through hole formed at a corresponding position on the PCB substrate (400) to connect the gate terminal on which the semiconductor chip (G) is mounted and the electrode pattern of the PCB substrate (400).

In addition, the connecting pin (800) is fitted into a through hole (320) formed at a position adjacent to the NTC temperature sensor (210) in the upper ceramic substrate (300). The connecting pin (800) fitted into the through hole (320) formed at a position adjacent to the NTC temperature sensor (210) can be fitted into a through hole formed at a position corresponding to the PCB substrate (400) to connect the terminal of the NTC temperature sensor (210) and the electrode pattern of the PCB substrate (400).

In addition, the connecting pin (800) is fitted into a plurality of through holes (320) formed in a row in the first electrode pattern (a) and the third electrode pattern (c) in the upper ceramic substrate (300). The connecting pin (800) fitted into a plurality of through holes (320) formed in the first electrode pattern (a) and the third electrode pattern (c) can be fitted into a through hole formed at a corresponding position in the PCB substrate (400) to connect the semiconductor chip (G) to the capacitor (410) of the PCB substrate (400).

The connecting pin (800) connects the semiconductor chip (G) mounted on the upper ceramic substrate (300) to the driving element mounted on the PCB substrate (400) at the shortest distance, thereby eliminating various output losses and enabling high-speed switching.

Fig. 10 is a plan view of a PCB substrate according to an embodiment of the present invention.

As illustrated in Fig. 10, a PCB substrate (400) is mounted with a driving element for switching a semiconductor chip (G) or switching the semiconductor chip using information detected by an NTC temperature sensor (210). The driving element includes a Gate Drive IC.

A capacitor (410) is mounted on the upper surface of the PCB substrate (400). The capacitor (410) is mounted on the upper surface of the PCB substrate (400) at a position corresponding to between a semiconductor chip (G) positioned to connect the first electrode pattern (a) and the second electrode pattern (b) of the upper ceramic substrate (300) and a semiconductor chip (G) positioned to connect the second electrode pattern (b) and the third electrode pattern (c) of the upper ceramic substrate (300).

When a capacitor (410) is mounted on the upper surface of the PCB substrate (400) at a position corresponding to the between the semiconductor chips (G), the semiconductor chips (G) and the Gate Drive IC circuit can be connected at the shortest distance using the connection pin (reference numeral 800 of FIG. 9), which is more advantageous for high-speed switching. For example, 10 capacitors (410) can be connected in parallel to match the capacity. In order to secure 2.5㎌ or more for decoupling purposes at the input terminal, 10 high-voltage capacitors must be connected to secure the capacity. The related formula is 56㎌/630V×5ea=2.8㎌. The Gate Drive IC circuit includes a High-side gate drive IC and a Low-side gate drive IC.

Figure 11 is an internal configuration diagram for explaining the power module structure according to an embodiment of the present invention.

As shown in Fig. 11, the power module (10) has a multi-layer structure of a lower ceramic substrate (200) and an upper ceramic substrate (300).

The upper ceramic substrate (300) is spaced apart from the upper portion of the lower ceramic substrate (200). The semiconductor chip (G) is mounted on the lower surface of the upper ceramic substrate (300) and is placed between the lower ceramic substrate (200) and the upper ceramic substrate (300). The semiconductor chip (G) for high-power control is placed between the lower ceramic substrate (200) and the upper ceramic substrate (300) to increase heat dissipation efficiency. In addition, when the lower ceramic substrate (200) and the upper ceramic substrate (300) are formed in a top-bottom multi-layer structure and the high-power semiconductor chip (G) is placed therebetween, the semiconductor chip (G) is protected from the external environment, so that performance can be implemented without being restricted by the area and volume of the power module (10).

A PCB substrate (400) is spaced apart from the upper ceramic substrate (300). The PCB substrate (400) for low-power control is spaced apart from the upper ceramic substrate (300) to prevent damage to the PCB substrate (400) due to heat generated from the semiconductor chip (G).

On the upper surface of the PCB substrate (400), a driving element for switching the semiconductor chip (G), a capacitor for making the voltage continuous, a connector, etc. are mounted. The driving element includes a Gate Drive IC circuit. The Gate Drive IC circuit includes a High side gate drive IC and a Low side gate drive IC. The PCB substrate (400) may have a multilayer structure in which an internal electrode pattern is formed between a plurality of insulating layers and an upper electrode pattern is formed on the top layer.

Through holes (320, 420) are formed in the upper ceramic substrate (300) and the PCB substrate (400). A connecting pin (800) is installed through the through holes (320, 420) formed in the upper ceramic substrate (300) and the PCB substrate (400). The connecting pin (800) vertically connects the electrode patterns (a, b, c, d) formed in the upper ceramic substrate (300) and the PCB substrate (400).

The connecting pin (800) installed through the through hole (320) of the upper ceramic substrate (300) and the through hole (420) of the PCB substrate (400) connects the electrode patterns (a, b, c) of the upper ceramic substrate (300) and the electrode pattern (d) of the PCB substrate (400) at the shortest distance, thereby eliminating various output losses and lowering impedance and inductance, thereby facilitating high-speed control of high power.

Assuming a constant voltage, low impedance facilitates current flow, facilitating high-speed current control. High inductance increases resistance and heat generation, making low inductance crucial for high-speed switching and heat dissipation. Impedance and inductance both increase with increasing electrode pattern connection distance.

If the lower ceramic substrate (200), upper ceramic substrate (300), and PCB substrate (400) are manufactured separately and assembled and used as needed, it is difficult to connect the electrode patterns with the shortest distance and they must be connected using wires, etc., which causes various output losses, and there is a limitation in that it is difficult to control the current at high speed due to high impedance and inductance.

Accordingly, the power module of the embodiment is configured as an integrated high-power power semiconductor chip module and a Drive PCBA (Print Circuit Board Assembly) to minimize the current path and lower impedance and inductance. The high-power power semiconductor chip module is a module having a structure in which a high-power semiconductor chip is placed between a lower ceramic substrate (200) and an upper ceramic substrate (300), and the Drive PCBA refers to a PCB assembly including a driving element and an electrode pattern on a PCB substrate (400).

The semiconductor chip (G) may be any one of a SiC chip, a GaN chip, a MOSFET, an IGBT, a JFET, and a HEMT. Preferably, the semiconductor chip (G) is a GaN chip and is fixed to the lower surface of the upper ceramic substrate (300) in a flip-chip form. In an embodiment, the semiconductor chip (G) has a surface electrode on the upper surface bonded to the metal layer (303) on the lower surface of the upper ceramic substrate (300) and a lower surface bonded to the metal layer (202) on the upper surface of the lower ceramic substrate (200). When the semiconductor chip (G) is fixed to the upper ceramic substrate (300) in a flip-chip form as described above, the distance between the semiconductor chip (G) and the gate drive IC terminal can be designed to be as short as possible, thereby maximizing the performance of the semiconductor chip (G).

The connecting pin (800) can connect the gate terminal of the semiconductor chip (G) mounted on the upper ceramic substrate (300) and the drive IC mounted on the PCB substrate (400). The drive IC includes a high gate drive IC (HS gate drive IC) and a low gate drive IC (LS gate drive IC). In addition, the connecting pin (800) can connect the electrode pattern of the upper ceramic substrate (300) to the capacitor mounted on the PCB substrate (400).

The connecting pin (800) vertically connects the upper ceramic substrate (300) and the PCB substrate (400), but does not come into contact with the lower ceramic substrate (200) placed below the upper ceramic substrate (300) to prevent short circuit.

The connecting pin (800) installed through the through-hole (320, 420) can be joined to the electrode patterns (a, b, c) on the edge of the through-hole (320) of the upper ceramic substrate (300) by laser welding. When the connecting pin (800) is inserted into the through-hole (320) and joined by laser welding, it is easy to fix the connecting pin (800) to the upper ceramic substrate (300) and the precision of the position is improved. This is advantageous in ensuring the operational reliability of the power module because the connecting pin (800) is stably connected to the electrode patterns (a, b, c) of the upper ceramic substrate (300).

The connecting pin (800) may include a solder layer (850) that joins the connecting pin (800) to the electrode patterns (a, b, c) of the upper ceramic substrate (300) during laser welding. The solder layer (850) may be applied to the edge of the through-hole (320) of the upper ceramic substrate (300) and may be melted during laser welding to join the connecting pin (800) to the electrode patterns (a, b, c). The connecting pin (800) may be formed of conductive copper or a copper alloy. The connecting pin (800) may be formed in a cylindrical shape corresponding to the inner diameter of the through-hole (320, 420) or may be formed in a square, cylindrical shape for ease of manufacturing. Alternatively, as illustrated in FIG. 9, the connecting pin (800) may be manufactured in a bundle shape and fitted into the through-hole (320) of the upper ceramic substrate (300).

It includes a heat sink (500) attached to the lower surface of the lower ceramic substrate (200). The heat sink (500) can be soldered to the lower surface of the lower ceramic substrate (200).

The lower ceramic substrate (200) and the upper ceramic substrate (300) include ceramic substrates (201, 301) and metal layers (202, 203, 302, 303) brazed to the upper and lower surfaces of the ceramic substrates (201, 301). The ceramic substrates (201, 301) are formed of one of alumina (Al ₂ O ₃ ), ZTA, AlN, SiN, and Si ₃ N ₄ , and the metal layers (202, 203, 302, 303) are formed of copper or a copper alloy material.

For example, the lower ceramic substrate (200) may be an AMB (Active Metal Brazing) substrate, and the thickness of the ceramic substrate (201) forming the AMB substrate may be 0.635 mm, and the thicknesses of the upper and lower metal layers (202, 203) of the ceramic substrate (201) may be 0.8 mm each. The upper ceramic substrate (300) may be an AMB (Active Metal Brazing) substrate, and the thickness of the ceramic substrate (301) forming the AMB substrate may be 0.38 mm, and the thicknesses of the upper and lower metal layers (302, 303) of the ceramic substrate (301) may be 0.3 mm each. In addition, the metal layers may be copper foil, as an example. The metal layers (302, 303) form electrode patterns (a, b, c).

The PCB substrate (400) is a multilayer FR4 substrate, for example, having a thickness of 0.9 mm. The heat sink (500) is formed of any one of copper material, copper alloy material, Cu-Mo-Cu three-layer structure, and Cu-CuMo-Cu three-layer structure, and can have a thickness of 4 mm, for example.

A via hole (330) can be formed in the upper ceramic substrate (300).

A via hole (330) is formed to vertically penetrate the ceramic substrate (301) of the upper ceramic substrate (300). A plurality of via holes (330) are formed, and a metal filler (P) is filled in the via hole (330). The metal filler (P) filled in the via hole (330) vertically connects the electrode patterns (a, b, c) on the upper and lower surfaces of the ceramic substrate (301). The metal filler (P) filled in the via hole (330) protrudes above and below the via hole (330) and can be joined to the electrode patterns (a, b, c) on the upper and lower surfaces of the ceramic substrate (301). Alternatively, a via hole (330) is formed to penetrate the upper ceramic substrate (300) upwardly and downwardly, and a metal filler (P) can be filled into the via hole (330) to connect the electrode patterns (a, b, c) on the upper and lower surfaces.

In the upper ceramic substrate (300), the ceramic material (301) is formed of one of alumina (Al ₂ O ₃ ), ZTA, AlN, SiN, and Si ₃ N ₄ . The metal layers (302, 303) are formed of copper or a copper alloy material. The metal layers (302, 303) of the upper ceramic substrate (300) form electrode patterns (a, b, c).

In this way, since the ceramic substrate (301) is formed of an insulating material, it is a structure in which electrical connection between the electrode patterns (a, b, c) on the upper and lower surfaces is impossible. In a power module, loop connection and electrical circuit connection through a semiconductor chip are required, but as the electrical loop length increases, the inductance value increases. An increase in the inductance value is disadvantageous for high-speed current movement.

Therefore, by lowering the inductance value and connecting the electrode patterns (a, b, c) on the upper and lower surfaces of the ceramic substrate (301) with a metal filler (P) filled in the via hole (330), the current movement efficiency can be increased and the power module can be made miniaturized.

The via hole (330) has an inner diameter of 0.1 mm to 0.3 mm to facilitate filling of the metal filler (P). The metal filler (P) is made of a conductive metal. For example, the metal filler (P) is made of one of Ag alloy, Ag-Pd, Ag-ceramic, and Cu alloy, or a mixed paste thereof. The metal filler (P) has low resistance and thus connects the electrode patterns (a, b, c) on the upper and lower surfaces of the ceramic substrate (301), thereby increasing the efficiency of current movement.

The area of the via hole (330) may be 10% or more of the area of the upper ceramic substrate (300).

The above-described embodiment can be easily controlled at high speed by minimizing the current path and lowering the impedance and inductance by manufacturing the lower ceramic substrate (200), the upper ceramic substrate (300), and the PCB substrate (400) as a three-layer integrated configuration.

In addition, by forming a plurality of via holes (330) in the upper ceramic substrate (300) to connect the electrode patterns (a, b, c) on the upper and lower surfaces, it is possible to facilitate the distribution and conduction of large currents, thereby preventing problems such as short circuits and overheating and increasing the efficiency of high-speed current movement.

The power module (10) described above is manufactured in the form of a module in which a lower ceramic substrate (200) is bonded to the upper surface of a heat sink (500), an upper ceramic substrate (300) is spaced apart from the upper surface of the lower ceramic substrate (200) via an insulating spacer (220), a PCB substrate (400) is spaced apart from the upper surface of the upper ceramic substrate (300) via a connecting pin (800), and the lower ceramic substrate (200), the upper ceramic substrate (300), and the PCB substrate (400) are packaged by a housing (100).

The housing (100) is formed with an empty space that is opened vertically in the center and is formed of an injection-molded material. A heat sink (500) is bonded to the lower surface of the housing (100), and a lower ceramic substrate (200) is bonded to the upper surface of the heat sink (500) exposed through the empty space of the housing (100), and an upper ceramic substrate (300) and a PCB substrate (400) are sequentially installed thereon. The distance between the upper ceramic substrate (300) and the PCB substrate (400) is maintained at a minimum of 0.5 mm to prevent damage to the components stored on the PCB substrate.

Additionally, a silicone liquid (S) or epoxy is filled between the lower ceramic substrate (200) and the upper ceramic substrate (300). The silicone liquid (S) or epoxy insulates the electrode patterns of the lower ceramic substrate (200) and the upper ceramic substrate (300).

The power module (10) described above is formed with a multi-layer structure of a lower ceramic substrate (200) and an upper ceramic substrate (300), a semiconductor chip (G) is mounted and protected between them, and a PCB substrate (400) is placed on top of the upper ceramic substrate (300). Since it is formed with a multi-layer structure and is in the form of a packing using silicone liquid (S) or epoxy, performance can be implemented without being restricted by the area and volume of the power module.

Fig. 12 is an internal configuration diagram for explaining a power module structure according to another embodiment of the present invention, and Fig. 13 is a cross-sectional view showing an upper ceramic substrate according to another embodiment of the present invention.

The power module (10') of another embodiment has a different shape of the upper ceramic substrate from that of the first embodiment.

As shown in FIGS. 12 and 13, a ceramic substrate (300') of another embodiment has a curvature slope (350, 350', 350") formed at the edge of a metal layer (302', 303') to alleviate stress concentration. The lifespan of the ceramic substrate is determined by the material of the ceramic substrate and the shape of the metal layer forming the electrode pattern.

The material of the ceramic substrate (301) is formed of one of high-strength alumina (Al ₂ O ₃ ), AlN, SiN, and Si ₃ N ₄ to ensure a long service life. As the thickness of the edge of the metal layer (302', 303') increases, the bonding stress with the ceramic substrate (301) increases due to stress concentration. If the bonding stress increases, the metal layer (302', 303') may separate from the ceramic substrate (301) under rapid temperature changes.

In order to prevent the metal layer (302', 303') from being separated from the ceramic substrate (301), the bonding stress must be minimized while maintaining the bonding strength. Therefore, the metal layer (302', 303') forms a rounded curvature slope (350, 350', 350") at the edge to gradually reduce the thickness, thereby alleviating stress concentration.

The curvature slope portion (350, 350', 350") has a shape that protrudes in the outer circumferential direction of the ceramic substrate (301). For example, the curvature slope portion (350, 350', 350") is formed in a concave shape in the direction of the ceramic substrate, and the protrusion length increases as it goes in the direction of the ceramic substrate. Alternatively, the curvature slope portion (350', 350") may have a multi-stage structure in which a plurality of concave portions (351, 352, 351', 352') are formed, and a protrusion portion (353, 353') is formed at a point where the concave portions (351, 352) and the concave portions (351', 352') meet. The protrusion portions (353, 353') have a sharp shape.

Alternatively, the curvature slope (350', 350") may be a two-stage structure in which two concave portions (351, 352, 351', 352') are formed and a protrusion (353, 353') is formed at the point where the concave portions (351, 352) and the concave portions (351', 352') meet.

The curvature slope (350, 350', 350") formed on the edge of the metal layer (302', 303') may have a single-stage structure and a multi-stage structure mixed together. For example, a single-stage curvature slope (350) may be formed on one edge of the edge of the metal layer (302', 303'), and a multi-stage curvature slope (350', 350") may be formed on the other edge. Alternatively, the entire edge of the metal layer (302', 303') may be formed as a multi-stage curvature slope (350', 350").

The length of the curved slope (350) of the single-stage structure is formed relatively small compared to the thickness of the metal layer (302', 303') so that the stress relief function can be performed while maintaining strong bonding strength.

Since the area bonded to the ceramic substrate (301) of the single-stage structured curvature slope (350) is relatively narrower than that of the multi-stage structured curvature slope (350', 350"), the bonding strength can be maintained even when the gap between the metal layers (302', 303') is narrow.

Since the area where the multi-stage structure's curvature slope (350', 350") is bonded to the ceramic substrate (301) is relatively larger than that of the single-stage structure's curvature slope (350), the bonding strength can be maintained strongly. However, since the area protruding in the outer circumferential direction is large, it may be difficult to apply when the gap between adjacent metal layers (302', 303') is narrow.

Depending on the distance between the metal layers (302', 303') and the adjacent metal layers (302', 303'), different shaped curvature slopes (350', 350") can be formed on the outer periphery adjacent to the other metal layers (302', 303').

The curvature slope (350, 350', 350") prevents stress concentration at the edge of the metal layer (302', 303') and alleviates thermal and electrical shocks, thereby securing a lifespan that is 2 to 3 times longer than that of the ceramic substrate (300') and ensuring reliability.

The ceramic substrate (300') illustrated in Fig. 13 is an upper ceramic substrate on which a semiconductor chip is mounted. In another embodiment, the above-described curvature slope portion (350, 350', 350") is applied to the edge of the upper ceramic substrate as an example, but the curvature slope portion (350, 350', 350") can also be applied to the lower ceramic substrate.

Ceramic substrate (300') is one of AMB (Active Metal Brazing) substrate, DBC (Direct Bonding Copper) substrate, DBA substrate (Direct Brazed Aluminum), and TPC (Thick Printing Copper) substrate. The ceramic substrate (300') is explained using the upper ceramic substrate on which the semiconductor chip is mounted as an example.

Figures 14 and 15 are process diagrams for explaining a method for manufacturing an upper ceramic substrate according to another embodiment of the present invention.

As illustrated in FIG. 14, the curvature slope (350, 350', 350") is formed by placing a photomask (m) on one surface of the metal layer (302, 303) and etching the metal layer (302, 303) exposed by the photomask (m).

In addition, the multi-stage structured curved slope (350', 350") is formed by arranging a photomask (m) in which two or more holes are continuously formed on one surface of a metal layer (302, 303) and etching the metal layer (302, 303) exposed by the photomask (m). If a photomask (m) in which two or more holes are continuously formed at a certain interval is used, the multi-stage structured curved slope (350', 350") can be formed with one etching.

The process includes a step of preparing a ceramic substrate (S10), a step of forming a photomask (S20), a step of forming a curvature slope (S30), and a step of removing the photomask (S40).

Step (S10) of preparing a ceramic substrate prepares a ceramic substrate (300) including a ceramic substrate (301) and a metal layer (302, 303) brazed to at least one surface of the ceramic substrate (301). The ceramic substrate (300) can be prepared in which the ceramic substrate (301) has a thickness of 0.3 mm to 0.4 mm and the metal layer (302', 303') has a thickness of 0.3 mm.

The step (S20) of forming a photomask can form a photomask (m) in which two or more holes (h) are continuously formed on one surface of a metal layer (302, 303). The two or more continuously formed holes (h) are for forming a multi-stage structure of a curvature slope (350', 350").

Additionally, the photomask (m) may form a plurality of photomasks (m) having an area narrower than the area of the metal layer (302', 303').

The step (S30) of forming a curvature slope portion is to etch the metal layer (302, 303) exposed by the photomask (m) with an etching solution to form a curvature slope portion (350') having a rounded slope toward the outer circumference of the ceramic substrate (301) toward the lower part of the metal layer (302', 303') or a multi-stage curvature slope portion (350', 350") having two or more rounded concave portions (351, 352, 351', 352'). Ferric chloride can be used as the etching solution.

When the etchant is introduced into two consecutive holes (h), etching is performed at about 80%, and a two-stage structure of curved slopes (350', 350") with different etching degrees can be formed with one etching. In the two-stage structure, the shape and length of the concave portion can be controlled by the size of the adjacent holes and the spacing between the holes.

Additionally, the shape and length of the concave portion can be controlled by adjusting the concentration of the etching solution and the etching time.

The step of removing the photomask (S40) forms a curvature slope (350, 350', 350") on the metal layer (302', 303') and then etches the photomask (m) formed on one surface of the metal layer (302', 303') using an etching solution. When the photomask (m) is removed by etching, a ceramic substrate (300') in the final state is manufactured. The ceramic substrate (300') can be used as an upper ceramic substrate to prevent stress concentration at the edge, thereby improving the lifespan of the substrate.

The ceramic substrate (300') illustrated in FIG. 14 shows a curvature slope (350, 350', 350") in which a single-stage structure and a multi-stage structure are mixed for convenience of explanation. However, only a single-stage curvature slope (350) or a two-stage curvature slope (350', 350") may be formed at the edge of the ceramic substrate (300').

For example, as illustrated in FIG. 15, a multi-stage structured curvature slope (35") can be formed at the edge of the metal layer (302').

The ceramic substrate (300') manufactured by the above-described method has a longer lifespan and contributes to improving the reliability of the power module by alleviating stress concentration due to heat and electrical shock at the edge compared to the upper ceramic substrate (300) of the embodiment.

The present invention has been disclosed in its optimal embodiments in the drawings and specifications. While specific terminology has been used herein, it is solely for the purpose of describing the invention and is not intended to limit the scope of the invention as defined in the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be defined by the technical spirit of the appended claims.

10: Power module 100: Housing
101: Guide rib 102: Hook
103: Fastener 104: Supporter
200: Lower ceramic substrate 201: Ceramic substrate
202,203: Metal layer 210: NTC temperature sensor
220: Insulating spacer 230: Conductive spacer
300,300': Upper ceramic substrate 301: Ceramic base material
302,303,302',303': Metal layer 310: Cutting part
320,420: Through-hole 330: Via-hole
350,350',350": Curvature slope m: Photomask
400: PCB board 401: Guide groove
410: Capacitor 420: Through-hole
430: Connector 500: Heatsink
501: flue hole 550: solder layer
610: Terminal 1 620: Terminal 2
630: Support bolt 700: Bus bar
G: Semiconductor chip (GaN chip) 800: Connection pin
S: silicone liquid h: hole

Claims (10)

Lower ceramic substrate;
An upper ceramic substrate spaced apart from the upper portion of the lower ceramic substrate and having a semiconductor chip mounted on the lower surface;
A PCB substrate placed on top of the upper ceramic substrate;
A plurality of through holes formed corresponding to the upper ceramic substrate and the PCB substrate; and
It includes a connecting pin that is installed through the through hole of the upper ceramic substrate and the through hole of the PCB substrate to vertically connect the metal layer of the upper ceramic substrate and the metal layer of the PCB substrate.
The above upper ceramic substrate
Comprising a ceramic substrate and a metal layer bonded to at least one surface of the ceramic substrate,
The above metal layer has a curved slope formed at the edge,
The above curvature slope protrudes in a direction from the edge of the metal layer toward the outer periphery of the ceramic substrate,
A power module in which the connecting pins installed through each of the above through-holes are joined to a metal layer at the edge of the through-hole of the upper ceramic substrate by laser welding, and further includes a solder layer that is applied to the edge of the through-hole of the upper ceramic substrate and melts during laser welding to join the connecting pins to the metal layer at the edge of the through-hole. In the first paragraph,
The above-mentioned curvature slope portion is formed in a concave shape in a cross-sectional shape viewed from the side of the upper ceramic substrate in a direction toward the ceramic substrate, and the power module in which the length protruding in the direction toward the outer periphery of the ceramic substrate increases as it goes toward the ceramic substrate. In the first paragraph,
The above curvature slope
A power module having a multi-stage structure in which a plurality of concave portions are formed and a protrusion is formed at a point where the concave portions meet. In the third paragraph,
The power module has a sharp protrusion. In the first paragraph,
The above curvature slope
A power module having a two-stage structure in which two concave portions are formed and a protrusion is formed at the point where the concave portions meet. In the first paragraph,
The curvature slope formed at the edge of the above metal layer
A power module in which a single-stage structure formed in a concave shape in the direction of the ceramic substrate and a multi-stage structure in which two or more concave portions are formed in the direction of the ceramic substrate are mixed. In paragraph 6,
The above curvature slope
A power module formed by placing a photomask on one surface of the above metal layer and etching the metal layer exposed by the photomask. In paragraph 6,
The above multi-stage structure's curvature slope
A power module formed by arranging a photomask having two or more holes formed continuously on one surface of the metal layer and etching the metal layer exposed by the photomask. In the first paragraph,
The above lower ceramic substrate
Comprising a ceramic substrate and a metal layer bonded to at least one surface of the ceramic substrate,
The above metal layer has a curved slope formed at the edge,
The above curvature slope is a power module that protrudes in a direction from the edge of the metal layer toward the outer periphery of the ceramic substrate. In the first paragraph,
The above ceramic substrate is a power module that is one of an AMB (Active Metal Brazing) substrate, a DBC (Direct Bonding Copper) substrate, a DBA substrate (Direct Brazed Aluminum), and a TPC (Thick Printing Copper) substrate.