KR102860219B1 - Performance diagnosis system using computer acceleration rate algorithm, and method thereof - Google Patents

Abstract

The present invention relates to a performance diagnosis system and method using a computer acceleration rate algorithm, and more specifically, to a performance diagnosis system and method using a computer acceleration rate algorithm for evaluating the performance of a computer by installing a performance diagnosis benchmark app program inside a computer, and at this time, increasing or decreasing the computer performance acceleration rate by adjusting the operating voltage, frequency, etc. including the timing of the computer semiconductor elements, analyzing the fluctuations in the computer performance, issuing a warning when the computer productivity falls below the average, and further reducing or adjusting the assigned tasks according to the decline in the computer productivity.

Description

Performance diagnosis system and method using computer acceleration rate algorithm {Performance diagnosis system using computer acceleration rate algorithm, and method thereof}

The present invention relates to a performance diagnosis system and method using a computer acceleration rate algorithm, and more particularly, to a performance diagnosis system and method using a computer acceleration rate algorithm for providing a performance diagnosis function to determine the basis for application of appropriate assignment of a personal computer to an appropriate task, such as game and graphic production or document work, based on the performance of the computer when utilizing the personal computer in the appropriate place.

The present invention relates to a system and method for efficiently using computer resources by measuring overload or heat generation phenomena affecting the performance and execution capability of device elements such as a central processing unit, memory, GPU, and SSD when a high-load app for big data processing is applied to a computer, and, if a performance degradation phenomenon exceeding a certain level occurs, excluding the computer task and further assigning it to a lower-level execution task that matches the task.

Computer performance means that all functional circuits inside the computer perform their functions to perform specific tasks, resulting in comprehensive computational processing performance.

The overall performance of a computer can be adjusted by adjusting the timing, clock frequency, and applied voltage values of the BIOS to the highest level, upper level, standard, lower, and lowest level settings according to the performance purpose, thereby demonstrating the performance at each level.

To improve computer performance or ensure availability, multiple computers can typically be run in parallel to provide high performance. In a single computer system, performance can be adjusted to either high or low levels by adjusting the computer's BIOS settings to increase or decrease the responsiveness of its components.

Diagnosing the state of computer performance means obtaining the computer's performance indicators from each setting value for the computer device components, for example, when running a benchmark application program that depicts graphic objects and pixels.

If performance indicators fall below average, this indicates a decline in computer performance and reduced responsiveness of computer components. To determine the cause, the load on the components and distracting effects such as heat generation are measured.

As a representative method for improving computer performance, Patent No. 10-2092091 (Prior Document 1) presents a method for providing high network reliability by managing all equipment systems of a computer network through an intelligent central management system.

This approach implemented a method to improve performance across multiple computers across a computer network. However, because it involved replacing the affected computer entirely with a standby system and a new path computer, it required additional computer resources. While this approach to ensuring performance through standby computers is suitable for large-scale network computing, it has limitations that make it inapplicable to small networks or computing environments operated by individual computers.

In addition, as a method to ensure the performance of functional circuits within a single computer system, the Scan DFT (Design For Testability) design method was proposed to continuously perform services by checking for failure and malfunction factors in real time while the computer system is in operation and replacing them with duplicated device components within the computer in case a problem occurs.

An example of a scan-type test is described in Patent No. 10-1629249 (Prior Document 2). As a scan test DFT method, a test pattern is input from outside the device to check the operation of the combinational circuit and sequential circuit inside the SoC device, etc., and the device can be replaced with a spare device if a problem occurs.

Figure 1 is a block diagram conceptually illustrating a conventional method for testing semiconductor devices during operation.

By using the test control and result generation unit (100) which is a test equipment, a test pattern is input into a semiconductor element (110), a test output signal on the semiconductor element (110) is checked to determine whether there is an abnormality in the semiconductor element (110), and a circuit and procedure are presented to perform a scan test for the presence or absence of an abnormality in the logic by separately adding a flip-flop scan circuit (111, 112) to the semiconductor function and test circuit (1, 2), which can be said to be a more advanced technology than having multiple computers in reserve to ensure performance.

However, this method more than doubles the cost of the device circuitry, requiring duplicate fabrication to ensure performance. Furthermore, because operation alternates between functional and test circuits, the operational overhead associated with switching between circuits increases. While this approach offers the advantage of being able to temporarily replace one circuit in the event of an error or failure, it also presents the disadvantage of not being able to maintain performance-guaranteed testing with a single functional circuit.

As another prior art, Patent Registration No. 10-0423192 (Prior Document 3) proposes a performance method that determines and displays the accumulated performance level of each application or all applications when running multiple applications in one server computer, thereby indicating the current allocation status of performance and the performance reserve that can be used in the future.

Application performance indicators are inserted into a performance database so that system administrators or automated service programs know how much application performance is available, and the signal records and corresponding time stamps can be used to plan performance utilization by time band.

Although this method has improved in showing the performance of an application server that accepts application service requests, it has limitations in that it cannot show how much computing performance and performance of the device components are provided in terms of the available capacity or maximum performance of the computer device components or semiconductor devices that make up the system.

The prior art discussed here has the advantage of being applicable to large-scale data centers, network systems, and large-scale production sites. However, it is difficult to apply it to small, single-computer computer labs or autonomous vehicles, where standalone computers are installed and operating in real time to inspect and diagnose computers and semiconductor devices. Even if applied, it faces significant challenges, such as high purchase and maintenance costs.

Therefore, in increasingly diverse computer environments such as autonomous vehicles and IoT, where single computers and embedded systems are applied, a real-time diagnostic system is needed in application sites where required services must be provided and the cause of problems must be investigated when they occur. In addition, an in-depth performance diagnostic system method that can self-diagnose through computer diagnostic software without separate additional equipment is urgently needed.

(Prior Document 1) Patent No. 10-2092091

(Prior Document 2) Patent No. 10-1629249

(Prior Document 3) Patent No. 10-0423192

The present invention is intended to solve such problems, and to provide a performance diagnosis system and method using a computer acceleration rate algorithm to provide a method for supplying performance within the functional circuit of the computer itself without separate additional resources by alleviating the burden of allocating spare resources on a software SDN network by designating adjacent switches and link redundancy groups in a conventional computer performance guarantee method.

In addition, it is to suggest a method to maintain computer performance with only given resources by self-diagnosing the cause of problems such as computer malfunctions and blocking the problem area internally to avoid it without the operational burden of maintaining performance in an emergency by operating the computer function circuit in duplicate, or by excluding it in the computer device manager and reconfiguring and operating the computer device with only non-problem resources.

Also, even if the BIOS does not have a separate diagnostic program and test data, the diagnostic program performs a diagnosis on the memory and device components after the OS starts, and instead of performing a diagnosis every time the computer starts, it performs a diagnosis only when the device components slow down or show abnormal signs, thereby identifying the type of problem and suggesting an immediate response method to take action.

The purposes of the present invention are not limited to the purposes mentioned above, and other purposes not mentioned can be clearly understood by those skilled in the art from the description below.

In order to achieve the above object, a performance diagnosis method using a computer acceleration rate algorithm according to an embodiment of the present invention tests whether device elements including a CPU, which is a typical central processing unit, a memory, an SSD, and a GPU, which are storage media, as information processing and data transmission elements of a computer, are operating normally, the performance diagnosis method using a computer acceleration rate algorithm comprising a first step of registering performance elements including at least the performance of a computer system and device element settings and displaying the values on a monitor, a second step of receiving setting value information including the clock frequency and information transmission timing and voltage of the CPU, memory, SSD, and GPU of the computer from a basic input/output program, BIOS, and displaying the operating level of the computer device elements, a third step of measuring a performance index value by executing a benchmark app program for measuring the computer operation and transmission performance at the current setting level of the device elements, and a fourth step of reducing and assigning a lower or next-lower task instead of the current task depending on the level of degradation when the performance index value differs from the average value.

At this time, the fourth step includes a step of obtaining a device timing setting value that produces a higher or lower performance in addition to the reference performance when upward or downward adjusting the clock frequency and device timing value of the device element in the BIOS, which is a basic input/output program, when evaluating the performance through at least one benchmark app program of the computer of the third step.

In addition, when evaluating at least one data operation and transmission performance of a computer, a step of obtaining a timing setting value of an element that produces the maximum amount of information transmission; a step of obtaining timing and clock frequency setting values that realize the maximum amount of information transmission by increasing the clock frequency of the element by a preset value in the timing setting step that produces the maximum amount of information transmission; a step of obtaining timing setting values and clock frequency setting values of an element that produces the minimum amount of information transmission when evaluating the data operation and transmission performance of a computer; a step of obtaining the highest and lowest performance of the computer and confirming the change trend in performance at each setting value, a step of securing and displaying a section in which the increase and decrease in performance shows a proportional characteristic with respect to the increase and decrease in the timing and clock frequency values; a step of adjusting the setting value of the maximum amount of information transmission, when the computer fails to start up and stops, determining that the cause is the element's inability to operate at the set value, and restoring the set value to the previous value to perform in the operating section; a step of adjusting the setting value to perform in the operating section by determining that the cause is an abnormal operation of the element, and excluding the set value in which the abnormal operation occurred and restoring the set value to the previous setting value that shows the proportional characteristic to perform the operation; A step of notifying that a range secured in an acceleration rate section having proportional characteristics is an available performance indicator of a test computer, and registering the acceleration section and the percentage of the highest performance compared to the lowest performance as an available performance section; and a step of registering the performance section as a computer acceleration quality section because the computer is operating normally in the available performance section.

In addition, the present invention includes a first step of increasing a benchmark production input value to increase a computer acceleration rate in order to increase productivity in a proportional acceleration rate section of a computer, a second step of determining that a performance index of a corresponding acceleration rate increase section is stable when the production amount in the acceleration rate increase section is a value proportional to the input value or a value within an error range, a third step of determining whether the cause is due to a distraction effect including a load processing speed decrease or a heat generation phenomenon by measuring a load value and temperature of a device element and comparing the measured load value and temperature with an average value in order to determine that an increase in the load value and temperature of the device element has eroded the performance index, and a fourth step of registering a performance erosion rate as a computer quality deterioration rate in order to determine that an increase in the load value and temperature of the device element has eroded the performance index.

In addition, when the performance index of the computer's benchmark performance deviates from the average, the step of determining whether the cause is a heat generation phenomenon of the device element when the temperature of the device element is measured and the value of the increase in the device element temperature of the computer does not correspond to the dangerous temperature of the Windows operating system, or when the rate of increase in the performance index is higher than the temperature increase value, determining that the increase in the temperature of the device element has not affected the performance degradation is further included.

In addition, the present invention is a performance diagnosis system using a computer acceleration rate algorithm that tests whether a device element including a CPU, a memory, an SSD, a GPU, which are storage media, and a performance diagnosis test unit, which are typical central processing units as information processing and data transmission elements of a computer, are operating normally, wherein the performance diagnosis test unit registers performance elements including at least the performance of a computer system and device element settings and displays the values on a monitor, and receives setting value information including the clock frequency, information transmission timing, and voltage of the CPU, memory, SSD, and GPU of the computer from the BIOS, which is a basic input/output program, and displays the operating level of the computer device element, and measures the performance index value by executing a benchmark app program for measuring the computer operation and transmission performance at the current setting level of the device element, and when the performance index value differs from the average value, the current task is reduced and assigned to a lower or next lower task depending on the level of deterioration.

The performance diagnosis system and method using a computer acceleration rate algorithm according to an embodiment of the present invention can examine the high-load response of a device element, and can simplify the test procedure and cost by mounting a semiconductor element on a computer to perform a diagnosis test without the help of an external test device.

In addition, the present invention provides an effect that can evaluate the response speed, performance degradation, and heat generation effects of a device in a maximum high load environment by testing by adjusting the minimum timing level of the highest frequency at the average operating level as a test condition.

In addition, it reduces the circuit size for testing through self-verification algorithms and reduces operational overhead. In addition, in case of a failure or malfunction, the corresponding circuit element is operated as a replacement circuit prepared in advance within the computer, providing the effect of allowing the system to continue to operate even in crisis situations such as computer system failure.

Figure 1 is a block diagram conceptually illustrating a conventional method for testing semiconductor devices during operation.
FIG. 2 is a block diagram showing the configuration of a performance diagnosis system and a performance diagnosis test unit using a computer acceleration rate algorithm according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a process of setting BIOS device timing upward to secure maximum performance and obtain the highest timing value, and conversely, setting it downward to obtain the lowest value and registering it in a performance register, in the computer performance conditions of a performance diagnosis system using a computer acceleration rate algorithm.
Figure 4 is a graph showing the results of compressing a test file by increasing the computer device component settings and obtaining the compression performance (MB/sec) for each accelerated setting value, and is a drawing for confirming whether the increase or decrease in compression performance shows a proportional characteristic according to the adjustment of the setting value.
FIG. 5 is a diagram showing an algorithm flow chart for determining the location and size of a bit cell malfunction, a decrease in response speed, etc. by performing a bit cell inspection on the corresponding device circuit when an unstable state or malfunction occurs beyond the proportional performance when the setting value for increasing or decreasing the performance of the device is set to an upward or downward step.
Figure 6 is a flowchart of an algorithm for determining a malfunction due to a slow failure or slow response of a semiconductor element when performing a bit cell inspection in inspection mode.

A detailed description of a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In describing the present invention, if a detailed description of a known function or configuration is determined to unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In this specification, when one component "transmits" data or a signal to another component, it means that the component can directly transmit the data or signal to the other component, and can transmit the data or signal to the other component through at least one other component.

The present invention is explained using FIGS. 2 to 4.

A computer can be said to perform optimally when all internal components perform their full potential in various tasks, including computation and transmission, and maintain comprehensive service performance. When the computer's device components are configured with the fastest operating clock frequency, the shortest signal processing intervals and timing, and high voltage, the computer achieves peak performance, or maximum performance indicators.

On the other hand, by lowering the operating conditions step by step instead of the best operating conditions, it is possible to secure performance at the highest level, then at the upper, standard, lower, and lowest levels.

Computer performance can be utilized to the best advantage by selecting and operating under appropriate operating conditions according to needs, even with limited resource capabilities. In this case, performance is achieved through the close interaction between the responsiveness of device components and computer software application programs.

Even if a computer was working well, if the device components become old or deteriorate due to excessive high load usage and the responsiveness decreases, the processing speed may decrease, and in severe cases, errors may occur during operation or the system may freeze.

When such a failure occurs, performance can be adjusted downward by lowering the settings of the device components to a lower level. Even if the computer performance is slow under the lower conditions, the device components can still operate normally at the slow level, so performance for low-level tasks can be maintained.

If your computer is slowing down or experiencing errors, identifying which device component and area is causing the issue can help you address the issue. To identify the component causing the issue, you can run a performance diagnostic app, or benchmark app, to measure performance indicators and component responsiveness, thereby identifying the location and cause of the issue.

A performance diagnostic system for identifying a fault must have the ability to identify the cause by encompassing all elements of the system, such as evaluating computer performance indicators and comparing and diagnosing the load and temperature response of components such as semiconductors, in order to properly perform the diagnostic function.

The first step in diagnosing a computer's performance is to evaluate its performance under its set operating conditions, the so-called baseline device component settings.

This evaluates the computer's performance by running a benchmark app program for performance testing, and the test results confirm whether the test computer reaches the average performance value derived for the set value.

If the average is not reached and a deteriorated result of reduced production is produced, it can be said that the performance of the CPU and memory related to the result is deteriorated, and the detailed cause can be identified by performing a CPU speed test and memory cell circuit test diagnosis.

In addition, the performance can be obtained by evaluating the performance not only for the current setting of the device elements, but also for the maximum or minimum setting allowed by the computer, and if the result is displayed at a high setting, the computer can be assigned to a high-level task.

FIG. 2 is a block diagram illustrating a performance diagnosis system (200) using a computer acceleration rate algorithm as a computer system according to a first embodiment of the present invention. The performance diagnosis system (200) using a computer acceleration rate algorithm is composed of a central processing unit (CPU) (210), a basic input/output system (BIOS) (220), a memory (230), an SSD (240) as a storage medium, and a performance diagnosis test unit (250).

When purchasing a computer, the manufacturer provides the CPU, BIOS, memory, SSD, GPU, etc. with settings suitable for average performance. The reason for this is to maintain the computer's optimal performance by setting it to achieve average performance across all tasks for which the computer is used.

Therefore, this is referred to as the standard performance as recommended by the manufacturer. In addition to the standard performance, other performance levels, such as maximum, upper, standard, lower, and minimum, can be defined. This will be explained through the setup value registration function of the present invention.

Below, we explain the preparations for the test in the performance diagnostic test section.

The performance diagnostic test unit (250) collects currently operating setting information from the CPU (210), BIOS (220), memory (230), and SSD (240) and stores and records the frequency, timing, and waiting time for each device element in the performance registration unit (251).

The performance diagnostic test unit (250) receives and displays the BIOS setting values such as the clock frequency, timing, and waiting time, including the operating frequency and memory frequency of the currently operating CPU (210), from the library of the BIOS (220), and a performance monitor (252) is provided for the purpose of showing how much performance the computer exhibits when operating at the setting values. In addition to the current setting values, the performance monitor (252) provides an upwardly adjustable value for the performance, a downwardly adjustable value for the performance, and an evaluation trend diagram showing the performance that appears when the performance is performed at the highest, upper, standard, lower, and lowest levels. An event log showing a record of such computer operation events can also be provided.

It can be said that the computer performance tested by the performance diagnostic test unit (250) is exerted within the operating limit of the device components allowed by the settings of the BIOS (220). Here, the test condition of the performance diagnostic test unit (250) is to assign the BIOS settings of the device components, so the process of setting the BIOS (220) is described in the procedure below.

When conducting a performance test, the current settings refer to the settings of the computer device on which the test is to be performed. This value may be a reference value received from the BIOS (220), or it may be a new BIOS setting that the user wishes to operate by changing the performance. The following explains in detail the principles by which this can be changed.

To check the settings in BIOS (220), enter the CMOS setup utility, and in the function menu of that screen, enter the Mainboard Intelligent Tweaker (M.I.T.) menu to check the settings of the CPU (210) and memory (230), and also change the values.

Among the device element settings provided by BIOS (220), the memory (230) element setting value is relatively simple in performance diagnosis, so the diagnostic test procedure is described for the memory (230) element.

The memory (230) element stores, retrieves, and stores data, and exhibits its own processing speed. The processing speed can be adjusted to be faster or slower by increasing or decreasing the setting value of the memory (230) element. In addition, the processing speed can also be adjusted to be higher or lower by increasing or decreasing the memory clock frequency.

The operating structure of a memory (230) systematized to adjust the setting value of a memory (230) element is described.

The memory (230) has a bit cell as the minimum memory element, and has a multi-layered fetch path structure to ensure the procedure for finding, writing, and reading the bit cell.

The memory data storage and retrieval procedure consists of several key timing values to perform procedures such as storing bit data in a bit cell, retrieving the stored data, and protecting data values.

The timing setting value refers to the time required to find the information of the cell by searching for the cell address located in the row and column constituting the bit cell of the memory (230) in the memory bank. By making the timing fast or slow based on the following four timing regulations including the CAS latency, the processing time can be adjusted to be fast or slow.

Let's look at the four timing rules, or settings.

First, tCL (cascading latency) is the waiting time required to find the column address of the row of the bitcell to be read from the memory. If CL17 is changed to CL16 for the purpose of narrowing the cascading latency, it means that it becomes about 1 nanosecond faster.

Second, tRCD (last to last delay) is the waiting time for the address sensor to charge between row and column addresses, the memory controller holds the address value during this time, which is the interval during which charging occurs before discharging.

Third, tRP (Laser Precharge Time) is the charge cycle time of the row address cell, which is the row charge time that allows the address information to be maintained before being discharged.

Fourth, tRAS (Row Address Strobe time) is the timing time of the signal that reads the cell value of the row address.

By quickly adjusting the four timing settings of the above-mentioned memory (230) elements, the data retrieval time is shortened, and the computer's performance is increased accordingly. In addition, the clock frequency of the memory (230) can be quickly adjusted, and the faster clock frequency, together with the narrowed timing values, increases the performance.

Meanwhile, increasing performance by accelerating the clock frequency and timing of device components such as memory (230) may overload the components and generate heat. If the heat generation temperature rises above a certain level, the gains from such rapid adjustments in performance are lost, and malfunctions may occur, resulting in failure.

Therefore, when heat is generated, a cooling means must be provided to dissipate the heat generated by the device components, or care must be taken to maintain performance only to a level where heat generation does not occur.

To determine the memory heat generation temperature, you can check the temperature value using a preset app, such as the CPU HW Monitor app, or you can write a library interface program to directly receive the temperature value through the device sensor data library.

The performance test and data section (253) of Fig. 2 is equipped with a test app and test data to examine performance, and can evaluate performance based on how much the computational and transmission capabilities of the computer increase or decrease when the setting values are changed, including performance for a given computer device element as a base.

In a typical computer, the test app, or benchmark app program, can perform an app that compresses video files, and the test data is tested by compressing an appropriate video file. However, if the computer's application task is tailored to a special purpose such as graphics processing, a graphics generation app and test data that match that can be applied.

Additionally, to evaluate computer performance in terms of mathematical computational capabilities, an app that can calculate mega floating point (Mega FLOPS) operations can be run for evaluation, and equation data for computational processing can be applied as test data. In addition, graphic processing aspects can be evaluated through an app that performs mega instructions (MIPS).

The present invention aims to determine the loss of expected performance due to the heat generation phenomenon of a device element or the influence of transmission delay that occurs when data is written to or read from a device element, and therefore, a corresponding video file compression app is applied to the performance evaluation.

The functional circuit bit cell test unit (254) of Fig. 2 is equipped with a diagnostic program that performs bit cell tests on device elements such as memory to determine the cause when a computer stops or malfunctions, and checks for defects in the elements and abnormal reactions.

The functional circuit bit cell test unit (254) receives test data from the functional circuit bit cell vector data generation unit (255) to perform a test for a device element bit cell test. Normally, when a device element shows rapid failure or in the case of a slow failure, vector data to be tested is selected and supplied to perform an appropriate bit cell inspection.

When a device element exhibits rapid failure, it refers to a clear error failure state in which the bit cell of the memory (230) element does not operate at all, or even if it operates, the cell current leaks immediately, and a slow failure refers to a malfunction in which the memory (230) element operates but the value changes after a certain period of time or is not stored at all. Therefore, the method of diagnosis is to look at the symptom and select and apply test data that matches the symptom from the functional circuit vector data generation unit (255).

The following describes a procedure for measuring computer performance. Performance is the unique performance that is exhibited at a fixed setting for the computer's device components. Recently, as the range of setting values for computer CPUs (210) and memory (230) components has expanded, the performance range has also expanded. Furthermore, even within the same setting values, performance has further improved as the physical properties and microcircuits of the components have become more stable and have developed higher performance.

As the performance range of the computer has been widened in this way, the user can check the performance according to the adjustment of the computer settings by adjusting the settings higher or lower, starting the computer, checking the performance, and then measuring the performance at the adjusted settings, thereby checking the performance for each adjusted setting.

Another reason for measuring performance is that the existing BIOS (220) input/output program has a limitation that it can only connect to the CPU (210) and memory (230) components of the computer when it is initially started, and cannot connect after the operating system is started, so it was difficult to determine the settings of the device components.

Therefore, if you want to use your computer across a wide range of performance capabilities, you need a way to check whether it starts up with various adjusted settings other than the initial BIOS default settings that the computer was manufactured with, and to register and check those adjusted settings in the form of an easily verifiable app program instead of the BIOS.

In the present invention, when adjusting the setting value in the performance diagnosis test unit (250), a performance registration unit (251) that registers the performance and the corresponding value according to the adjustment is provided as an app program.

Additionally, a benchmark app program and test data that can be used to test and confirm what kind of performance is exhibited in the performance registered with the new setting value are provided as an app program from the performance diagnosis test section (250).

The reason for registering the performance of additional settings in the app program is for the convenience of the user, and if the speed of the computer slows down or an abnormality occurs while using it, there is an advantage in that the current settings and performance can be checked through the performance registration program (251) without having to enter the BIOS (220), and also, depending on the symptom of the problem, it can help solve the problem by selecting another performance with the settings adjusted.

Referring to FIG. 3, the process of FIG. 3 shows a process of securing available performance by adjusting the setting value higher or lower, checking whether the computer starts at the adjusted setting value, registering the performance and setting value when the computer starts, and testing how much performance the computer exerts at the registered performance value and recording the result.

In the procedure of Fig. 3, the computer system BIOS (220) on the left shows a process of checking the reference setting value and adjusting the reference setting value higher or lower to start up. In addition, the performance diagnostic test unit (250) on the right shows the available performance range by registering the BIOS setting value through the computer diagnostic test unit app program when the computer is started following the BIOS setting value adjustment process on the left.

Therefore, the process performed in BIOS (220) is a process for preparing for performance adjustment, and the process of the performance diagnosis test section (250) can be said to be a process for performing a performance test and registering and evaluating the test results after the computer is started with new settings.

When a computer is manufactured and released, the motherboard is usually given a set of settings, called reference settings, that allow the device components to operate in an appropriate state.

To check the baseline settings, you need to access the BIOS from the boot screen that appears briefly when the computer starts (220). This is usually done by repeatedly pressing a specific key (F2 or Delete) several times while the computer is booting to access the BIOS setup screen M.I.T. menu. In the M.I.T. menu, you can find the Advanced Memory Information submenu and check the baseline settings for the corresponding frequencies and timings (CPU and RAM frequency, timing, etc.) (S300).

However, since the Step (S300) procedure may vary slightly depending on the motherboard manufacturer, you should refer to the manual. Additionally, instead of checking the baseline settings through the BIOS access screen, as in the Step (S300) procedure, users can obtain the settings directly from the BIOS firmware database.

The settings confirmed in the BIOS M.I.T. screen operation at step (S300) are those initially input to the motherboard, and can be 7 to 8 types of values, including the four major timing values mentioned above, namely the bit cell data fetch timing and power protection timings tCL, tRCD, tRP, and tRAS. Since these settings are already used as reference values for computer startup, there is no need to separately check whether the computer starts according to the settings.

Next, step (S310) is a process for registering a performance standard setting value, in which the BIOS standard setting value of the step (S300) procedure is provided from the BIOS (220) through a program on the performance registration unit (251) and registered as a standard setting value. In addition, in order to confirm the performance in the standard setting, the performance test and data unit (253) can perform a performance test and record the performance result in the performance test unit (253) itself.

The step (S320) procedure is a preparatory procedure for registering the four major timing values for the BIOS (220) by the performance diagnostic test unit (250) as values that are one level higher than the standard setting values. For example, if the representative timing value is CL17 for the CAS latency value, it is adjusted to CL16 to be approximately 1 nanosecond faster, and the remaining three elements are also adjusted to values corresponding to 1 nanosecond faster. More specifically, the read/write latency tRCD can be adjusted to 20, the row charge time tRP to 20, the last strobe time tRAS to 45, and the refresh time tRFC to 600.

Step (S330) is a process for registering advanced settings by the performance diagnosis test unit (250). If the computer is started by assigning the upgraded settings in step (S320) from the BIOS (220), the upgraded settings are registered as advanced settings in the performance registration unit (251) through the performance diagnosis test unit app program, and a performance test and data (253) are performed on the performance, and the results are recorded in the performance test and data unit (253) itself.

However, depending on the typical device characteristics of the computer, if you increase the timing settings by one level, such as the upper setting, the computer may not start. This is because the device components cannot withstand the high timing settings, causing heat generation or malfunction.

Similarly, if a computer device operates reliably at high timing and frequency, the computer can boot up when the frequency is increased one step further. To verify these device characteristics, the computer must be gradually increased to higher settings and its boot up must be confirmed (S340).

If the computer is started at a setting value that is adjusted one level higher than the upper setting value, the setting value is registered as a next-level setting value in the performance registration unit (251), and a performance test is performed in the performance test and data unit (253), and the result is recorded as the next-level performance value (S350).

In step (S350), in the present invention, since the computer is not started at the second upward setting value (S340) following the first upward setting, the first upward value tested immediately before is registered as the maximum setting value in the performance registration unit (251). Since the performance performance test for the registered upward value has already been performed in the upper setting value registration procedure, it is preferable to replace it with the performance performance test and data recorded in the data unit (253).

In step (S360), the performance register (251) lowers the timing by one step from the reference setting value in order to measure the low performance that operates the computer at a low speed for the BIOS (220). For example, if the reference setting value of the CAS latency tCL, which is the waiting time to find the bit cell row and column address, was CL17, it is adjusted to CL18, which is 1 nanosecond slower, and the remaining three timings tRP, tRAS, tRFC, etc. are also adjusted to be approximately 1 nanosecond slower to match this, and the computer system is checked for startup.

In step (S370), when the computer is started at a lower setting value, the setting value is registered as a lower setting value in the performance registration unit (251), and the performance test and data unit (253) can test the performance for the lower setting value and record the result.

When the computer starts up by continuously lowering the memory timing wait time from the above lower setting value, it is registered as the next lower setting value, and if it does not start up at the lowered setting value, the performance registration unit (251) performs registration of the setting value that was started up just before as the lowest setting value.

In the step (S380) procedure, the lower or minimum setting value is obtained, and the computer startup is confirmed in the step (S390), and the performance test and data section (253) can test the performance according to the confirmed value and record the result. However, in the present invention, since the computer was not started when the performance test and data section (253) was set to the lower setting, the immediately previous lower setting value can be registered as the minimum setting value, and the performance result can be recorded as the minimum performance.

During the setup process in Figure 3, the computer naturally adjusts to the maximum setting while determining the possible upward and downward performance levels. However, it may freeze or malfunction during the process. This is due to the computer's limited performance range. In such cases, performance can be improved by replacing the device components. However, if replacement is not possible, the computer must be operated within its current performance range.

When adjusting the settings upward or downward, computer freezes or malfunctions occur because the computing power of the device is reduced or the device cannot keep up with the high or low frequency. The reason the device cannot keep up when the settings are adjusted upward or downward is because the memory controller cannot properly meet the signal processing conditions under the pressure created by the adjusted timing latency.

The identification of upper, reference, and lower setting values in the present invention is possible because the device element can perform signal processing within the adjusted range. By identifying the range of setting values within which the device element can operate, the computer secures performance according to each setting value, and these ranges form the upper, reference, and lower performance levels of the computer's performance.

However, if a higher-level setting is made above a higher-level setting, the computer does not boot, and if a lower-level setting is made below a lower-level setting, the computer does not boot. In cases like this where the computer does not boot immediately, the device component's signal processing is impossible, and the performance registration unit (251) performs registration on its own.

However, if the computer boots but the operating speed becomes slow immediately after booting when changed to a higher or lower level setting, or the computer stops or malfunctions, this is judged to be a speed reduction error caused by the device element signal processing process becoming slow due to the device element's heat generation, etc., and is registered as a speed reduction error in the performance registration unit (251). The speed reduction after booting can be confirmed by reading the temperature value higher than the normal level in the application that checks the motherboard temperature.

If the computer boots up in a higher or lower level setting and does not stop immediately, but instead malfunctions after being used for a considerable period of time, this is judged to be an error that occurs due to the slow response caused by the value of the bit cell being stressed or delayed rather than due to a heat phenomenon, and is therefore registered as a bit cell error in the performance register (251).

In order to confirm that a bit cell error has been registered, the bit cell verification procedure according to the error occurrence rate of FIGS. 5 and 6 of the present invention can be performed in the functional circuit bit cell test unit (254) to confirm.

Next, the performance diagnostic test unit (250) measures the performance of the computer at each set value and obtains a distribution diagram showing the trend of the values, which can be used as a basis for intuitive judgment on utilizing the computer performance.

Evaluating a computer's performance should be performed using appropriate samples, depending on the intended use of the computer. For example, in the present invention, performance values are measured by performing video file compression on a computer with preset values assigned to the performance test and data section (253), and the performance value trend according to the corresponding preset value range is graphically plotted, thereby allowing an intuitive understanding of the overall performance.

This test application demonstrates how well a computer's compression performance improves when adjusting the settings of its device components. This application utilizes an MP4 video compression application. The test data is an MP4 video file, approximately 1.3 gigabytes in size—equivalent to a typical movie—and the performance is measured.

Figure 4 shows the experimental results of video compression performance as a function of the ratio of adjusted settings to the reference settings, and is a diagram showing the trend of performance changes in the upper (412), reference (411), and lower (410) setting ranges. In this experiment, the CAS waiting time tCL is set as a representative setting value to enable a simple comparison, and the change in performance in response to changes in that value is presented as a compression performance value.

The ratio of the adjusted setting to the baseline setting represents the degree to which the signal processing speed of a device is accelerated or decelerated. Typically, shortening the device's setting, such as the CAS latency, accelerates signal processing speed, and consequently, the computer's compression performance is expected to improve.

Therefore, since the increase or decrease in compression performance is proportional to the adjustment ratio of the setting value, the compression performance trend diagram of Fig. 4 shows the change in the performance value based on the ratio of the adjusted setting value to the reference setting value, and the ratio of the setting value adjusted by acceleration or deceleration to the reference setting value is defined as the acceleration rate.

The present invention determines the contribution of changes in acceleration rate to compression performance by measuring performance. If the performance is proportional to the change in acceleration rate, the device is deemed efficient. If the measured change in performance is not proportional after applying an acceleration rate to a computer, it is ineffective, and therefore, it is recommended not to adjust the acceleration setting.

By shortening the CAS latency, which is set as the representative value of the device component settings, the computer is expected to exhibit higher compression performance due to the increased acceleration rate. However, if the device component experiences thermal resistance or signal processing delays at high settings, the acceleration rate's effects will be offset, preventing further increases.

As an example of the acceleration rate of the present invention, in order to reduce the CAS waiting time by approximately 1 nanosecond, tCL is adjusted from 17 to 16. At this time, the acceleration rate is expressed as the value obtained by dividing the adjusted waiting time 16 by the denominator with the standard waiting time 17 as the numerator, i.e., 1.07 or 7%, as the accelerated acceleration rate (412 in FIG. 4).

Referring to FIG. 4, when the computer device component setting value is adjusted, if the result of the sample data obtained by performing a compression test at the setting value is divided by time, the compressed data size per time is obtained, so in the present invention, the compression size per second (MB/sec) comparison value is obtained, and that value is regarded as the compression performance, and is used as a compression performance index that can compare the performance according to the computer setting value (413, 414, 415 in FIG. 4).

As an example of the compression performance test of Fig. 4, the setting values of the device elements are as follows.

The clock frequency of the central processing unit (CPU) (210) is 3,950 MHz, and the DRAM memory DRAM frequency of 2,666 MHz is set as the reference frequency (see 440 in Fig. 4), and the CAS latency tCL 17, the read latency tRCD-RD 20, the write latency tRCD-WR 20, the row charge time tRP 20, the last strobe time tRAS 45, the refresh time tRFC 600, and the DRAM voltage are set to 1.35 V.

In the above settings, the performance test for a video file of 1,365.6 MB in size and the compression test of the data section (253) took 48.8 seconds, which shows a video compression performance of 28 MB/s (414) when converted to performance per second.

To see that the compression performance is improved by accelerating the setting value, the acceleration rate setting value indicated by 411 in Figure 4 is increased by one step as follows.

The DRAM frequency is set to 2,666 MHz, and the CAS latency tCL is adjusted to 16, the read latency tRCD-RD to 18, the write latency tRCD-WR to 18, the row charge time tRP to 18, the last strobe time tRAS to 42, the refresh time tRFC to 560, and the DRAM voltage to 1.35 V are each adjusted in the performance diagnostic test section (250).

In the above settings, a compression test on a video file of 1,365.6 MB in size took 44.9 seconds, which is equivalent to a compression performance of 30.4 MB/s (see 415 in Fig. 4) when converted to a performance per second. This means that when the timing acceleration rate was increased by 7%, the video compression performance was increased by 8.6%.

In the present invention, the process of accelerating the setting value is performed only up to the upper setting value adjusted one level above. In addition, the setting value is adjusted downward as follows to confirm the lower setting value that operates the computer at a low speed.

The DRAM DRAM frequency is set to 2,666 MHz, the CAS latency tCL is adjusted to 18, the read latency tRCD-RD is adjusted to 24, the row charge time tRP is adjusted to 24, the last strobe time tRAS is adjusted to 48, the refresh time tRFC is adjusted to 630, and the DRAM voltage is adjusted to 1.35 V by the performance diagnostic test unit (250).

In the compression test on a video file of 1,365.6 MB in the above low settings, it took 51.7 seconds, which converted to a compression performance of 26.4 MB/s (see 413 in Fig. 4). In summary, when the timing acceleration rate is lowered by 6% from the base setting, the compression performance is slowed down by 5.7%.

Table 1 shows the memory timing acceleration rate for viewing the compression performance of three acceleration rate sections (lower 410, standard 411, upper 412) obtained by adjusting the memory timing, and shows the results of each compression performance (413, 414, 415) obtained according to the value. Table 1 is a diagram showing the compression performance experimental values and frequency-adjusted compression performance measurements by memory timing acceleration rate.

Application acceleration rate Compression performance
(Reference frequency:
2666 Mhz) Compression performance
(Upstream frequency:
3200 Mhz) 0.89 Lower 0.94 26.4 28.5 Criterion 1 28 30.4 Advanced 1.07 30.4 32.6 1.14

Next, we will look at the registration of computer performance ranges and quality maintenance ranges.

Regarding the three acceleration rate increases and decreases above, the compression performance increases by 8.6% when it increases and decreases by 5.7% when it decreases, although there is a slight difference, which is evaluated as a proportional increase in the compression performance compared to the acceleration rate in the set value range.

This demonstrates that accelerated timing contributes steadily to computer performance. If the signal processing speed of the device components is uneven in response to timing changes, high-intensity testing, such as video compression, can generate heat, preventing the computer from exhibiting a proportional increase or decrease in performance.

When the above standard setting value is adjusted to upper and lower levels, the performance shows proportional characteristics from the lowest performance to the highest performance, and since that range is the available performance range in which the computer can operate, it is registered as the available performance range in the performance register (251), which is the system register.

When the performance is measured at the above-mentioned higher or lower setting values and the result does not show a proportional characteristic but a decreased value, the cause is determined by measuring the temperature of the CPU (210) and memory (230) elements and determining that the delay in processing speed due to heat generation offsets the increase in performance, resulting in a decreasing trend rather than a proportional characteristic or a malfunction. In this case, the setting value with decreased performance is registered as an unavailable section.

However, when the proportional performance characteristic is lowered, but the performance indicator deterioration is relatively small and the temperature increase rate is less than the reduced performance indicator rate, the quality of the computer is judged not to have deteriorated, and the corresponding setting value is registered as an available range.

The computer performance index values expressed in the above-mentioned quality-maintained setting value range are registered as performance range values, and the ratio of the highest performance to the lowest performance is registered as the performance guarantee rate. In addition, the setting value range where the above-mentioned minimum and maximum performance index values are secured is registered as the quality maintenance range, and the ratio of the highest setting value to the lowest setting value is registered as the quality guarantee rate.

As can be seen in the table above, compression performance can be improved by increasing the frequency of DRAM memory, not just the timing. Therefore, the present invention proposes a method of increasing the transmission speed by increasing the memory clock frequency by one step, thereby obtaining higher compression performance.

As a setting value for obtaining the upper limit of the adjustment section, the compression performance according to the setting value was obtained at the upward clock (450) where the memory frequency was increased to 3,200 MHz, and the compression performance was 28.5 (416), 30.4 (417), and 32.6 MB/sec (418) for three sections of the reference clock (2,666 MHz), respectively.

This shows that the compression performance improved by approximately 8.6% when the memory frequency was increased by 20% from the reference timing (1), and 7.2% when the timing was increased by one unit (1.07). If we interpret this based on Shannon's information transmission channel formula, it can be seen that the signal-to-noise ratio remains the same, but by making the timing faster, the channel connection capacity was increased, so the data transmission amount was improved accordingly.

According to this result, the present invention regards the compression performance (418) obtained by adjusting the timing acceleration rate and memory clock frequency as the maximum computer performance that can be obtained, and records it in the performance register (251).

FIG. 5 is a diagram showing an algorithm flow chart for determining the location and size of the malfunction of the bit cell, a decrease in the response speed, etc. by performing a bit cell inspection on the corresponding device circuit when the device is operated by setting the setting value for increasing or decreasing the performance of the device in an upward or downward step according to an embodiment of the present invention, and an unstable state or malfunction occurs due to deviation from the proportional performance.

The performance diagnostic test unit (250) selects a memory test routine (S501). Specifically, the performance diagnostic test unit (250) can select a test routine for a Fail at a value lower than the average set value, a Fail due to heat generation, a Fail during operation (transition to a gentle test), a full test, or a sample test.

After step (S502), the performance diagnostic test unit (250) performs bit cell test data selection (S502), and can perform rapid stop test data inspection.

After step (S502), the performance diagnostic test unit (250) determines the test results and measures the test time (S503).

According to the measurement for step (S503), the performance diagnostic test unit (250) determines whether the memory is operating normally (S504).

If the result of the judgment in step (S504) is not operating normally, the performance diagnostic test unit (250) outputs a component abnormality response message (S506) and performs administrator standby (S511).

Meanwhile, if the result of the judgment in step (S504) is normal operation, the performance diagnostic test unit (250) determines whether the functional circuit inspection time is normal (S505).

If the judgment result of step (S505) is normal, the performance diagnosis test unit (250) performs an update of the component inspection time (S510).

If the judgment result of step (S505) is not normal, the performance diagnostic test unit (250) performs an evaluation of the required time (S507). For example, the evaluation can be performed as a percentage of the standard inspection time, such as 0.4/0.2/0/-0.2.

Afterwards, the performance diagnostic test unit (250) can perform a component reactivity update (S508) and output a notification message along with a memory low-speed timing clock in-depth test request output (S509).

FIG. 6 is a flowchart of an algorithm for determining a malfunction due to slow response of a semiconductor device or a slow failure that has not been verified when performing a bit cell inspection in an inspection mode in a performance diagnosis system using a computer acceleration rate algorithm according to one embodiment of the present invention.

The performance diagnostic test section (250) selects a gentle memory test routine (S601), and can perform a sample test (zone 2) or a full test and element failure occurrence characteristic setting.

After step (S601), the performance diagnostic test unit (250) can check for defective cells by reading the value after half the waiting time for writing/writing/refreshing the pattern to the bit cell background data/writing the maintenance value pattern and comparing it with the test value (S602).

After step (S602), the performance diagnostic test unit (250) determines the test results and measures the test time (S603).

After step (S603), the performance diagnostic test unit (250) determines whether the memory is operating normally based on the measurement for step (S603) (S604).

If the result of the judgment in step (S604) is not operating normally, the performance diagnostic test unit (250) outputs a component abnormality response message (S606) and performs administrator standby (S611).

Meanwhile, if the judgment result of step (S604) is normal operation, the performance diagnostic test unit (250) determines whether the functional circuit inspection time is normal (S605).

If the judgment result of step (S605) is normal, the performance diagnostic test unit (250) updates the component inspection time (S610).

Meanwhile, if the judgment result of step (S605) is not normal, the performance diagnostic test unit (250) performs an evaluation of the required time (S607). For example, the evaluation can be performed as a percentage of the standard inspection time, such as 0.4/0.2/0/-0.2.

Afterwards, the performance diagnostic test unit (250) can perform a component reactivity update (S608) and output a notification message along with a memory low-speed timing clock in-depth test request output (S609).

The present invention can also be implemented as computer-readable code on a computer-readable recording medium. A computer-readable recording medium includes any type of recording device that stores data readable by a computer system. The computer-readable recording medium can be distributed across network-connected computer systems, allowing the computer-readable code to be stored and executed in a distributed manner. Furthermore, functional programs, codes, and code segments for implementing the present invention can be readily inferred by programmers in the technical field to which the present invention pertains.

As described above, the present specification and drawings have disclosed preferred embodiments of the present invention. Although specific terms have been used, they are used in a general sense only to easily explain the technical contents of the present invention and to assist in understanding the invention, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein.

100: Inspection Control and Result Generation Department
200: Performance Diagnosis System Using Computer Acceleration Algorithm
210: Central Processing Unit (CPU)
220: Basic Input/Output System (BIOS)
230: Memory
240: Storage media (SSD)
250: Performance Diagnostic Test Section

Claims (5)

delete delete A first step is to increase the computer acceleration rate by increasing the benchmark production input value to increase productivity in the proportional acceleration rate range of the computer;
A second step of determining that the performance indicator of the corresponding acceleration rate increase section is stable when the production volume in the acceleration rate increase section is a value proportional to the input value or a value within the error range;
In the case where the performance indicator of the above production quantity deviates from the proportional value and does not reach the average value and thus does not show a stable performance indicator, a third step is to determine whether the cause is due to a distracting effect including a decrease in load processing speed or a heat generation phenomenon by measuring the load value and temperature of the device element and comparing them with the average value to determine the cause; and
A performance diagnosis method using a computer acceleration rate algorithm, characterized in that it includes a fourth step of registering a performance erosion rate as a computer quality deterioration rate to determine that an increase in the load value and temperature of a device element has eroded the performance indicator. In claim 3,
A method for diagnosing performance using a computer acceleration rate algorithm, characterized in that it further includes a step of determining whether the cause is a heat generation phenomenon of a device component when the temperature of the device component is measured when the temperature of the device component of the computer is measured and the value of the increase in the temperature of the device component of the computer does not correspond to the dangerous temperature of the Windows operating system, or if the rate of increase in the performance indicator is higher than the rate of the temperature increase, it determines that the temperature increase of the device component has not affected the performance degradation. delete