KR19980043600A - Serial EEPROM Controller - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial EEPROM controller, and more particularly, to an EEPROM controller that enables a CPU to access only a buffer memory composed of a general DRAM or SRAM so as to quickly read and write data of the serial EEPROM. The serial EEPROM controller 100 of the present invention is a buffer memory area 45 allocated on the data memory 40 instead of the CPU 20 directly accessing the serial EEPROM 10 after the system has booted up. EEPROM data is read sequentially and downloaded to the buffer memory 45 allocated on the data memory 40 so that EEPROM data can be read and written by the system. During the update, the HOLD signal is sent to the CPU 20 to prevent the CPU 20 from accessing the EEPROM data. When the EEPROM controller of the present invention is employed in the system, instead of driving the EEPROM in a complicated manner as in the prior art, the EEPROM data can be read and written directly through the CPU bus as in general data memory, thereby improving the efficiency of the CPU program. You can increase it. Also, if the EEPROM controller is used to download the EEPROM data to the buffer memory only once at system power-up, then the CPU can access the EEPROM directly instead of taking a long time each time the EEPROM data is read. By directly reading the data in the short buffer memory, the time taken to read the data can be greatly reduced.

Description

Serial EEPROM Controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial EEPROM controller, and more particularly, to an EEPROM controller that enables a CPU to access only a buffer memory composed of a general DRAM or SRAM so as to quickly read and write data of the serial EEPROM.

In general, the EEPROM is a non-volatile memory that can read and write, and is widely used to store important data that must be maintained even when the power is turned off. Particularly, among EEPROMs, serial EEPROMs, which are inexpensive, small in size and low in power consumption, are most widely used in portable terminals such as mobile phones.

1 is a block diagram of a system according to the prior art in which a CPU accesses a serial EEPROM through a serial controller. As shown in FIG. 1, in a conventional system, a serial EEPROM 10 is connected to a serial controller via a serial bus. And a serial controller 50 and a CPU 20 connected to the CPU bus 60. The data and the program are respectively connected to the data memory 40 and the program memory 30, each of which is composed of DRAM or SRAM. It is stored and configured to be accessed by the CPU 20 via the CPU bus 60.

In the above system, when the CPU 20 reads EEPROM data from the serial EEPROM 10 or writes to the serial EEPROM 10, the serial EEPROM 10 must be accessed through the serial controller 50.

As such, when the CPU 20 accesses the EEPROM 10 through a serial bus, each time reading and writing takes about 1 to 20 μsec per byte (for reference, the data memory is directly accessed through the CPU bus). In this case, it takes about 100 nsec), and since the CPU 20 must drive the serial controller 50 every time the EEPROM 10 is accessed, a driver for reading and writing the EEPROM 10. Program is required separately. In addition, since the EEPROM 10 takes a long time, such as 2 to 10 msec, to completely write data to the actual memory cell, in the system where real-time processing is required, such as a mobile phone, the data is stored in the EEPROM 10. To ensure that it is written, failure to process other tasks for a few msecs can cause real-time behavior that can lead to many problems. Therefore, in order to prevent the data from being read before the data is completely written to the EEPROM 10 and to make the data write reliable, the EEPROM data management algorithm for this should be included in the CPU program.

For these reasons, in the conventional system using the serial EEPROM, not only it takes a long time to read and write the EEPROM, but also has problems such as a large CPU program in order to secure the reliability of the EEPROM data.

After all, the present invention is to solve the above problems of the prior art, the object of the present invention is to automatically maintain the reliability of the EEPROM data, even if the CPU does not care about the time it takes to write the data to the EEPROM at all, The present invention provides an EEPROM controller that can significantly reduce the access time of EEPROM data.

1 is a block diagram of a system according to the prior art in which a CPU is configured to access a serial EEPROM via a serial controller;

2 is a block diagram of a system employing a serial EEPROM controller according to a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: Serial EEPROM20: CPU

30: program memory 40: data memory

45: EEPROM buffer memory 50: Serial controller

60: CPU Bus 100: Serial EEPROM Controller

In order to achieve the above object, the serial EEPROM controller according to the present invention reads the EEPROM data by accessing the buffer memory area allocated on the data memory, instead of directly accessing the serial EEPROM by the CPU after the system has booted up. In order to be able to write, EEPROM data is read sequentially and downloaded to the buffer memory allocated on the data memory when the system is powered on, while a hold signal is sent to the CPU when the serial EEPROM data is moved or updated. Is configured to prevent access to the EEPROM data.

Hereinafter, the configuration and operation of a serial EEPROM controller according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a system employing a serial EEPROM controller according to a preferred embodiment of the present invention, in which the same reference numerals are used for the same components as those of FIG.

As shown in FIG. 2, the serial EEPROM controller 100 of the present invention is provided on the data memory 40 instead of the CPU 20 directly accessing the serial EEPROM 10 after the system is booted up. The EEPROM data is sequentially read and downloaded to the buffer memory 45 allocated on the data memory 40 so that the EEPROM data can be read and written by accessing the buffer memory area 45 allocated to the system. When the serial EEPROM data is moved or the data is updated, a hold signal is sent to the CPU 20 to prevent the CPU 20 from accessing the EEPROM data.

The operation principle of the serial EEPROM controller of the present invention will be described in the following.

(1) The CPU 20 allocates a buffer memory area 45 of the same size as the serial EEPROM 10 capacity on the data memory 40, and the memory capacity and the buffer memory 45 of the serial EEPROM 10 are allocated. The area is written to the register of the EEPROM controller 100.

(2) When the system is booted up, when a download command is given to the EEPROM controller 100, the EEPROM controller 100 sequentially reads data of the serial EEPROM 10 and buffers the memory 45 on the CPU data memory 40. Transfer it to At this time, in order to prevent the CPU 20 from using the CPU bus 60 during data download, the EEPROM controller 100 sends a hold signal to the CPU 10. The hold signal is the same as the HOLD signal used by the Intel 86 series CPU. When the hold signal is 1, the EEPROM controller 100 causes the CPU bus (60) to terminate immediately. Generate a HOLD ACK signal (corresponding to the Intel 86 series HLDA signal) and stop using the bus.

According to the above process, when the download of the EEPROM data is completely completed, the CPU 20 reads the data in the buffer memory 45 instead of directly accessing the serial EEPROM 10 to read the EEPROM data. This can greatly reduce the time it takes to read.

(3) On the other hand, even when the data value of the EEPROM 10 is to be updated, the CPU 20 does not directly access the EEPROM 10, but the EEPROM 10 is stored in the buffer memory 45 on the data memory 40. Write the data to write. When writing to the buffer memory area 45 as described above, the EEPROM controller 100 generates a hold signal during a write cycle, and stores the data address and data value of the EEPROM 10 in a register. When writing of the buffer memory of the CPU 20 is completed and a HOLD ACK signal is generated, the EEPROM controller 100 writes data stored at an already stored EEPROM address through a serial bus connected to the EEPROM 10 and writes the data to the EEPROM 10. Check that the data is written correctly. When the data checking process is finished, the hold signal is set to 0 (Low) so that the CPU 20 can use the bus 60 again. During this process, while the EEPROM controller 100 updates and confirms the EEPROM data, it sends a hold signal to the CPU 20, and since the CPU 20 receives the hold signal and stops using the bus 60, Reading or writing data of the EEPROM 10 is automatically prevented.

Accordingly, the serial EEPROM controller 100 according to the present invention secures the data reliability of the EEPROM 10 through the above process, while the CPU 20 does not recognize the EEPROM 10 at all and reads and writes it to a general data memory. The data of the EEPROM 10 can be read and updated. In this case, the connection between the EEPROM 10 and the EEPROM controller 100 may vary according to the type of the EEPROM 10.

As described above, when the EEPROM controller of the present invention is employed in the system, instead of driving the EEPROM in a complicated manner as in the prior art, the EEPROM data can be read and written directly through the CPU bus as in the general data memory. The efficiency of the CPU program can be increased. Also, if the EEPROM controller is used to download the EEPROM data to the buffer memory only once at system power-up, then the CPU can access the EEPROM directly instead of taking a long time each time the EEPROM data is read. By directly reading the data in the short buffer memory, the time taken to read the data can be greatly reduced.

Claims (1)

Instead of directly accessing the serial EEPROM after the system's power boot, the EEPROM data is read sequentially during system power-on so that the EEPROM data can be read and written by accessing the allocated buffer memory area on the data memory. It is configured to download to a buffer memory allocated on the data memory, and to send a HOLD signal to the CPU during the movement of the serial EEPROM data or during the data update to prevent the CPU from accessing the EEPROM data. Serial EEPROM Controller.