KR19990038106A - Column selection line disable control circuit and semiconductor memory device using same - Google Patents

Abstract

A column select line disable control circuit and a semiconductor memory device using the same are disclosed. The column select line disable control circuit logically multiplies a block write master signal generated in response to an externally applied block write command and a control signal generated in response to an externally provided column address strobe command and multiplies the result thereof by a predetermined value. A delay unit for delaying by time, a latch unit for latching an output signal of the delay unit, an automatic pulse generator for generating an automatic pulse by inputting the clock, an output signal of the latch unit, and an output signal of the automatic pulse generator unit And a logic unit for generating a signal for disabling the column select line by AND. Therefore, the column select line disable control circuit can variably adjust the disable timing of the column select line according to the clock cycle time, and includes the column select line disable control circuit and has a synchronous interface and a block light function. The semiconductor memory device can selectively operate as one cycle block light or two cycle block writes depending on the cycle time of the clock.

Description

Column selection line disable control circuit and semiconductor memory device using same

The present invention relates to a semiconductor memory device, and more particularly, to a column select line disable control circuit of a semiconductor memory device having a synchronous interface and a graphic function.

In the case of a semiconductor memory device having a synchronous interface and a graphic function, the specification of the block light is performed by one cycle block light when tBWC≤tCC and tBWC≥tCC based on the cycle time of the operation clock (hereinafter referred to as tCC). It is specified to perform 2 cycle block light. Here, tBWC refers to a time from a time point at which a block write command is input to a time point at which a next block write command is input. In addition, based on a predetermined cycle time, that is, a predetermined frequency, one cycle block write is performed when the operating frequency is less than or equal to the predetermined frequency, and two cycle block writes are performed when the operating frequency is greater than or equal to the predetermined frequency. . In the block write function, unlike a general write function in which one row and one column are selected and writing is performed, one row is selected and a plurality of columns are simultaneously selected to write to a plurality of memory cells at the same time. Therefore, if the cycle time is faster, it is difficult to perform the block light during one cycle. Therefore, as described above, it is prescribed to selectively perform the one cycle block light and the two cycle block light on the basis of the predetermined cycle time.

1A and 1B are timing diagrams illustrating a method of controlling a column select line (CSL) at the time of block writing in a semiconductor memory device having a conventional synchronous interface and a graphic function. FIG. 1A is a case of one cycle block light, and FIG. 1B is a case of two cycle block light. When the column select line CSL is enabled, data is written to the memory cell.

Referring to FIG. 1A, the one cycle block write according to the prior art applies a block write command BW CMD at a predetermined cycle of an operation clock CLK, and then applies the block write command BW CMD again at a first next cycle. Is performed. In more detail, when the first block write command BW CMD is applied, the master signal Φ BW, which informs the block write operation in response thereto, is active as the logic “high” and remains. In addition, ΦCP, which is a signal for controlling the column selection line CSL, is generated in response to the operation clock CLK. The ΦCP is a pulse that becomes a logic "low" when the block write command BW CMD is applied. Has Accordingly, the column select line CSL is enabled and disabled in response to the Φ CP with the Φ BW being logic "high." That is, the column select line CSL is disabled as logic "low" when the φCP is logic "low" and the column select line CSL is logic "high" when the ΦCP is logic "high". Is enabled.

Referring to FIG. 1B, the two-cycle block write according to the prior art applies a block write command BW CMD at a predetermined cycle of the operation clock CLK, and then applies a block write command BW CMD again at a second next cycle. Is performed. In more detail, when the first block write command BW CMD is applied, the master signal Φ BW, which responds to the block write operation in response to the logic " high ", is activated for a predetermined time until the second next cycle. The φ BW is previously non-active to logic “low”, and in response to the block write command BW CMD being applied again in the second next cycle, the φ BW is again active to logic “high”. In addition, ΦCP, which is a signal for controlling the column selection line CSL, is generated in response to the operation clock CLK. The ΦCP is a pulse that becomes a logic "low" when the block write command BW CMD is applied. Has Accordingly, the column selection line CSL is enabled and disabled in response to the Φ CP and the Φ BW. That is, the column select line CSL is disabled as a logic "low" when the Φ CP becomes a logic "low" or the Φ BW becomes a logic "low", otherwise the column select line CSL is disabled. Is enabled.

In the prior art, two cycle block lights are performed as a default, and a user can selectively use one cycle block light if necessary. Therefore, in the above-described prior art, although one cycle block light is possible at a predetermined cycle time, a case in which the two cycle block lights should be used may occur.

Accordingly, an object of the present invention is to operate a semiconductor memory device having a synchronous interface and a block write function by default as two cycle block lights, and selectively operating as one cycle block light or two cycle block lights according to the cycle time of a clock. The present invention provides a column select line disable control circuit.

Another object of the present invention is to provide a semiconductor memory device which has a synchronous interface and a block light function, and is basically operated as a two cycle block light and capable of operating as one cycle block light or two cycle block lights according to the cycle time of the clock. have.

1A and 1B are timing diagrams illustrating a method for controlling a column selection line at the time of block writing in a semiconductor memory device having a conventional synchronous interface and a graphic function.

2 is a schematic block diagram of a column select line disable control circuit and a semiconductor memory device including the same according to an embodiment of the present invention.

FIG. 3 is a timing diagram of signals of the column select line disable control circuit shown in FIG.

The column selection line disable control circuit of the semiconductor memory device according to the present invention for achieving the above object has a synchronous interface operated by a clock applied from the outside, one row is selected and a plurality of column selection lines are simultaneously A column select line disable control circuit of a semiconductor memory device having a block write function that is enabled and writes to a plurality of memory cells simultaneously.

A delay unit for multiplying a block write master signal generated in response to an externally applied block write command and a control signal generated in response to an externally applied column address strobe command and delaying the result by a predetermined time; Disables the column select line by logically multiplying a latch unit for latching a negative output signal, an automatic pulse generator for generating an automatic pulse by inputting the clock, and an output signal of the latch unit and an output signal of the automatic pulse generator. And a logic unit for generating a signal to make a signal.

The column select line is enabled as logic "high" when the block write command is input and is disabled as logic "low" when the signal for disabling the column select line is activated as logic "high".

In addition, the semiconductor memory device according to the present invention for achieving the above object, a synchronous interface operated by a clock applied from the outside, a row is selected and a plurality of column selection lines are enabled at the same time a plurality of memory cells And a block selection function for controlling the disable time of the column selection line according to the cycle time of the clock.

The column select line disable control circuit may include a delay unit which multiplies the block write master signal generated in response to the block write command and the control signal generated in response to the column address strobe command and delays the result by a predetermined time period; And a latch unit for latching an output signal of the delay unit, an automatic pulse generator for generating an automatic pulse by inputting the clock, and an output signal of the latch unit and an output signal of the automatic pulse generator for the column selection line. And a logic section for generating a signal for disabling the signal.

The column select line is enabled as logic "high" when the block write command is input and is disabled as logic "low" when the signal for disabling the column select line is activated as logic "high".

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic block diagram of a column select line disable control circuit and a semiconductor memory device including the same according to an embodiment of the present invention.

2, the semiconductor memory device according to the present invention includes a column select line disable control circuit 21, a column select line (CSL) driving circuit 23, and a memory cell array 25.

The semiconductor memory device has a synchronous interface operated by an externally applied clock CLK, and one row is selected and a plurality of column selection lines CSL are simultaneously driven by the column selection line driving circuit 23. The block write function is enabled to write simultaneously to a plurality of memory cells of the memory cell array 25. Since this is well known to those skilled in the art, a detailed description thereof will be omitted. In particular, the semiconductor memory device may include a column select line disable control circuit 21 that variably adjusts the disable timing of the column select line CSL according to the cycle time of the clock CLK.

The column select line disable control circuit 21 includes a delay unit 21a, a latch unit 21b, an automatic pulse generator 21c, and a logic unit 21d.

In more detail, the delay unit 21a may include a block write master signal Φ BW generated in response to a block write command applied externally and a control signal Φ CA generated in response to a column address strobe command applied externally. Is multiplied by and delays the result by a predetermined time. The latch unit 21b latches the output signal P8NS of the delay unit 21a, and the automatic pulse generator 21c generates the automatic pulse by inputting the clock CLK. The logic unit 21d generates a signal CSLPRE for disabling the column selection line CSL by logically multiplying the output signal of the latch unit 21b and the output signal of the automatic pulse generator 21c.

Here, the delay unit 21a may include a NAND gate ND1 that logically multiplies the block light master signal Φ BW and the control signal Φ CA, an even number of inverters I1, I2, and resistors R1 to R4. And a retarder 21aa configured to include the capacitors C1 and C2 and delay the output signal of the NAND gate ND1, and an output signal P8NS by inverting the output signal of the retarder 21aa. Another inverter I3 which generate | occur | produces is provided.

The latch unit 21b includes a first inverter I4 for inverting the output signal P8NS of the delay unit 21a, an output signal of the first inverter I4, and the block light master signal Φ BW. A first NAND gate ND2 having an input as an input, an output signal of the first NAND gate ND2 and the control signal Φ CA being input, and an output signal being input to the first NAND gate ND2. A second NAND gate ND3, a second inverter I5 for inverting the output signal of the first NAND gate ND2, and a third inverter I6 for inverting the output signal of the second inverter I5. Equipped.

The automatic pulse generator 21c supplies an inverter I7 for inverting the clock CLK, an odd number of inverters I8, I9, I10, resistors R5, R6, R7, and a capacitor C3. And an inverting delay 21ca for inverting and delaying the output signal of the inverter I7, and a noar gate for inputting the output signal of the inverter I7 and the output signal of the inverting delay 21ca. NR1).

The logic unit 21d includes a NAND gate ND4 for inputting the output signal of the latch unit 21b and the output signal of the automatic pulse generator 21c, and an odd number of inverters I11, I12, and I13. And an inverter chain 21da configured to be connected in series and to generate a signal CSLPRE for inverting and buffering the output signal of the NAND gate ND4 to disable the column select line CSL.

FIG. 3 is a timing diagram of signals of the column select line disable control circuit 21 shown in FIG. 2.

An operation of the column select line disable control circuit 21 according to the present invention shown in FIG. 2 will be described with reference to the timing diagram of FIG. 3. Here, the block write master signal Φ BW is activated to be logic " high " when the block write command BW CMD is applied at a predetermined cycle of the clock CLK from outside of the semiconductor memory device. It is a signal that is non-active to logic "low" in the next cycle of, and is activated to logic "high" again when the block write command (BW CMD) is applied again in the next cycle. In addition, the control signal .phi.CA is activated by a logic " high " when a column address strobe CAS command is applied in a predetermined cycle of the clock CLK from the outside of the semiconductor memory device, and then the clock signal of the clock CLK. This signal is non-active with a logic "low" on the falling edge. The block write master signal .phi.BW and the control signal .phi.CA are generated in other circuits not shown here.

First, when the block write command BW CMD and the column address strobe command are applied in a predetermined cycle of the clock CLK from the outside of the semiconductor memory device, the block write master signal Φ BW and the control signal ΦCA) is generated. Accordingly, the block write master signal? BW and the control signal? CA are logically multiplied by the delay unit 21a of the column select line disable control circuit 21, and the result is delayed by a predetermined time to output the output signal. (P8NS). When the output signal P8NS is activated with logic "high", the signal CSLPRE for disabling the column selection line CSL is enabled with logic "high." That is, the enable time of the signal CSLPRE is determined according to the active time of the output signal P8NS of the delay unit 21a, and thus the disable time of the column selection line CSL is determined.

When the cycle time tCC of the clock CLK is large, that is, when the frequency of the clock CLK is low, the output signal P8NS is activated to a logic " high " When the logic section 21d is reached via the automatic pulse generator 21c, the signal CSLPRE is quickly enabled to a logic " high " in response to the output signal P8NS. Therefore, when the cycle time tCC of the clock CLK is large, the column selection line CSL is quickly disabled by a logic "low" in response to the signal CSLPRE which is quickly enabled by a logic "high". (In case of I)

When the cycle time tCC of the clock CLK is small, that is, when the frequency of the clock CLK is high, the first time of the clock CLK before the output signal P8NS is activated to the logic " high " Since the cycle arrives in advance to the logic unit 21d via the automatic pulse generator 21c, the signal CSLPRE is not enabled in the first clock cycle. In the next clock cycle, the output signal P8NS is activated with a logic "high" so that the signal CSLPRE is enabled with a logic "high" late in response to the output signal P8NS. Therefore, when the cycle time tCC of the clock CLK is small, the column selection line CSL is disabled to a logic "low" late in response to the signal CSLPRE being enabled to a logic "high" late. (In case of II)

In conclusion, the signal CSLPRE is quickly read in according to the cycle time of the clock CLK by the output signal P8NS generated in response to the block light master signal Φ BW and the control signal Φ CA. By enabling or late enabling, the disable timing of the column selection line CSL may be variably adjusted according to the cycle time of the clock CLK. Accordingly, one cycle block light or two cycle block lights may be selectively performed according to the cycle time of the clock CLK.

As described above, the present invention has been limited to one embodiment, but not limited thereto. It is obvious that various modifications to the present invention can be made by those skilled in the art within the scope of the spirit of the present invention. .

As described above, the column select line disable control circuit according to the present invention can variably adjust the disable timing of the column select line according to the clock cycle time. Therefore, the semiconductor memory device having the column select line disable control circuit and having the synchronous interface and the block write function can be selectively operated as one cycle block light or two cycle block lights according to the cycle time of the clock.

Claims (17)

A column of a semiconductor memory device having a synchronous interface operated by an externally applied clock, and having a block write function in which one row is selected and a plurality of column selection lines are enabled at the same time so that writing is performed simultaneously to a plurality of memory cells. In the selection line disable control circuit, A delay unit for multiplying a block write master signal generated in response to an externally applied block write command and a control signal generated in response to an externally applied column address strobe command and delaying the result by a predetermined time; A latch unit for latching an output signal of the delay unit; An automatic pulse generator for generating an automatic pulse as the clock; And a logic unit for generating a signal for disabling the column selection line by ANDing the output signal of the latch unit and the output signal of the automatic pulse generation unit. 2. The delay unit of claim 1, wherein the delay unit comprises a NAND gate logically multiplying the block light master signal and the control signal, an even number of inverters, resistors, and capacitors, and delays an output signal of the NAND gate. And another inverter for inverting the output signal of the delayer to generate an output signal. The display device of claim 1, wherein the latch unit comprises: a first inverter for inverting an output signal of the delay unit; a first NAND gate configured to input an output signal of the first inverter and the block write master signal; A second NAND gate to which an output signal of the gate and the control signal are input, and an output signal is input to the first NAND gate, a second inverter to invert the output signal of the first NAND gate, and the second inverter And a third inverter for inverting an output signal. The inverter of claim 1, wherein the automatic pulse generator comprises an inverter for inverting the clock, an odd number of inverters, a resistor, and a capacitor, and an inverting delay for inverting the output signal of the inverter, and an output of the inverter. And a noble gate for inputting a signal and an output signal of the inverting delay unit. The NAND gate of claim 1, wherein the logic unit comprises an NAND gate configured to input an output signal of the latch unit and an output signal of the automatic pulse generator, and an odd number of inverters connected in series to invert the output signal of the NAND gate. And an inverter chain generating a signal for disabling the column select line. 2. The column select line disable control circuit of claim 1, wherein the block write master signal is activated with a logic " high " when the block write command is applied. 2. The column select line disable control circuit of claim 1, wherein the control signal is activated with logic " high " when the column address strobe command is applied. The logic of claim 1, wherein the column select line is enabled as logic "high" when the block write command is input and logic "low" when the signal for disabling the column select line is activated as logic "high". And a column select line disable control circuit of the semiconductor memory device. A semiconductor memory device having a synchronous interface operated by an externally applied clock, and having a block write function in which one row is selected and a plurality of column selection lines are enabled at the same time so that writing is performed simultaneously to a plurality of memory cells. , And a column select line disable control circuit which variably adjusts the disable timing of the column select line according to the cycle time of the clock. 10. The method of claim 9, wherein the column select line disable control circuit is configured to perform an AND operation on a block write master signal generated in response to the block write command and a control signal generated in response to a column address strobe (CAS) command. A delay unit for delaying by a predetermined time, a latch unit for latching an output signal of the delay unit, an automatic pulse generator for generating an automatic pulse by inputting the clock, an output signal of the latch unit, and the automatic pulse generator And a logic unit for generating a signal for disabling the column select line by performing an AND operation on the output signal. 10. The delay unit of claim 9, wherein the delay unit comprises a NAND gate logically multiplying the block light master signal and the control signal, an even number of inverters, resistors, and capacitors, and delays an output signal of the NAND gate. And another inverter generating an output signal by inverting the output signal of the delay device. 10. The display device of claim 9, wherein the latch unit comprises: a first inverter for inverting an output signal of the delay unit; a first NAND gate for inputting an output signal of the first inverter and the block write master signal; A second NAND gate to which an output signal of the gate and the control signal are input, and an output signal is input to the first NAND gate, a second inverter to invert the output signal of the first NAND gate, and the second inverter And a third inverter for inverting the output signal. The inverter of claim 9, wherein the automatic pulse generator comprises an inverter for inverting the clock, an odd number of inverters, a resistor, and a capacitor, and an inverting delay for inverting the output signal of the inverter, and an output of the inverter. And a no-gate for inputting a signal and an output signal of the inverting delay unit. The NAND gate of claim 9, wherein the logic unit comprises an NAND gate configured to input an output signal of the latch unit and an output signal of the automatic pulse generator, and an odd number of inverters connected in series to invert the output signal of the NAND gate. And an inverter chain generating a signal for disabling the column select line. 10. The semiconductor memory device according to claim 9, wherein the block write master signal is activated logic "high" when the block write command is applied. 10. The semiconductor memory device according to claim 9, wherein said control signal is activated with logic " high " when said column address strobe command is applied. 10. The method of claim 9, wherein the column select line is enabled with logic "high" when the block write command is input and logic "low" when the signal for disabling the column select line is activated with logic "high". A semiconductor memory device, characterized in that disabled.