KR20000025638A - Method for forming contacts of semiconductor device - Google Patents
Method for forming contacts of semiconductor device Download PDFInfo
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- KR20000025638A KR20000025638A KR1019980042795A KR19980042795A KR20000025638A KR 20000025638 A KR20000025638 A KR 20000025638A KR 1019980042795 A KR1019980042795 A KR 1019980042795A KR 19980042795 A KR19980042795 A KR 19980042795A KR 20000025638 A KR20000025638 A KR 20000025638A
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- semiconductor device
- forming
- film
- oxynitride
- device manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 22
- 125000006850 spacer group Chemical group 0.000 claims abstract description 15
- 238000004140 cleaning Methods 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 5
- 238000004519 manufacturing process Methods 0.000 claims description 10
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical class O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 claims description 8
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 8
- 229910001930 tungsten oxide Inorganic materials 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000005406 washing Methods 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 콘택을 형성하는 방법에 관한 것으로서, 반도체 소자의 콘택 측벽에 형성되는 스페이서를 옥시나이트라이드로 형성하고, 어닐링을 실시함으로써, 후속 세정공정에서 과도한 세정을 실시해도 식각되지 않고, 그 하부막을 보호함으로써, 층간 단선을 피하고, 소자의 특성을 향상시킬 수 있다. 또한, 층간 절연막 상부에도, 옥시나이트라이드막을 도포함으로써, 세정시 절연막의 과도한 손실을 방지할 수 있다.The present invention relates to a method for forming a contact of a semiconductor device, by forming an spacer formed on the contact sidewall of the semiconductor device with oxynitride and annealing, it is not etched even if excessive cleaning in the subsequent cleaning step, By protecting the lower film, interlayer disconnection can be avoided and device characteristics can be improved. In addition, by applying the oxynitride film on the interlayer insulating film, excessive loss of the insulating film during cleaning can be prevented.
Description
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것으로서, 특히, 반도체 소자의 폴리사이드 전극과 접속되는 폴리사이드 도전층 사이의 콘택저항을 효과적으로 개선하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and more particularly, to a method for effectively improving contact resistance between a polyside electrode of a semiconductor device and a polyside conductive layer connected thereto.
종래의 반도체 소자의 콘택을 형성하기 위한 방법중에 SOSCON 방법이 있다. 도1a에 도시된 바와 같이, 일반적으로 반도체 기판(1) 상에서 게이트 전극(2,3,4,) 옆에 비트라인 전극(8,9)이 형성된다. 이때, 비트라인 전극(9)을 형성하기 위하여 포토마스크 작업을 하는데, 이 포토마스크 작업시 약간의 오정렬이 발생해도 도1b에 도시된 바와 같이, 비트라인 전극(8,9)이 게이트 전극(2,3,4)으로 치우치는 현상이 발생한다. 또한, 반도체 기판(1)의 주변회로 지역에서는 도1c에 도시된 바와 같이, 비트라인 콘택(8,9)이 게이트 전극(2,3,4) 위에 형성되는 부분이 있으며, 이때, 텅스텐 실리사이드막(3) 표면에 쉽게 텅스텐 산화막(20)이 형성되며, 이 텅스텐 산화막(20)은 세정공정에서도 제거되지 않고 남아 콘택 저항을 높이는 문제가 있다. 이러한 텅스텐 산화막을 제거하기 위해서는 BOE(또는 HF) 용액에서 오랫동안 세정해야 한다. 그러나, 과도한 세정공정으로 인해 도1b에 도시된 경우에서와 같이, 콘택 측면 부분의 스페이서 산화막(7)이 제거되어 비트라인과 게이트 전극이 접촉되는 문제를 야기시킬 수 있으며, 또한 절연막의 상부로부터의 손실을 심하게 유발시키는 문제점이 있었다.Among the methods for forming the contacts of a conventional semiconductor device is the SOSCON method. As shown in FIG. 1A, bit line electrodes 8, 9 are generally formed next to gate electrodes 2, 3, 4, on semiconductor substrate 1. At this time, a photomask operation is performed to form the bitline electrode 9. Even though some misalignment occurs during the photomask operation, as shown in FIG. 1B, the bitline electrodes 8 and 9 are connected to the gate electrode 2. , 3, 4) bias occurs. In addition, in the peripheral circuit region of the semiconductor substrate 1, as shown in FIG. (3) The tungsten oxide film 20 is easily formed on the surface, and the tungsten oxide film 20 remains without being removed even in the cleaning process, thereby increasing the contact resistance. In order to remove such a tungsten oxide film, it has to be cleaned for a long time in a BOE (or HF) solution. However, due to the excessive cleaning process, as in the case shown in FIG. There was a problem causing severe loss.
따라서, 전술한 문제점을 해결하기 위해 안출된 본 발명은, 콘택홀 측벽에 옥시나이트라이드를 이용하여 스페이서를 형성하고, 어닐링을 실시함으로써, 장시간의 세정공정을 실시해도 층간의 단선을 피하고, 층간 절연막의 손실을 방지할 수 있는 반도체 소자 제조 방법을 제공하는 것을 목적으로 한다.Therefore, the present invention devised to solve the above-mentioned problem is formed by forming an spacer on the sidewall of the contact hole using oxynitride and annealing, thereby avoiding disconnection between layers even after performing a long time cleaning process, interlayer insulating film Disclosure of Invention It is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent the loss of the semiconductor.
본 발명의 양호한 실시예에 따른 반도체 소지 제조 방법은, 반도체 기판 상부에 게이트 전극을 형성하는 단계; 상기 게이트 전극 측벽에 산화막 스페이서를 형성하는 단계; 전체 구조 상부에 절연막을 증착하는 단계; 상기 절연막 상부에 옥시나이트라이드막을 증착하는 단계; 포토리소그래피 공정을 이용하여 콘택홀을 형성하는 단계; 상기 콘택홀 측벽에 옥시나이트라이드 스페이서를 형성하는 단계; 소정의 온도에서 어닐링을 실시하는 단계; 산화막 제거용 화학용액을 이용하여 세정하는 단계; 및 상기 콘택홀을 매립하여 비트라인을 형성하는 단계를 포함한다.A semiconductor substrate manufacturing method according to a preferred embodiment of the present invention, forming a gate electrode on the semiconductor substrate; Forming an oxide spacer on sidewalls of the gate electrode; Depositing an insulating film over the entire structure; Depositing an oxynitride film on the insulating film; Forming a contact hole using a photolithography process; Forming an oxynitride spacer on sidewalls of the contact hole; Performing annealing at a predetermined temperature; Washing with a chemical solution for removing an oxide film; And filling the contact hole to form a bit line.
도1a 내지 도1c는 종래 기술에 따른 반도체 소자 제조 공정의 단면도.1A to 1C are cross-sectional views of a semiconductor device manufacturing process according to the prior art.
도2a 내지 도2d는 본 발명의 양호한 실시예에 따른 반도체 소자 제조 공정의 단면도.2A-2D are cross-sectional views of a semiconductor device manufacturing process in accordance with the preferred embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11:반도체 기판 12:제1 폴리실리콘막11: semiconductor substrate 12: first polysilicon film
13:텅스텐 실리사이드막 14:옥시나이트라이드막13: Tungsten silicide film 14: Oxynitride film
15:산화막 스페이서 16:절연막15: oxide spacer 16: insulation film
17:옥시나이트라이드 스페이서 18:제2 폴리실리콘막17: oxynitride spacer 18: second polysilicon film
19:텅스텐 실리사이드 20:텅스텐 산화막19: tungsten silicide 20: tungsten oxide film
21:옥시나이트라이드막21: oxynitride film
이하, 첨부도면을 참조하여 본 발명의 양호한 실시예에 대해 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도2a 내지 도2b는 본 발명의 양호한 실시예에 따른 반도체 소자의 콘택 형성 공정을 도시한 단면도로서, 반도체 소자의 주변회로지역도 함께 도시하고 있다. 먼저, 도2a에 도시된 바와 같이, 반도체 기판(11) 상부에 제1 폴리실리콘막(12), 텅스텐 실리사이드막(13), 옥시나이트라이드막(oxynitride)(14)을 증착하고, 마스크를 이용하여 식각하여, 게이트 전극(12,13,14)을 패터닝한 다음, 산화막 스페이서(15)를 형성한다.2A to 2B are cross-sectional views illustrating a process for forming a contact of a semiconductor device according to a preferred embodiment of the present invention, and also showing peripheral circuit areas of the semiconductor device. First, as shown in FIG. 2A, a first polysilicon film 12, a tungsten silicide film 13, and an oxynitride film 14 are deposited on the semiconductor substrate 11, and a mask is used. By etching to pattern the gate electrodes 12, 13, and 14, and then form an oxide film spacer 15.
다음에는, 도2b에 도시된 바와 같이, 전체 구조 상부에 절연막(16)을 증착하고, 그 위에 옥시나이트라이드막(21)을 도포한 다음, 마스크를 이용하여 콘택홀을 형성한다. 이때, 도시된 바와 같이, 포토마스크 작업시 오정렬이 발생하면, 콘택홀이 게이트 전극(12,13,14) 쪽으로 치우치는 경우가 발생할 수 있다.Next, as shown in FIG. 2B, an insulating film 16 is deposited over the entire structure, an oxynitride film 21 is applied thereon, and then contact holes are formed using a mask. In this case, as shown in the drawing, when misalignment occurs during the photomask operation, contact holes may be biased toward the gate electrodes 12, 13, and 14.
다음에는, 도2c에 도시된 바와 같이, 종래의 산화막 스페이서 대신에 옥시나이트라이드 스페이서(17)를 콘택홀 측벽에 형성하고, 약 600-900℃, 바람직하게는, 750-900℃의 고온에서 어닐링 공정을 수행한다. 이렇게 형성된 옥시나이트라이드 스페이서(17)는 보통의 산화막 보다 HF나 BOE 화학용액에서의 식각속도(etch rate)가 1000배 이상 느리다. 따라서, 도2c의 주변회로지역에 도시된 바와 같이, 게이트 전극 상부에 비트라인이 형성되는 경우에, 텅스텐 실리사이드 표면에 생기는 텅스텐 산화막(20)을 제거하기 위한 과도한 세정공정에도 종래의 산화막 스페이서와 달리 쉽게 제거되지 않아 비트라인과 게이트 전극이 접촉되는 문제를 해결할 수 있다. 또한, 절연막(16) 상부에도 옥시나이트라이드막(21)이 형성되어 있기 때문에 과도한 세정에도 불구하고, 절연막(16)의 상부로부터의 손실을 막을 수 있다. 또한, 포토리소그래피 작업시 오정렬로 인하여 콘택홀이 게이트 전극쪽으로 치우치는 경우에도 단선을 방지할 수 있다.Next, as shown in Fig. 2C, an oxynitride spacer 17 is formed on the contact hole sidewall instead of the conventional oxide film spacer, and annealed at a high temperature of about 600-900 ° C, preferably 750-900 ° C. Perform the process. The oxynitride spacer 17 thus formed has a etch rate of at least 1000 times slower in a HF or BOE chemical solution than a normal oxide film. Therefore, as shown in the peripheral circuit region of FIG. 2C, when a bit line is formed on the gate electrode, an excessive cleaning process for removing the tungsten oxide film 20 occurring on the surface of the tungsten silicide is performed, unlike the conventional oxide spacer. It is not easily removed, which solves the problem of contact between the bit line and the gate electrode. In addition, since the oxynitride film 21 is formed on the insulating film 16, the loss from the top of the insulating film 16 can be prevented despite excessive cleaning. In addition, disconnection may be prevented even when the contact hole is biased toward the gate electrode due to misalignment during photolithography.
다음에는, 도2d에 도시된 바와 같이, 세정공정을 마친 후, 제2 폴리실리콘막(18)과 텅스텐 실리사이드(19)막을 형성하고, 패터닝하여 콘택을 완성한다.Next, as shown in FIG. 2D, after the cleaning process is completed, a second polysilicon film 18 and a tungsten silicide 19 film are formed and patterned to complete the contact.
전술한 바와 본 발명에 따른 반도체 소자 제조 방법에 있어서는, 텅스텐 산화막을 제거하기 위한 과도한 세정공정에도 어닐링된 옥시나이트라이드 스페이서가 산화막 스페이서와 달리 쉽게 제거되지 않기 때문에, 비트라인과 게이트 전극이 접촉되는 문제를 해결할 수 있으며, 절연막이 상부로부터 손실되는 것을 막을 수 있다. 이렇게 함으로써 텅스텐 실리사이드 표면에 텅스텐 산화막이 생기는 문제를 해결할 수 있게 되며, 따라서, 반도체 소자의 콘택저항을 낮출 수 있고, 반도체 소자의 특성을 향상시켜, 그에 따른 반도체 소자의 고집적화를 가능하게 한다는 효과가 있다.In the semiconductor device manufacturing method as described above and the present invention, the annealed oxynitride spacer is not easily removed unlike the oxide spacer even in an excessive cleaning process for removing the tungsten oxide film, the contact between the bit line and the gate electrode Can be solved, and the insulating film can be prevented from being lost from the top. By doing so, it is possible to solve the problem that a tungsten oxide film is formed on the surface of the tungsten silicide, thereby reducing the contact resistance of the semiconductor device, improving the characteristics of the semiconductor device, and thereby enabling high integration of the semiconductor device. .
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042795A KR20000025638A (en) | 1998-10-13 | 1998-10-13 | Method for forming contacts of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980042795A KR20000025638A (en) | 1998-10-13 | 1998-10-13 | Method for forming contacts of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000025638A true KR20000025638A (en) | 2000-05-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980042795A Withdrawn KR20000025638A (en) | 1998-10-13 | 1998-10-13 | Method for forming contacts of semiconductor device |
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| Country | Link |
|---|---|
| KR (1) | KR20000025638A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299826B2 (en) | 2013-03-13 | 2016-03-29 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
-
1998
- 1998-10-13 KR KR1019980042795A patent/KR20000025638A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299826B2 (en) | 2013-03-13 | 2016-03-29 | Samsung Electronics Co., Ltd. | Memory device and method of manufacturing the same |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19981013 |
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| PG1501 | Laying open of application | ||
| PC1203 | Withdrawal of no request for examination | ||
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |