KR20000044885A - Method for forming isolation film of semiconductor device - Google Patents
Method for forming isolation film of semiconductor device Download PDFInfo
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- KR20000044885A KR20000044885A KR1019980061388A KR19980061388A KR20000044885A KR 20000044885 A KR20000044885 A KR 20000044885A KR 1019980061388 A KR1019980061388 A KR 1019980061388A KR 19980061388 A KR19980061388 A KR 19980061388A KR 20000044885 A KR20000044885 A KR 20000044885A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 소자 분리막 형성 방법이다.The present invention is a method of forming a device isolation film of a semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
본 발명은 질화막상에 부분 식각에 의한 산화막 패턴을 형성하고 이를 식각 마스크로 이용하여 트렌치를 형성하므로서 소자 분리막의 식각 마진을 확보하고자 한다.The present invention is to form an oxide film pattern by partial etching on the nitride film and to form a trench using this as an etching mask to secure the etching margin of the device isolation layer.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
본 발명은 반도체 기판상에 패드 산화막, 질화막 및 산화막을 순차적으로 형성하는 단계와; 상기 산화막 및 질화막의 일부를 패턴화하는 단계와; 상기 패턴화된 산화막의 측벽을 일부 식각하는 단계와; 상기 측벽 일부가 식각된 패턴화된 산화막을 식각 마스크로 이용하여 상기 반도체 기판을 식각하여 트렌치를 형성하고, 동시에 상기 질화막의 노출된 일부가 식각되는 단계와; 상기 트렌치 내부에 열 산화막을 형성한 후, 상기 트렌치를 포함하는 전체 구조상에 절연물을 형성하는 단계와; 상기 질화막이 노출되도록 상기 절연물을 연마한 후, 상기 절연물의 일부를 식각하는 단계와; 상기 질화막을 제거한 후 산화 공정을 통해 소자 분리막을 형성하는 단계로 이루어진다.The present invention comprises the steps of sequentially forming a pad oxide film, a nitride film and an oxide film on a semiconductor substrate; Patterning a portion of the oxide film and the nitride film; Partially etching sidewalls of the patterned oxide film; Etching the semiconductor substrate using a patterned oxide film etched with a portion of the sidewalls as an etch mask to form a trench, and simultaneously etching a portion of the nitride film; Forming an insulator on the entire structure including the trench after forming a thermal oxide film inside the trench; Polishing the insulator so that the nitride film is exposed, and then etching a portion of the insulator; After removing the nitride film and forming an isolation layer through an oxidation process.
Description
본 발명은 1G DRAM, 4G DRAM 또는 16G DRAM 이상의 초 고집적 소자의 제조 공정중 소자 분리막 형성 방법에 관한 것으로서, 더욱 상세히는 질화막상에 부분 식각에 의한 산화막 패턴을 형성하고 이를 식각 마스크로 이용하여 트렌치를 형성하므로서 소자 분리막의 식각 마진을 확보할 수 있는 반도체 소자의 소자 분리막 형성 방법에 관한 것이다.The present invention relates to a method of forming a device isolation layer during a manufacturing process of an ultra-high density device of 1G DRAM, 4G DRAM or 16G DRAM or more, and more particularly, to form an oxide layer pattern by partial etching on a nitride film and using the trench as an etching mask. The present invention relates to a method of forming a device isolation film of a semiconductor device by forming an etching margin of the device isolation film.
일반적으로 소자분리 기술이란 집적소자를 구성하는 개별소자를 전기적 및 구조적으로 서로 분리시켜, 각 소자가 인접한 소자의 간섭을 받지 않고 독자적으로 그 주어진 기능을 수행할 수 있도록 하는데 필요한 기능을 집적소자 제조시 부여하는 기술이다. 고밀도 또는 고집적화라는 관점에서, 소자의 집적도를 높이기 위해서는 개개의 소자의 영역(Dimension)을 축소하는 것도 필요한 동시에 소자와 소자 사이에 존재하는 소자분리 영역의 폭 및 면적을 축소하는 것이 필요하다. 이 축소정도가 셀 사이즈(Cell Size)를 좌우한다는 점에서 소자분리 기술이 메모리 셀 사이즈를 결정하는 기술 중의 하나라고 말해도 과언이 아니다. 그래서 오늘날까지 많은 연구가 되어 왔다.In general, device isolation technology separates the individual devices constituting the integrated device from each other electrically and structurally, so that each device can perform its function independently without interference from adjacent devices. It is a technique to grant. In view of high density or high integration, in order to increase the degree of integration of the device, it is necessary to reduce the dimensions of individual devices, and at the same time, it is necessary to reduce the width and the area of the device isolation region between the devices. It is no exaggeration to say that the device isolation technique is one of the techniques for determining the memory cell size in that this reduction degree determines the cell size. So much research has been done to this day.
도 1은 종래의 소자 분리막 형성 방법을 설명하기 위한 단면도로서, 셀로우 트렌치 소자분리 방법(Shallow Trench Isolation)을 이용하여 소자 분리막이 형성되는 과정이 도시된다.FIG. 1 is a cross-sectional view illustrating a conventional method of forming a device isolation layer, and illustrates a process of forming a device isolation layer using a shallow trench isolation method.
반도체 기판(1)상에 패드 산화막(도시 안됨) 및 패드 질화막(도시 안됨)을 순차적으로 형성하고, 마스크를 이용한 트렌치 식각(Trench Etch) 공정을 통해 상기 패드 질화막, 패드 산화막 및 반도체 기판(1)의 선택된 부분을 순차적으로 식각하여 트렌치(2)를 형성한다. 마스크를 제거한 후, 트렌치(2)의 양측벽에 희생 산화막을 형성하고, 상기 트렌치(2) 내에 소자 분리막(3)을 형성한다. 이때, 소자 분리막(3)은 일반적인 산화 공정(oxidation)에 의해 형성되거나 고밀도 플라즈마 화학 기상 증착법(HDP CVD)에 의해 형성된다. 덴시피케이션(densification)을 수행한 후, 소자 분리막(3)에 화학적 기계적 연마(CMP) 공정을 실시한다.A pad oxide film (not shown) and a pad nitride film (not shown) are sequentially formed on the semiconductor substrate 1, and the pad nitride film, the pad oxide film, and the semiconductor substrate 1 are formed through a trench etching process using a mask. The selected portions of are sequentially etched to form trenches 2. After removing the mask, a sacrificial oxide film is formed on both side walls of the trench 2, and the device isolation film 3 is formed in the trench 2. In this case, the device isolation layer 3 is formed by a general oxidation process (oxidation) or by a high density plasma chemical vapor deposition (HDP CVD). After performing densification, a chemical mechanical polishing (CMP) process is performed on the device isolation layer 3.
상기 소자 분리막(3)에 화학적 기계적 연마 공정을 실시한 후, HF 또는 BOE 세정 공정을 실시한다. 상기 패드 질화막을 제거한 후, HF 또는 BOE 세정 공정을 실시하여 상기 패드 산화막을 제거한다.After the chemical mechanical polishing process is performed on the device isolation film 3, an HF or BOE cleaning process is performed. After removing the pad nitride film, a HF or BOE cleaning process is performed to remove the pad oxide film.
상기에서, HF 또는 BOE 세정 공정으로 인하여, 소자 분리막(3)과 액티브 영역의 접점 부근에 산화막 리세스(oxide recess)로 인한 산화막 로스(loss)가 발생된다.In the above, due to the HF or BOE cleaning process, an oxide loss due to an oxide recess is generated near the contact of the device isolation layer 3 and the active region.
상술한 바와 같이, 종래의 트렌치 소자 분리막 형성 공정중에서 패드 질화막 제거 이후에 행해지는 습식 식각 공정에서 소자 분리막(3)은 등방성 식각이 되어 결국에는 도 1의 A 부분처럼, 소자 분리막(3)이 액티브 영역 보다 낮아지는 현상인 모우트(moat)라는 소자 분리막 리세스가 발생된다. 이런 액티브 영역의 모서리의 실리콘은 게이트 산화막(4) 형성 공정에서 게이트 산화막(4)이 얇게 형성되고, 워드라인 형성 공정에서 폴리실리콘 식각시 모우트에 폴리실리콘이 잔류하게 되어 소자의 단락을 유발시킬 수 도 있으며, 노출된 반도체 기판(1)의 모서리 부근에서의 전기장 집중에 의한 소자의 전기적 특성 열화를 초래할 수 있다.As described above, in the wet etching process performed after the pad nitride film is removed in the conventional trench device isolation layer forming process, the device isolation film 3 is isotropically etched, and as a result, as shown in part A of FIG. 1, the device isolation film 3 is active. A device isolation layer recess called moat, which is a phenomenon lower than the region, is generated. In the silicon of the corner of the active region, the gate oxide film 4 is thinly formed in the gate oxide film forming process, and polysilicon remains in the mote during polysilicon etching in the word line forming process, causing a short circuit of the device. In addition, it may cause the deterioration of the electrical characteristics of the device due to the concentration of the electric field near the edge of the exposed semiconductor substrate (1).
따라서, 본 발명의 목적은 상기한 문제점을 해결하기 위해 질화막 상에 부분 식각에 의한 산화막 패턴을 형성하고 이를 식각 마스크로 이용하여 트렌치를 형성하므로서 소자 분리막의 측면 식각 마진을 확보할 수 있어, 소자 분리막의 경계면이 기판의 액티브 영역 보다 밑으로 내려가는 현상을 방지하여 게이트 산화막 형성시에 게이트 산화막이 얇게 성장되는 현상을 방지할 수 있으며 전기장의 집중을 막을 수 있고, 워드 라인 형성 공정에서 폴리실리콘 식각시의 잔류물의 생성을 방지할 수 있는 반도체 소자의 소자 분리막 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to form an oxide film pattern by partial etching on the nitride film and to form a trench using the etching mask as an etching mask to solve the above problems, thereby securing the side etching margin of the device isolation layer, It is possible to prevent the gate oxide film from growing thinner when the gate oxide film is formed by preventing the boundary surface of the substrate from being lower than the active area of the substrate, and to prevent concentration of the electric field. It is an object of the present invention to provide a method for forming an isolation layer of a semiconductor device capable of preventing the formation of residues.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법은 반도체 기판상에 패드 산화막, 질화막 및 산화막을 순차적으로 형성하는 단계와; 상기 산화막 및 질화막의 일부를 패턴화하는 단계와; 상기 패턴화된 산화막의 측벽을 일부 식각하는 단계와; 상기 측벽 일부가 식각된 패턴화된 산화막을 식각 마스크로 이용하여 상기 반도체 기판을 식각하여 트렌치를 형성하고, 동시에 상기 질화막의 노출된 일부가 식각되는 단계와; 상기 트렌치 내부에 열 산화막을 형성한 후, 상기 트렌치를 포함하는 전체 구조상에 절연물을 형성하는 단계와; 상기 질화막이 노출되도록 상기 절연물을 연마한 후, 상기 절연물의 일부를 식각하는 단계와; 상기 질화막을 제거한 후 산화 공정을 통해 소자 분리막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.A device isolation film forming method of a semiconductor device according to the present invention for achieving the above object comprises the steps of sequentially forming a pad oxide film, a nitride film and an oxide film on a semiconductor substrate; Patterning a portion of the oxide film and the nitride film; Partially etching sidewalls of the patterned oxide film; Etching the semiconductor substrate using a patterned oxide film etched with a portion of the sidewalls as an etch mask to form a trench, and simultaneously etching a portion of the nitride film; Forming an insulator on the entire structure including the trench after forming a thermal oxide film inside the trench; Polishing the insulator so that the nitride film is exposed, and then etching a portion of the insulator; And removing the nitride film to form an isolation layer through an oxidation process.
도 1은 종래의 소자 분리막 형성 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a conventional method of forming a device isolation film.
도 2(a) 내지 도 2(f)는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 순차적으로 설명하기 위해 도시된 단면도.2 (a) to 2 (f) are cross-sectional views sequentially illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
1 및 11 : 반도체 기판 2 및 16 : 트렌치1 and 11: semiconductor substrate 2 and 16: trench
3 및 19 : 소자 분리막 4 및 20 : 게이트 산화막3 and 19: device isolation film 4 and 20: gate oxide film
12 : 패드 산화막 13 : 질화막12 pad oxide film 13 nitride film
14 : 산화막 15 : 마스크층14 oxide film 15 mask layer
17 : 열 산화막 18 : 절연물17 thermal oxide film 18 insulator
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 도 2(f)는 본 발명에 따른 반도체 소자의 소자 분리막 형성 방법을 순차적으로 설명하기 위해 도시된 단면도이다.2 (a) to 2 (f) are cross-sectional views sequentially illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.
도 2(a)를 참조하여 설명하면, 반도체 기판(11)상에 패드 산화막(12), 질화막(13) 및 산화막(14)을 순차적으로 형성한다. 상기 산화막(14)상의 선택된 영역에 포토레지스트를 이용한 마스크층(15)을 형성한 후, 상기 마스크층(15)을 이용한 식각 공정을 통해 상기 산화막(14) 및 질화막(13)을 순차적으로 식각한다. 이때, 상기 질화막(13)은 소정의 두께가 잔류된다.Referring to FIG. 2A, the pad oxide film 12, the nitride film 13, and the oxide film 14 are sequentially formed on the semiconductor substrate 11. After the mask layer 15 using the photoresist is formed in the selected region on the oxide layer 14, the oxide layer 14 and the nitride layer 13 are sequentially etched through an etching process using the mask layer 15. . At this time, the nitride film 13 has a predetermined thickness.
상기 패드 산화막(14)은 50 내지 200 Å의 두께로 형성되고, 상기 질화막(13) 및 산화막(14)은 1000 내지 3000 Å의 두께로 형성된다.The pad oxide film 14 is formed to a thickness of 50 to 200 kPa, and the nitride film 13 and the oxide film 14 is formed to a thickness of 1000 to 3000 kPa.
도 2(b)를 참조하여 설명하면, 상기 전체 구조상에 산화막 식각 용액을 사용한 식각 공정을 통해 산화막 패턴(14)의 노출된 측면의 일부를 식각한다.Referring to FIG. 2B, a portion of the exposed side surface of the oxide layer pattern 14 is etched through an etching process using an oxide layer etching solution on the entire structure.
상기 산화막 패턴(14)의 측면 일부를 식각하기 위해, HF 또는 BOE 용액을 사용하며, 100 내지 300 Å 정도 식각한다.In order to etch a part of the side surface of the oxide layer pattern 14, an HF or BOE solution is used, and 100 to 300 mm 3 is etched.
도 2(c)를 참조하여 설명하면, 상기 마스크층(15)을 제거한 후 상기 일부가 식각된 산화막 패턴(14)을 식각 마스크로 이용한 식각 공정을 통해 상기 반도체 기판(11)을 식각하여 트렌치(16)를 형성한다. 이때, 상기 일부가 식각된 산화막 패턴(14)과 노출된 질화막(13)이 식각되는데, 질화막의 일부 식각으로 인해 후속 공정에서 소자 분리막의 측면 식각 마진을 확보할 수 있게 된다.Referring to FIG. 2C, after the mask layer 15 is removed, the semiconductor substrate 11 is etched through an etching process using the oxide layer pattern 14 etched partially as an etching mask to form a trench ( 16). At this time, the oxide layer pattern 14 and the nitride layer 13 exposed are partially etched, so that the side etching margin of the device isolation layer can be secured in a subsequent process due to the etching of the nitride layer.
상기 식각 공정은 건식 식각일 경우 비등방성 식각이므로 수직으로만 식각되고, 트렌치(16)의 깊이는 식각 선택비로서 조절할 수 있는데, 상기 트렌치(16)는 1500 내지 4000 Å의 깊이로 형성된다.Since the etching process is anisotropic etching in the case of dry etching, only the vertical etching is performed, and the depth of the trench 16 can be adjusted as an etching selectivity, and the trench 16 is formed to a depth of 1500 to 4000 mm 3.
도 2(d)를 참조하여 설명하면, 열 산화 공정을 통해 상기 트렌치(16) 내부에 희생 산화막(도시 안됨)을 형성한 후, 습식 식각 공정을 통해 희생 산화막을 제거한다. 이후, 열 산화 공정을 통해 상기 트렌치(16) 내부에 열 산화막(17)을 형성한 후, 산화막 증착 방법을 통해 상기 트렌치(16)를 포함하는 전체 구조상에 절연물(18)을 형성한다.Referring to FIG. 2 (d), after the sacrificial oxide film (not shown) is formed in the trench 16 through the thermal oxidation process, the sacrificial oxide film is removed through the wet etching process. Thereafter, the thermal oxide film 17 is formed inside the trench 16 through a thermal oxidation process, and then an insulator 18 is formed on the entire structure including the trench 16 through an oxide film deposition method.
상기 희생 산화막은 50 내지 200 Å의 두께로 형성되고, 상기 열 산화막(17)은 건식 또는 습식 산화 방법을 사용하여 50 내지 200 Å의 두께로 형성된다.The sacrificial oxide film is formed to a thickness of 50 to 200 kPa, and the thermal oxide film 17 is formed to a thickness of 50 to 200 kPa using a dry or wet oxidation method.
도 2(e)를 참조하여 설명하면, 화학적 기계적 연마(CMP) 공정을 통해 질화막(12)이 노출되도록 상기 절연물(18)을 연마한다. 이후, 소자 분리막의 높이를 조절하기 위해 습식 식각 공정을 통해 상기 절연물(18)을 식각한다.Referring to FIG. 2E, the insulator 18 is polished to expose the nitride film 12 through a chemical mechanical polishing (CMP) process. Thereafter, the insulator 18 is etched through a wet etching process to adjust the height of the device isolation layer.
상기 절연물(18)은 고밀도 플라즈마 화학 기상 증착 방법 또는 오존 티오스 화학 기상 증착 방법을 사용하여 형성된다. 소자 분리막의 높이 조절을 위한 습식 식각 공정은 산화물 식각 용액에서 산화물이 200 내지 500 Å 정도가 식각되도록 한다.The insulator 18 is formed using a high density plasma chemical vapor deposition method or an ozone thiose chemical vapor deposition method. The wet etching process for adjusting the height of the device separator allows the oxide to be etched in an amount of about 200 to 500 kPa in the oxide etching solution.
도 2(f)를 참조하여 설명하면, 상기 질화막(12)을 제거한 후 산화 공정을 실시하여 소자 분리막(19)을 형성하고, 게이트 산화 공정을 통해 게이트 산화막(20)을 형성한다.Referring to FIG. 2 (f), after removing the nitride film 12, an oxidation process is performed to form an isolation layer 19, and a gate oxide film 20 is formed through a gate oxidation process.
상술한 바와 같이, 본 발명에 의하면 게이트 산화 공정시에 종래의 발명에서 발생되는 모우트에 산화막이 성장되는 것을 방지할 수 있고, 모우트로 인하여 소자 분리막 모서리 부근에서의 전기장 집중을 방지하여 전기적 특성 열화를 방지할 수 있으며, 워드라인 형성 공정에서 게이트용 폴리실리콘층의 식각시에 잔류물 발생을 방지할 수 있다.As described above, according to the present invention, the oxide film can be prevented from growing in the moat generated in the conventional invention during the gate oxidation process, and the electric property is deteriorated by preventing the electric field concentration near the edge of the device isolation layer due to the moat. It is possible to prevent the occurrence of residues during the etching of the gate polysilicon layer in the word line forming process.
Claims (7)
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| KR1019980061388A KR20000044885A (en) | 1998-12-30 | 1998-12-30 | Method for forming isolation film of semiconductor device |
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| KR1019980061388A KR20000044885A (en) | 1998-12-30 | 1998-12-30 | Method for forming isolation film of semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100541707B1 (en) * | 2002-12-09 | 2006-01-11 | 매그나칩 반도체 유한회사 | Device Separating Method of Semiconductor Device |
| KR100674647B1 (en) * | 2002-03-05 | 2007-01-25 | 매그나칩 반도체 유한회사 | Manufacturing method of high voltage semiconductor device |
| KR100756774B1 (en) * | 2001-06-22 | 2007-09-07 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| KR100779398B1 (en) * | 2001-06-26 | 2007-11-23 | 매그나칩 반도체 유한회사 | Device Separator Formation Method of Semiconductor Device |
| KR100939161B1 (en) * | 2003-02-17 | 2010-01-28 | 주식회사 하이닉스반도체 | Device Separation Method of Semiconductor Device |
| KR20230049254A (en) * | 2021-10-06 | 2023-04-13 | 주식회사 테스 | Method of processing substrate |
-
1998
- 1998-12-30 KR KR1019980061388A patent/KR20000044885A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100756774B1 (en) * | 2001-06-22 | 2007-09-07 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| KR100779398B1 (en) * | 2001-06-26 | 2007-11-23 | 매그나칩 반도체 유한회사 | Device Separator Formation Method of Semiconductor Device |
| KR100674647B1 (en) * | 2002-03-05 | 2007-01-25 | 매그나칩 반도체 유한회사 | Manufacturing method of high voltage semiconductor device |
| KR100541707B1 (en) * | 2002-12-09 | 2006-01-11 | 매그나칩 반도체 유한회사 | Device Separating Method of Semiconductor Device |
| KR100939161B1 (en) * | 2003-02-17 | 2010-01-28 | 주식회사 하이닉스반도체 | Device Separation Method of Semiconductor Device |
| KR20230049254A (en) * | 2021-10-06 | 2023-04-13 | 주식회사 테스 | Method of processing substrate |
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