KR20000044893A - Fabrication method of capacitor for semiconductor device - Google Patents
Fabrication method of capacitor for semiconductor device Download PDFInfo
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- KR20000044893A KR20000044893A KR1019980061396A KR19980061396A KR20000044893A KR 20000044893 A KR20000044893 A KR 20000044893A KR 1019980061396 A KR1019980061396 A KR 1019980061396A KR 19980061396 A KR19980061396 A KR 19980061396A KR 20000044893 A KR20000044893 A KR 20000044893A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/694—Electrodes comprising noble metals or noble metal oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
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Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조 방법에 관한 것으로, 특히 백금(Pt)을 사용한 캐패시터의 하부 전극 형성시 듀얼 다마신(dual damascene) 공법을 적용하므로써, 백금층을 패터닝하기 위한 건식 식각의 어려움을 해결할 수 있어, 백금을 사용하는 캐패시터 하부 전극 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and in particular, by applying a dual damascene method when forming a lower electrode of a capacitor using platinum (Pt), solving the difficulty of dry etching for patterning the platinum layer. The present invention relates to a method for manufacturing a capacitor of a semiconductor device capable of improving the stability and yield of the device, as well as securing the stability of the capacitor lower electrode forming process using platinum.
일반적으로, 반도체 소자가 고집적화, 소형화 및 고속화되어 감에 따라 캐패시터가 차지하는 면적 또한 줄어들게 된다. 반도체 소자가 고집적화 및 소형화되더라도 반도체 소자를 구동시키기 위한 캐패시터의 정전 용량은 최소한 확보되어야 한다. 캐패시터의 정전 용량은 확보하기 위한 한 방안으로 캐패시터 하부 전극을 실린더 구조, 스택 구조, 벨로우즈 구조, 핀 구조 등 다양한 구조로 형성하여 제한된 면적 하에서 캐패시터 하부 전극의 유효 표면적을 극대화시키고 있다. 캐패시터의 정전 용량을 확보하기 위한 다른 방안으로 캐패시터 유전체막으로 BST, Ta2O5등과 같은 고유전체를 적용하고 있다. BST, Ta2O5등과 같은 고유전체를 적용할 경우 전기적 특성 측면에서 백금이 유리하여 많이 검토되고 있다.In general, as semiconductor devices become more integrated, smaller, and faster, the area occupied by the capacitor is also reduced. Even if the semiconductor device is highly integrated and miniaturized, the capacitance of the capacitor for driving the semiconductor device should be at least secured. In order to secure the capacitance of the capacitor, the capacitor lower electrode is formed into various structures such as a cylinder structure, a stack structure, a bellows structure, and a fin structure to maximize the effective surface area of the capacitor lower electrode under a limited area. In order to secure the capacitance of the capacitor, a high dielectric material such as BST and Ta 2 O 5 is used as the capacitor dielectric layer. When high dielectric constants such as BST and Ta 2 O 5 are applied, platinum is advantageous in terms of electrical properties, and many studies have been conducted.
도 1은 백금(Pt)을 사용하여 캐패시터 하부 전극을 형성한 단면도이다.1 is a cross-sectional view of a capacitor lower electrode formed using platinum Pt.
반도체 소자를 구성하기 위한 여러 요소가 형성된 반도체 기판(11) 상에 층간 절연막(12)을 형성한다. 층간 절연막(12)의 일부분을 식각 하여 반도체 기판(11)이 노출되는 콘택홀(13)을 형성하고, 콘택홀(13) 내부에 도프트 실리콘(doped silicon)과 같은 전도성 물질로 캐패시터 콘택 플러그(14)를 형성한다. 콘택 플러그(14)를 포함한 층간 절연막(12) 상에 백금을 두껍게 증착한 후 식각 공정을 통해 백금으로 된 캐패시터 하부 전극(15)을 형성한다. 이후, 캐패시터 유전체막 및 캐패시터 상부 전극을 형성한다.An interlayer insulating film 12 is formed on a semiconductor substrate 11 on which various elements for forming a semiconductor element are formed. A portion of the interlayer insulating layer 12 is etched to form a contact hole 13 through which the semiconductor substrate 11 is exposed, and a capacitor contact plug made of a conductive material such as doped silicon in the contact hole 13. 14). A thick platinum is deposited on the interlayer insulating layer 12 including the contact plug 14, and then the capacitor lower electrode 15 made of platinum is formed through an etching process. A capacitor dielectric film and a capacitor upper electrode are then formed.
상기에서, 캐패시터 하부 전극(15)을 형성하기 위한 식각 공정은 비등방성(anisotropic)의 방향성을 갖는 건식 식각을 주로 사용하는데, 백금은 건식 식각이 어려워 그 두께가 두꺼울 경우 패턴 형성이 거의 불가능하고, 식각 되더라도 도 1에 도시된 바와 같이, 이상적인 패턴(점선 부분)으로 식각 되지 않고 경사지게 식각이 되어 캐패시터 하부 전극(15)의 유효 표면적이 줄어드는 등의 문제가 있다.In the above, an etching process for forming the capacitor lower electrode 15 mainly uses dry etching having an anisotropic directionality, platinum is difficult to dry etching because the dry etching is difficult, it is almost impossible to form a pattern, Even if it is etched, as shown in FIG. 1, there is a problem that the effective surface area of the capacitor lower electrode 15 is reduced by being etched obliquely rather than by etching into an ideal pattern (dotted line).
따라서, 본 발명은 백금(Pt)을 사용한 캐패시터의 하부 전극 형성시 듀얼 다마신(dual damascene) 공법을 적용하므로써, 백금층을 패터닝하기 위한 건식 식각의 어려움을 해결할 수 있어, 백금을 사용하는 캐패시터 하부 전극 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있는 반도체 소자의 캐패시터 제조 방법을 제공함에 그 목적이 있다.Therefore, the present invention can solve the difficulty of dry etching for patterning the platinum layer by applying the dual damascene method when forming the lower electrode of the capacitor using platinum (Pt), the lower portion of the capacitor using platinum It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device capable of improving the reliability and yield of the device as well as securing stability of the electrode forming process.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 캐패시터 제조 방법은 반도체 기판 상에 콘택홀을 갖는 제 1 절연막을 형성하는 단계; 상기 콘택홀 내부에 전도성 물질로 캐패시터 콘택 플러그를 형성하는 단계; 상기 캐패시터 콘택 플러그를 포함한 제 1 절연막 상에 제 2 절연막을 형성한 후, 상기 제 2 절연막의 일부분을 식각 하여 상기 캐패시터 콘택 플러그가 노출되는 캐패시터 하부 전극용 홀을 형성하는 단계; 상기 캐패시터 하부 전극용 홀이 매립되도록 백금층을 형성한 후, 화학 기계적 연마 공정으로 상기 홀 내에 백금층을 남기는 단계; 상기 제 2 절연막을 제거하여 상기 백금층으로 된 캐패시터 하부 전극을 형성하는 단계; 및 상기 캐패시터 하부 전극 상에 캐패시터 유전체막 및 캐패시터 상부 전극을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.A method of manufacturing a capacitor of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a first insulating film having a contact hole on a semiconductor substrate; Forming a capacitor contact plug with a conductive material in the contact hole; Forming a second insulating film on the first insulating film including the capacitor contact plug, and then etching a portion of the second insulating film to form a hole for a capacitor lower electrode through which the capacitor contact plug is exposed; Forming a platinum layer to bury the capacitor lower electrode hole, and then leaving a platinum layer in the hole by a chemical mechanical polishing process; Removing the second insulating film to form a capacitor lower electrode formed of the platinum layer; And forming a capacitor dielectric layer and a capacitor upper electrode on the capacitor lower electrode.
도 1은 종래 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.1 is a cross-sectional view of a device for explaining a capacitor manufacturing method of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of devices for explaining a method of manufacturing a capacitor of a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 층간 절연막11: semiconductor substrate 12: interlayer insulating film
13: 콘택홀 14: 캐패시터 콘택 플러그13: contact hole 14: capacitor contact plug
15: 캐패시터 하부 전극 21: 반도체 기판15: capacitor lower electrode 21: semiconductor substrate
22: 제 1 절연막 23: 식각 정지막22: first insulating film 23: etch stop film
24: 콘택홀 25: 캐패시터 콘택 플러그24: contact hole 25: capacitor contact plug
26: 제 2 절연막 27: 캐패시터 하부 전극용 홀26: second insulating film 27: hole for capacitor lower electrode
28: 백금층 31: 캐패시터 유전체막28: platinum layer 31: capacitor dielectric film
32: 캐패시터 상부 전극 280: 캐패시터 하부 전극32: capacitor upper electrode 280: capacitor lower electrode
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 캐패시터 제조 방법을 설명하기 위한 소자의 단면도이다.2A to 2D are cross-sectional views of devices for describing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 소자를 구성하기 위한 여러 요소가 형성된 반도체 기판(21) 상에 제 1 절연막(22)을 형성하고, 제 1 절연막(22) 상에 식각 정지막(23)을 형성한다. 포토리소그라피(photolithography) 공정 및 식각 공정으로 식각 정지막(23) 및 제 1 절연막(22)의 일부분을 순차적으로 식각 하여 반도체 기판(21)이 노출되는 콘택홀(24)을 형성한 후, 콘택홀(24) 내부에 전도성 물질로 캐패시터 콘택 플러그(25)를 형성한다.Referring to FIG. 2A, a first insulating layer 22 is formed on a semiconductor substrate 21 on which various elements for forming a semiconductor element are formed, and an etch stop layer 23 is formed on the first insulating layer 22. . A portion of the etch stop layer 23 and the first insulating layer 22 are sequentially etched through a photolithography process and an etching process to form a contact hole 24 through which the semiconductor substrate 21 is exposed, and then a contact hole. The capacitor contact plug 25 is formed of a conductive material therein.
상기에서, 제 1 절연막(22)은 언도프트 산화물(undoped oxide)이나 도프트 산화물(doped oxide)을 사용하여 1000 내지 3000Å의 두께로 증착하여 형성된다. 식각 정지막(23)은 질화물(nitride)을 사용하여 100 내지 300Å의 두께로 증착하여 형성된다. 캐패시터 콘택 플러그(25)는 도프트 실리콘(doped silicon)과 같은 전도성 물질이나 고융점 금속 물질을 사용하여 형성된다.In the above description, the first insulating layer 22 is formed by depositing a thickness of 1000 to 3000 GPa using an undoped oxide or a doped oxide. The etch stop layer 23 is formed by depositing a thickness of 100 to 300 Å using nitride. The capacitor contact plug 25 is formed using a conductive material such as doped silicon or a high melting point metal material.
도 2b를 참조하면, 캐패시터 콘택 플러그(25)를 포함한 식각 정지막(23) 상에 제 2 절연막(26)을 형성한 후, 포토리소그라피 공정 및 식각 공정으로 제 2 절연막(26)의 일부분을 식각 하여 캐패시터 콘택 플러그(25)가 노출되는 캐패시터 하부 전극용 홀(27)을 형성한다.Referring to FIG. 2B, after forming the second insulating layer 26 on the etch stop layer 23 including the capacitor contact plug 25, a portion of the second insulating layer 26 is etched by a photolithography process and an etching process. As a result, the capacitor lower electrode hole 27 through which the capacitor contact plug 25 is exposed is formed.
상기에서, 제 2 절연막(26)은 식각 정지막(23)과 습식 식각 선택비가 높은 물질 예를 들어, 산화물을 증착하여 형성되며, 증착 두께는 후에 형성될 캐패시터 하부 전극의 높이를 고려하여 결정한다. 한편, 상기에서 식각 정지막(23)을 형성하지 않을 경우에 제 2 절연막(26)은 제 1 절연막(22)과 습식 식각 선택비가 높은 물질을 사용하여 형성하여야 한다.In the above, the second insulating layer 26 is formed by depositing an etch stop layer 23 and a material having a high wet etching selectivity, for example, an oxide, and the deposition thickness is determined in consideration of the height of the capacitor lower electrode to be formed later. . In the case where the etch stop layer 23 is not formed, the second insulating layer 26 should be formed using a material having a high wet etching selectivity with the first insulating layer 22.
도 2c를 참조하면, 캐패시터 하부 전극용 홀(27)이 충분히 매립되도록 백금층(28)을 증착한 후, 제 2 절연막(26) 상부가 노출되도록 화학 기계적 연마(CMP) 공정으로 백금층(28)을 연마하여 캐패시터 하부 전극용 홀(27) 내에만 백금층(28)이 남도록 한다.Referring to FIG. 2C, after the platinum layer 28 is deposited to sufficiently fill the lower hole 27 for the capacitor lower electrode, the platinum layer 28 is subjected to a chemical mechanical polishing (CMP) process to expose the upper portion of the second insulating layer 26. ) Is ground so that the platinum layer 28 remains only in the capacitor lower electrode hole 27.
상기에서, 백금층(28)을 증착하기 전에 Ir, TiN 등의 다른 금속막을 증착하여 백금층의 열적, 기계적 성질을 향상시킬 수 있다.In the above, before depositing the platinum layer 28, another metal film such as Ir and TiN may be deposited to improve the thermal and mechanical properties of the platinum layer.
도 2d를 참조하면, 제 2 절연막(26)을 제거하여 백금층(28)으로 된 캐패시터 하부 전극(280)을 형성한다. 이후, 캐패시터 유전체막(31) 및 캐패시터 상부 전극(32)을 형성한다.Referring to FIG. 2D, the second insulating layer 26 is removed to form the capacitor lower electrode 280 made of the platinum layer 28. Thereafter, the capacitor dielectric film 31 and the capacitor upper electrode 32 are formed.
상기에서, 제 2 절연막(26)은 습식 식각으로 제거하되, 산화물로 형성될 경우 HF계 화학제(HF-base chemical) 또는 HF 증기(HF vapor)를 이용한 습식 식각 공정으로 제거한다. 제 2 절연막(26) 제거 후에 노출되는 식각 정지막(24)은 제거할 수도 있고 제거하지 않아도 된다. 캐패시터 유전체막(31)은 BST, Ta2O5등과 같은 고유전체를 사용하여 형성한다. 캐패시터 상부 전극(32)은 캐패시터 유전체막(31)에 따라 폴리실리콘이나 TiN, Pt 등과 같은 도전성 물질을 선택하여 형성한다.In the above, the second insulating layer 26 is removed by wet etching, and when formed of an oxide, is removed by a wet etching process using HF-based chemical or HF vapor. The etch stop film 24 exposed after the removal of the second insulating film 26 may or may not be removed. The capacitor dielectric film 31 is formed using a high dielectric material such as BST, Ta 2 O 5, or the like. The capacitor upper electrode 32 is formed by selecting a conductive material such as polysilicon, TiN, Pt, or the like according to the capacitor dielectric layer 31.
상술한 바와 같이, 본 발명은 백금(Pt)을 사용한 캐패시터 하부 전극 형성시 듀얼 다마신(dual damascene) 공법을 적용하므로 양호한 형상(profile)의 패턴을 얻을 수 있고, 캐패시터 하부 전극으로 백금을 사용함에 따라 고유전체의 사용을 가능하게 하고, 제 2 절연막에 의해 백금층의 두께를 임의로 조절 가능하여 적용하는 소자에 따라 적절히 백금층의 두께를 조절하여 캐패시터 하부 전극의 표면적을 조절할 수 있다. 따라서, 백금을 사용하는 캐패시터 하부 전극 형성 공정의 안정성 확보와 더불어 소자의 신뢰성 및 수율을 향상시킬 수 있다.As described above, the present invention applies a dual damascene method when forming a capacitor lower electrode using platinum (Pt), thereby obtaining a pattern of a good profile, and using platinum as the capacitor lower electrode. Accordingly, it is possible to use a high dielectric constant, and the thickness of the platinum layer can be arbitrarily adjusted by the second insulating film, so that the surface area of the capacitor lower electrode can be adjusted by appropriately adjusting the thickness of the platinum layer according to the device to be applied. Therefore, the stability and yield of the device can be improved while securing the stability of the capacitor lower electrode forming process using platinum.
Claims (11)
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| KR1019980061396A KR20000044893A (en) | 1998-12-30 | 1998-12-30 | Fabrication method of capacitor for semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100414227B1 (en) * | 2001-06-30 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
| KR100824136B1 (en) * | 2001-06-28 | 2008-04-21 | 주식회사 하이닉스반도체 | Capacitor manufacturing method of semiconductor device |
| KR100849078B1 (en) * | 2002-06-21 | 2008-07-30 | 매그나칩 반도체 유한회사 | Method for forming metal insalator metal capacitor of semiconductor device |
-
1998
- 1998-12-30 KR KR1019980061396A patent/KR20000044893A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100824136B1 (en) * | 2001-06-28 | 2008-04-21 | 주식회사 하이닉스반도체 | Capacitor manufacturing method of semiconductor device |
| KR100414227B1 (en) * | 2001-06-30 | 2004-01-07 | 주식회사 하이닉스반도체 | Method for fabricating capacitor |
| KR100849078B1 (en) * | 2002-06-21 | 2008-07-30 | 매그나칩 반도체 유한회사 | Method for forming metal insalator metal capacitor of semiconductor device |
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