KR200150080Y1 - Semiconductor memory device - Google Patents

Abstract

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device adapted to high integration requirements.

The present invention has a semiconductor memory device comprising a semiconductor substrate, an active region arranged in one direction on the semiconductor substrate, a ground region arranged in the semiconductor substrate in a direction perpendicular to the active region, and on the semiconductor substrate on both sides of the ground region. And word lines formed in a direction parallel to the ground region, and active regions on both sides of the word line and impurity regions formed in the ground region.

According to this design, the grounding region is deeply formed in the semiconductor substrate, and the degree of needle integration is good.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device adapted to high integration requirements.

Current computer systems use almost all of SRAM or DRAM, which can be electrically read / write, as cache memory and main memory, but since they are volatile memory, they lose their stored data when they are turned off. have.

Therefore, current computer systems have separate external storage devices composed of nonvolatile memory capable of continuously storing data even when the power is cut off.

That is, a memory device may be classified into a volatile memory device capable of erasing large stored information and storing new information again, and a nonvolatile memory device in which information stored once is permanently preserved.

As a volatile memory device, there is a random access memory (RAM) capable of writing and reading information, and a read only memory (ROM), erasable programmable ROM (EPROM), and electrically erasable programmable ROM as a nonvolatile memory device. There is).

Among the nonvolatile memory devices, ROM is a device that cannot be reprogrammed once information is stored, and EPROM and EEPROM are devices that can be stored by erasing and reprogramming the stored information.

EPROM and EEPROM have the same operation of programming information, only the method of erasing stored information is different.

In other words, the EPROM erases the information stored in ultraviolet light and the EEPROM erases the information stored electrically, and the basic structure and operation are the same.

Hereinafter, the EPROM will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a general EPROM cell.

In FIG. 1, a general EPROM cell is formed by sequentially stacking a tunneling insulating film 12, a floating gate 13, an insulating film 14, and a control gate 15 on a predetermined portion on a semiconductor substrate 11. 13) First and second hard furnace n-type impurity regions 16 and 17 are formed in the semiconductor substrate 11 on both sides.

Accordingly, the channel region 18 is formed between the first and second hard furnace n-type impurity regions 16 and 17 of FIG.

The tunneling insulating film 12 is formed thinner than the insulating film 14 between the control gate 15 and the floating gate 13.

This general EPROM write operation is as follows.

In order to write data in one cell, a voltage of 7 to 0 V is applied to the second high furnace n-type impurity region 17, a voltage pulse of 12 to 13 V is applied to the control gate 15, and the first hard furnace n is applied. The type impurity region 16 and the semiconductor substrate 11 are grounded.

As a result, high energy is generated at the PN junction between the second hard furnace furnace n-type impurity region 17 and the semiconductor substrate 11, resulting in a breakdown situation, whereby hot electrons are generated. .

Some of the generated hot electrons obtain an energy larger than the energy barrier height (about 3.2 V) between the semiconductor substrate 11 and the tunneling insulating film 12 so that the hot electrons tunnel through the tunneling insulating film 12 to the floating gate 13. It is stored there.

This method is called Channel Hot Electron Injection.

As described above, the data written in one cell is deleted.

It can be erased by tightening ultraviolet light, which generates a photocurrent from the floating gate to the semiconductor substrate to remove stored data.

The erase process requires 10-30 minutes of UV exposure and erases all cells at the same time.

The conventional structure of the EPROM storing data as described above is as follows.

2 is a layout diagram of an EPROM according to the prior art.

In FIG. 2, a plurality of active regions 22 are formed on a semiconductor substrate (not shown in the drawing), which are divided into a field region and an active region at regular intervals and in one direction.

The ground region 23 is formed in a direction perpendicular to the active region 22.

The word line 24 is formed on the semiconductor substrate formed at regular intervals on both sides of the ground region 23 so as to be perpendicular to and parallel to the ground region.

Impurity regions (not shown) are formed in the active region 22 and the ground region 23 on both sides of the word line 24.

Bit line contact holes 25 are formed in the active region 22 on one side of the word line 24 opposite to the ground region 23.

Subsequently, a field oxide film is formed in portions except the active region 22 and the ground region 23.

A portion of the word line 24 at the intersection of the word line 24 and the active region 22 is called a control gate (not shown).

A floating gate (not shown) is formed between the control gate and the semiconductor substrate.

3 is a cross-sectional view taken along the line X-X 'of FIG.

In FIG. 3, the cross-sectional configuration along the line X-X 'is formed by sequentially forming the tunneling insulating film 26, the floating gate 27, the second insulating film 28, and the control gate 24a on the semiconductor substrate 21. An impurity region 31 is formed in the semiconductor substrate 21 on both sides of the gate 27.

The ground region 23 is formed in the middle of the impurity region 31.

4 is a cross-sectional view taken along the line Y-Y 'of FIG.

As shown in FIG. 4, in the cross-sectional structure of the line Y-Y ', the field oxide film 30 is grown on a predetermined portion of the surface of the semiconductor substrate 21, and the word line 24 is formed on the predetermined portion on the field oxide film 30. As shown in FIG. Is formed, and a ground region 23 is formed in the semiconductor substrate between the field oxide films 30.

5 is a circuit diagram of a general NOR type EPROM.

As shown in FIG. 5, a general NOR type EPROM includes a plurality of bit lines 31, a plurality of word lines 24 perpendicular to the plurality of bit lines 31, and the plurality of word lines. (24) A plurality of EPROM cells 32 are formed at regular intervals under the line.

Parallel to the plurality of EPROM cells 32, a plurality of first ground regions 23a are formed in each of the two EPROM cells 32, perpendicular to the plurality of word lines 24, and the plurality of first ground regions ( 23a) One second grounding region 23b is formed at one end of one side.

In the conventional EPROM cell unit, since the ground region is located at the upper portion of the substrate, the gate electrode is affected. Thus, the active region connected to the ground region is lengthened by the gap between the ground region and the gate electrode. Therefore, the distance between the gate electrode and the gate electrode.

Therefore, in case of NOR type (Not OR Type), there is a ground area for every two EPROM cells in case of NAND type (Not And Type), so the area occupied by the area of the cell increases, which is bad for the density. There is a problem that affects.

1 is a cross-sectional view of a typical EPROM cell.

2 is a layout diagram of an EPROM according to the prior art.

3 is a cross-sectional view taken along the line X-X 'of FIG.

4 is a cross-sectional view taken along the line Y-Y 'of FIG.

5 is a circuit diagram of a general NOR type.

6 is a layout diagram of the EPROM according to the present invention

7 is a cross-sectional view taken along the line X-X 'of FIG.

8 is a cross-sectional view taken along the line Y-Y 'of FIG.

9 is a cross-sectional view taken along line AA ′ of FIG. 6.

* Explanation of symbols for main parts of the drawings

41 semiconductor substrate 42 active region

43: ground area 44: word line

44a: Control Site 47: Floating Gate

51 impurity region 53 field oxide film

The present invention provides a semiconductor substrate, an active region arranged in one direction on the semiconductor substrate, a ground region arranged on the semiconductor substrate in a direction perpendicular to the active region, and the ground on the semiconductor substrate on both sides of the ground region. A semiconductor memory device comprising word lines formed in a direction parallel to a region, and impurity regions formed in active regions on both sides of the word line and a ground region.

6 is a layout diagram of an EPROM according to the present invention.

As shown in FIG. 6, a plurality of active regions 42 are formed in one direction by dividing into a field region and an active region on a semiconductor substrate (not shown), and perpendicular to the plurality of active regions 42. The ground region 43 is formed in a direction, and word lines 44 are formed at both sides of the ground region 43 so as to be perpendicular to the plurality of active regions 42 and parallel to the ground region 43.

An impurity region (not shown) is formed in the active region 42 and the ground region 43 on both sides of the word line 44, and on one side of the word line 44 opposite to the ground region 43. A plurality of bit-tlang contact holes 45 are formed in the plurality of active regions 42 to form the EPROM of the present invention.

7 is a cross-sectional view taken along the line X-X 'of FIG.

In Fig. 7, the tunneling insulating film 46, the boring gate 47, the second insulating film 48, and the control gate 44a are sequentially formed on the semiconductor substrate 41 in the cross-sectional configuration along the X-X 'line.

An impurity region 51 is formed in the semiconductor substrate 41 on both sides of the floating gate 47.

A ground region 43 is formed under the impurity region 51, and the ground region 43 is deeply formed in the substrate, and the impurity region on the ground region 43, that is, connected to the ground region 43, is different. Ions are implanted with higher energy than impurity regions and are deeply formed in the semiconductor substrate 41.

FIG. 8 is a cross-sectional view taken along the line Y-Y 'of FIG.

As shown in FIG. 8, in the cross-sectional configuration of the line Y-Y ', a plurality of impurity regions 51 are formed in the semiconductor substrate 41, and a plurality of impurity regions 51 under the plurality of impurity regions 51 are formed. The ground region 43 is connected to the ground.

9 is a cross-sectional view taken along line AA ′ of FIG. 6.

As shown in FIG. 9, in the cross-sectional structure along the line A-A ', the field oxide film 53 is grown on a predetermined portion of the surface of the semiconductor substrate 41, and the word line 44 is formed on the predetermined portion on the field oxide film 53. As shown in FIG. The ground region 43 is deeply formed in the semiconductor substrate between the field oxide films 53.

In the semiconductor memory device of the present invention, since the active area is shortened by forming a deeply grounded area in the semiconductor substrate, the area of the NOR type is reduced by 20% and the NAND type by 70%. It has a big effect on savings.

Claims (2)

Semiconductor substrates; Active regions arranged in one direction on the semiconductor substrate, a ground region arranged in the semiconductor substrate in a direction perpendicular to the active region, and word lines formed in a direction parallel to the ground region on semiconductor substrates on both sides of the ground region; And an impurity region formed in the active region and the ground region on both sides of the word line. The semiconductor memory device of claim 1, wherein the impurity region is formed thin in the active region and deep in the ground region.