KR20020059343A - High-efficiency modulating RF amplifier - Google Patents

Abstract

The present invention provides high efficiency power control of high efficiency (e.g. hard-limiting or switch-mode) power amplifiers. The spread between the maximum frequency of the desired modulation and the operating frequency of the switch-mode DC-DC converter is reduced by placing the active linear regulator after the switch-mode converter. The linear regulator controls the operating voltage of the power amplifier with sufficient bandwidth to reproduce the desired amplitude modulated waveform. The linear regulator eliminates variations to its input voltage even while the output voltage is changing in response to the applied control signal. Amplitude modulation is achieved by changing the operating voltage for the power amplifier. High efficiency is enhanced by allowing the switch-mode DC-DC converter to change its output voltage so that the voltage drop across the linear regulator is low and remains at a relatively constant level.

Description

[0001] The present invention relates to a high-efficiency modulating RF amplifier,

Battery life is a major concern for wireless communication devices such as cellular telephones, pagers, wireless modems, and the like. In particular, wireless-frequency transmission consumes considerable power. The cause of this power consumption is inefficient power amplifier operation. A typical RF power amplifier for wireless communications operates with only about 10% efficiency. Obviously, low-cost technology for significantly boosting amplifier efficiency will meet the intense need.

Moreover, most modern digital wireless communication devices operate on a packet basis. That is, the transmitted information is transmitted in a series of one or more short bursts, the transmitter being active only during the burst time and not at all other times. It is therefore also desirable that control of burst activation and deactivation be controlled in an energy-efficient manner, and thus in a manner that contributes to extended battery life.

Power amplifiers are classified into different groups: Class A, Class B, Class AB, and so on. Different classes of power amplifiers usually exhibit different biasing conditions. In designing RF power amplifiers, there is usually a trade-off between linearity and efficiency. Different classes of amplifier operation provide designers with ways to balance these two parameters.

Generally, power amplifiers are divided into two different categories, linear and non-linear. Linear amplifiers (e.g., Class A amplifiers and Class B push-pull amplifiers) maintain high linearity because the output signal is linearly proportional to the input signal so that a reliable input signal at the output do. For non-linear amplifiers (e.g., single-ended Class B and Class C amplifiers), the output signal is not directly proportional to the input signal. The resulting amplitude distortion on the output signal makes these amplifiers most applicable to signals without any amplitude modulation, which is also known as constant-envelope signals.

The amplifier output efficiency is defined as the ratio between the RF output power and the input (DC) power. The main source of power amplifier inefficiency is the dissipated power in the transistor. Class A amplifiers are inefficient because current flows continuously through the device. Conventionally, efficiency is improved by trade-off linearity for increased efficiency. For example, in Class B amplifiers, the bias condition is chosen so that the output signal is cut off for half a cycle if the opposite half cycle is not provided by the second transistor (push-pull). As a result, the waveform will be less linear. The output waveform may still be sinusoidally formed using a tank circuit or other filter to filter out and remove the higher and lower frequency components.

Class C amplifiers are conducted for less than 50% of the cycles to further increase efficiency; That is, when the output current conduction angle is less than 180 degrees, the amplifier is referred to as class C. This mode of operation may have a higher efficiency than Class A or Class B, but it typically produces more distortion than Class A or Class B amplifiers. In the case of class C amplifiers, the output amplitude is still slightly changed when the input amplitude changes. This is because the Class C amplifier acts as a constant current source - although it is simply being warmed - and not a switch.

The amplifiers of the remaining classes use the transistor as a switch only, thereby strongly solving the power dissipation problem in the transistor. The basic principle of these amplifiers is that the switch ideally dissipates no power, because there is zero voltage across it or zero current passing through it. Therefore, since the V-I product of the switch is always zero, there is no dissipation in the device. Class E power amplifiers use a single transistor in contrast to Class D power amplifiers that use two transistors.

However, actually, the switches are not ideal. (The switches have turn-on / turn-off time and on-resistance.) The associated dissipation degrades efficiency. Therefore, the prior art has sought ways to change so-called " switch-mode " amplifiers so that the switch voltage becomes zero during non-zero time periods at approximately the moment of switching to reduce power dissipation The transistor is driven to operate as a switch at the operating frequency to minimize power dissipated while the current is conducting. The class E amplifier uses a reactance output network that reduces switching losses by providing a degree of freedom sufficient to form the switch voltage to have both a zero value and a zero slope at switch turn-on. Class F amplifiers are still an additional class of switch-mode amplifiers. Class F amplifiers usually produce a square output waveform that is more squared than a sine wave. The "squaring-up" of this output waveform facilitates the generation of odd-order harmonics (ie, x3, x5, x7, etc.) in the output network and the generation of even-order harmonics (ie x2, ).

An example of a known power amplifier for use in a cellular telephone is shown in FIG. For example, a GSM cellular telephone should be capable of outputting power in excess of the 30 dBm range. Moreover, the transmitter turn-on and turn-off profiles must be precisely controlled to prevent spurious emissions. The power is directly controlled by a digital signal processor (DSP) of the cellular telephone via a digital-analog converter (DAC). In the circuit of Figure 1, the signal GCTL drives the gate of an external AGC amplifier that controls the RF level of the power amplifier. A portion of the output is fed back through the directional coupler for closed loop operation. The amplifier of Fig. 1 is not a switch-mode amplifier. Rather, the amplifier is a Class AB amplifier that is driven to saturation at best, thus exhibiting relatively poor efficiency.

Figure 2 shows an example of a known class E power amplifier, as described in U.S. Patent 3,919,656. The RF input signal is connected to the driver stage 2 via a lead 1 and the driver stage controls the active device 5 via a signal connected via a lead 3. The active device 5 is a And substantially operates as a switch when properly driven by the driver 2. Therefore, the output port of the active device is represented as a single-pole single throw switch 6. Connected across the switch 6 is a series combination of the DC power supply 7 and the input port of the load network 9. The output port of the load network 9 is connected to the load 11. When the switch 6 is operated periodically at a desired AC output frequency, the DC energy from the power supply 7 is converted to AC energy at the switching frequency (and its harmonics).

U.S. Patent 3,900,823 to Sokal et al. Describes the feedback control of Class E power amplifiers. The need for feedback control indicates that the device action can not be fully characterized, which in turn represents a substantial departure from the operation of the device as a true switch. The buckle further describes a solution to the problem of feedthrough power control at low power levels by controlling the RF input drive amplitude through the application of negative feedback techniques to control the DC power supply of one or more preceding stages. The need for feedback control places constraints on feedback loop dynamics on the system.

The Class E amplifier configuration of Figure 2 suffers from the disadvantage that a large voltage swing occurs at the output of the active device due to ringing, although it can achieve theoretically high conversion efficiency. A large voltage swing, typically more than three times the power supply voltage, prevents the Class E circuit from being used with some active devices having a low breakdown voltage.

In order to operate the RF power amplifier in switch mode, it is necessary to repeatedly drive the output transistor (s) rapidly between shutdown and full-on, and then back off. The means for achieving this fast switching depends on the type of transistor selected to be used as the switch: For a field-effect transistor (FET), the control parameter is a gate-source voltage and the bipolar transistor bipolar transistor, BJT, HBT), the control parameter is a base-emitter current.

However, the driving circuit of the RF amplifier of Fig. 2 typically includes a matching network of tuning (resonance) circuits. Referring to FIG. 3, in this configuration, the RF input signal is typically coupled to a driver amplifier that operates in Class A. The output signal of the driver amplifier is connected to the control terminal of the switching transistor shown in FIG. 3 as an FET through the matching network. As with the design of the load network of Figure 2, the proper design of the matching network is not an easy problem.

Various designs have been attempted to improve on the different aspects of the base class E amplifier. One such design is described by Choi et al. In IEEE Transactions on Microwave Theory and Technologies, Vol. 47, No. 9, "Physically Based Analysis Model of FET Class-E Power Amplifiers - Design for Maximum PAE". This article models various non-idealities of the FET switch and conclusions are drawn on a class E amplifier design that is advantageous from this model. For the selected topology, a maximum power-added efficiency (PAE) of about 55% occurs at a power level of less than 0.5 watts. At higher power, PAE is dramatically reduced, for example less than 30% at 2W.

The PAE of the power amplifier is set by the amount of DC power required to achieve the last 26 dB of gain required to achieve the final output power. (At this gain level, the power input to the amplifier via the drive signal may be neglected - which is not easily sensitive to the measurement.) Currently, it is possible to generate output power of at least 1 W at radio frequencies, There are no known amplifiers that provide 26dB of power gain. Thus, one or more amplifiers must be provided in front of the final stage, and the DC power consumed by these amplifiers must be included in the determination of the overall PAE.

Conventional design implementations require the amplifier designer to impedance-match the driver output impedance to the input impedance of the final switching transistor. Therefore, the actual power output required from the driver stage is defined by the required voltage (or current) operating at the (usually low) effective input impedance of the switching element. Since the concept of impedance requires linear operation, the specific impedance to the input of the switching transistor can not be defined, and the switch is very nonlinear.

An example of an RF amplifier circuit based on the above approach is shown in FIG. An interstage " T section " consisting of an inductor L1, a shunt capacitor C and an inductor L2 is used to match the driver stage to the assumed 50 ohm load (i.e. the final stage) do.

This conventional implementation treats the interstage between the driver stage and the final stage as a linear network, which is not a linear network. Moreover, the conventional implementation maximizes the power transfer between the driver stage and the final stage (the intended result of impedance matching). Thus, for example, to generate the required drive voltage for the FET as the switching transistor, the driver also generates an in-phase current to provide the impedance-matched power.

Another example of a conventional RF power amplifier circuit is shown in Fig. The circuit uses " resonant interstage matching " in which the driver stage and the final stage are connected using a coupling capacitor (Ccpl).

As noted, conventional design implementations do not achieve high PAE at high output power (e.g., 2 W, the power level commonly encountered during the operation of a cellular telephone). Therefore, there is a need for an RF power amplifier that exhibits high PAE at relatively high output power.

Investigation of conventional patents

Control of the output power from the amplifier can be done as illustrated by Socal et al. And in the following U. S. patents: 4,392, 245; 4,992,753; 5,095,542; 5,193,223; 5,369,789; 5,410,272; 5,697,072 and 5,697,074, which are incorporated herein by reference in their entirety. Other references such as U.S. Pat. No. 5,276,912 teach the control of the amplifier output power by changing the amplifier load circuit.

A related problem is the generation of modulated signals such as, for example, amplitude modulated (AM) signals, quadrature amplitude modulated (QAM) signals, and the like. The known IQ modulation structure is shown in Fig. The data signal is applied to a quadrature modulation encoder that generates I and Q signals. The I and Q signals are applied to the quadrature modulator together with the carrier signal. The carrier signal is generated by a carrier generator to which a tuning signal is applied.

Typically, the output signal of the quadrature modulator is then applied to a variable attenuator controlled in accordance with the power control signal. In other examples, power control is implemented by changing the gain of the amplifier. This is achieved by adjusting the bias for the transistors in the linear amplifier, taking advantage of the effect that the transistor transconductance varies with the applied bias conditions. Because the amplifier gain is strongly related to the transistor transconductance, changing the transconductance actually changes the amplifier gain. The resulting signal is then amplified by a linear power amplifier and applied to the antenna.

In AM signals, the amplitude of the signal is substantially proportional to the amplitude of the information signal, such as voice. Information signals such as speech are not constant at all, and therefore the resulting AM signals always change in output power.

A method for generating precisely amplitude modulated signals using a non-linear class C amplifier called so-called " plate modulation " is described in Terman's Wireless Engineer's Handbook (McGraw-Hill, 1943) Has been known for over 70 years, as described in textbooks such as In a typical plate-modulation technique, the output current from the modulator amplifier is linearly added to the supply current for the amplification element (tube or transistor), which means that the supply current increases in its mean value . This varying current causes the apparent supply voltage for the amplifying element to vary, depending on the resistance (or conductance) characteristics of the amplifying element.

With this direct control of the output power, the AM can be performed as long as the bandwidth of the varying operating voltage is sufficient. That is, these nonlinear amplifiers actually operate as linear amplifiers for the amplifier operating voltage. The output signal will be linearly amplitude modulated to the extent that the operating voltage can vary over time during driving the nonlinear power amplifier.

Other methods of achieving amplitude modulation are described in the following U.S. patents: 4,580,111; 4,804,931; 5,268, 658, and 5,652, 546, which are incorporated herein by reference. Amplitude modulation by using pulse-width modulation to change the power of the power amplifier is described in the following U.S. Patents: 4,896,372; 3,506,920; 3,588,744 and 3,413,570. However, these patents teach that the operating frequency of the switch-mode DC-DC converter should be significantly higher than the maximum modulation frequency.

U.S. Patent No. 5,126,688 to Nakanishi et al., In combination with periodic adjustment of the power amplifier operating voltage to improve the operating efficiency of the power amplifier, uses feedback control to set the actual amplifier output power Control of linear amplifiers is covered. The main disadvantage of this technique is the need for additional control circuitry to determine if the power amplifier operating voltage should be modified to improve efficiency and to detect the desired output voltage to make any changes if so determined. This additional control circuit increases the amplifier complexity and results in additional power beyond the power of the amplifier itself, which directly reduces the overall efficiency.

There was an additional challenge to generate high-power RF signals with desired modulation characteristics. This object is achieved by the teachings of Swanson U.S. Patent No. 4,580,111 by using a number of high efficiency amplifiers that provide a fixed output power, And are enabled in sequence to be individual amplifier power. In this scheme, the minimum change in total output power is essentially equal to the power of each of the multiple high efficiency amplifiers. If a finely graded output power resolution is required, a very large number of individual high efficiency amplifiers may be potentially required. This obviously increases the overall complexity of the amplifier.

U.S. Patent No. 5,321,799 performs polar modulation but is limited to pre-response data signals and is not useful with high power, high-efficiency amplifiers. The patent teaches that amplitude variations for a modulated signal are applied through a digital multiplier that comes after the phase modulation and signal generating stages. The final analog signal is then generated using a digital-to-analog converter. Signals having information already implemented in amplitude variations as described herein in the background art are incompatible with high-efficiency nonlinear power amplifiers due to possible severe distortion of signal amplitude variations.

Notwithstanding the teachings of these references, a number of problems have been addressed, including the following: (i) by using a switch mode transducer without requiring high-frequency switch-mode operation Achieving high-efficiency amplitude modulation of the RF signal by variation of the operating voltage; Integrating power-level and burst control with modulation control; Enabling high-efficiency modulation of any desired characteristics (amplitude and / or phase); And enabling high-power operation (e.g., for base stations) without sacrificing power efficiency.

The present invention relates to an RF amplifier and signal modulation.

1 is a block diagram of a known power amplifier having an output power controlled by varying the power supply voltage.

Figure 2 is a simplified block diagram of a known single-ended switch mode RF amplifier.

3 is a schematic diagram of a portion of a known RF amplifier.

4 is a schematic diagram of a conventional RF power amplifier circuit.

5 is a schematic diagram of another conventional RF power amplifier circuit.

6 is a block diagram of a known IQ modulation structure.

7 is a block diagram of a power amplifier according to an exemplary embodiment.

8 is a graphical representation Lt; RTI ID = 0.0 > AB < / RTI > power amplifier output power versus operating voltage.

9 is a waveform diagram illustrating the operation of one embodiment.

10 is a waveform diagram illustrating the operation of another embodiment.

11 is a waveform diagram for explaining the burst AM operation.

12 is a waveform diagram illustrating burst AM operation with power level control.

13 is a block diagram of a polar modulation structure using a high-efficiency amplifier.

14 is a block diagram of a first high power, high efficiency, amplitude modulated RF amplifier.

15 is a waveform diagram for explaining the operation of the amplifier of Fig.

16 is a block diagram of a second high power, high efficiency, amplitude modulated RF amplifier.

17 is a waveform diagram for explaining the operation of the amplifier of Fig.

18 is a block diagram of an RF switch mode amplifier according to one embodiment.

19 is a schematic diagram of a portion of an RF switch mode amplifier according to one embodiment of the present invention.

Figure 20 is a schematic diagram of a load network suitable for use in the RF switch mode amplifier of Figure 19;

Figure 21 is a waveform diagram showing the input voltage and associated waveforms for the RF switch mode amplifier of Figure 19;

22 is a waveform diagram showing the base and collector current waveforms of the switching transistor of Fig.

FIG. 23 is a waveform diagram showing the output voltage for the RF switch mode amplifier of FIG. 19; FIG.

24 is a schematic diagram of a portion of an RF switch mode amplifier according to another embodiment.

25 is a waveform diagram illustrating input voltages and associated waveforms for the RF switch mode amplifier of FIG.

26 is a waveform diagram showing collector current waveforms of the drive transistors of FIG. 24. FIG.

FIG. 27 is a waveform diagram showing a gate voltage waveform of the switching transistor of FIG. 24. FIG.

28 is a schematic diagram of an RF power amplifier circuit according to another embodiment.

Fig. 29 is a waveform diagram showing waveforms occurring at selected nodes of the amplifier circuit of Fig. 28; Fig.

The present invention generally provides high-efficiency power control of high efficiency (e.g., hard-limiting or switch-mode) power amplifiers in a manner that can achieve the desired control or modulation. Unlike the prior art, no feedback is required. That is, the amplifier can be controlled without continuous or frequent feedback adjustment. In one embodiment, the spread between the maximum frequency of the desired modulation and the operating frequency of the switch-mode DC-DC converter is reduced by placing an active linear regulator after the switch-mode converter. The linear regulator is designed to control the operating voltage of the power amplifier with sufficient bandwidth to faithfully reproduce the desired amplitude modulated waveform. The linear regulator is further designed to eliminate variations in its input voltage even while the output voltage is changing in response to an applied control signal. The removal will occur even if the variations for the input voltage are at a frequency equal to or much lower than the frequency of the controlled output variation. Amplitude modulation can be achieved by directly or effectively varying the operating voltage for the power amplifier while simultaneously achieving high efficiency in converting the main DC power to the amplitude modulated output signal. High efficiency is enhanced by allowing the switch-mode DC-DC converter to change its output voltage so that the voltage drop across the linear regulator is low and remains at a relatively constant level. The time-division multiple access (TDMA) bursting capability can be combined with effective amplitude modulation, with control of these functions being combined. Moreover, variations in the average output power level in accordance with instructions from the communication system may also be combined in the same structure.

The high-efficiency amplitude modulation scheme may be extended to any arbitrary modulation. The modulation is performed in a polar form, that is, quarture-free.

Single high-efficiency stages can be combined together to form high-power, high-efficiency modulation structures.

The invention may be better understood from the following description taken in conjunction with the accompanying drawings.

Referring now to FIG. 7, a block diagram of a power amplifier is shown that overcomes many of the above mentioned drawbacks. A switch-mode (or saturating) nonlinear amplifier applied to it the voltage generated by the power control stage. In an exemplary embodiment, the voltage (V) applied to the nonlinear amplifier is given by Equation As shown in FIG. Where P is the desired power output level of the amplifier and R is the resistance value of the amplifier. In the case of a switch-mode or a saturated amplifier, the resistance value R can be considered to be constant. The power control stage receives, for example, a DC input voltage from a battery, receives a power level control signal, and outputs a voltage according to the above equation.

The effect of directly controlling the output power of the nonlinear amplifiers over a wide dynamic range by changing only the operating voltage is specified in Fig. 8, which shows that the saturation class AB power amplifier output power vs. mathematical model ≪ / RTI > is compared.

Referring again to Fig. 7, a power control circuit according to an exemplary embodiment is shown. The power control circuit includes a switched-mode converter stage and a linear regulator stage connected in series. The switch-mode converter stage may be, for example, a Class D device or a switch-mode power supply (SMPS). The switch-mode converter effectively reduces the DC voltage to a similar voltage, somewhat exceeding the desired power-amplifier operating voltage level. That is, the switch-mode converter performs effective overall power level control. The switch-mode converter may or may not provide sufficiently fine control to define the ramp portion of the desired power envelope.

The linear regulator performs a filtering function on the output of the switch-mode converter. That is, the linear regulator controls precise power-envelope modulation during a TDMA burst, for example. The linear regulator may or may not provide the same level control capability as the switch-mode converter.

Note that depending on the speed of the switch-mode converter and the linear regulator, the power control circuit may be used to perform power control and / or amplitude modulation. The control signal PL / BURST / MOD is input to the control unit, which outputs appropriate analog or digital control signals for the switch-mode converter and the linear regulator. The control unit may be realized as a read-only memory (ROM) and / or a digital-to-analog converter (DAC).

Referring to FIG. 9, a waveform diagram illustrating operation of an embodiment of the present invention is shown. The waveforms A and B represent the analog control signals respectively applied to the switch-mode converter and the linear regulator. The waveforms ( ) Represent the output voltages of the switch-mode converter and the linear regulator, respectively. Assume that the switch-mode converter has a relatively large time constant. That is, the switch-mode converter ramps relatively slowly. When the control signal (A) is set to a first non-zero power level, the voltage ) Will begin to ramp toward an equivalent voltage. Because of the switch-mode nature of the converter, the voltage ) Can have a significant amount of ripple. The amount of time required to reach the desired voltage defines a wake-up period. When the voltage is reached, the control signal B rises and falls to define a series of transmission bursts. When the control signal (B) rises, the voltage ) Rapidly ramps up to an equivalent voltage, and when the control signal (B) falls, the voltage ) Quickly ramps down. Following a series of bursts (in this example), the control signal A is raised to increase the RF power level of subsequent bursts. The control signal B is kept low during the waiting time. The voltage ( ) Reaches a certain level, the control signal (B) rises and falls to define an additional series of transmission bursts.

The voltage ( ) ≪ / RTI > As shown in Fig. The voltage ( ) Is less than the voltage < RTI ID = 0.0 > ), And the voltage ( ) ≪ / RTI > The input voltage of the linear regulator ( ) And the output voltage of the linear regulator ( ) Allows the overall high-efficiency operation.

10, the switch-mode converter is assumed to have a relatively short time constant; That is, it ramps relatively quickly. Therefore, when the control signal A rises, the voltage ( ) Quickly ramps to the equivalent voltage. Then, the control signal (B) rises and the voltage Lt; / RTI > The time difference between when the control signal A rises and when the control signal B rises defines the wake-up time, which is very short and maximizes sleep time and power savings. Then, the control signal (B) is lowered at the end of the transmission burst, and then the control signal (A) is lowered. 9, next, in Fig. 10, when the control signal A rises next, it defines a higher power level. Again, the voltage ) ≪ / RTI > ). ≪ / RTI >

The same structure can be used to perform amplitude modulation in addition to power and burst control. Referring to FIG. 11, a waveform diagram illustrating the burst AM operation is shown. The output signal of the switch-mode converter is shown as a solid line. When the burst starts, the output signal of the switch-mode converter ramps up. Optionally, as shown by the dashed line, the switch-mode converter can ramp up to a fixed level with the linear regulator performing all amplitude modulation on the output signal. More preferably, in terms of efficiency, the switch-mode converter performs amplitude modulation and ignores the noise to produce a small fixed offset (" ≪ / RTI > Wherein the linear regulator removes the noise from an output signal of the switch-mode converter, ) Effectively. The output signal of the linear regulator is shown in dashed lines in FIG. At the end of the burst, the signals are ramped down.

Full control of the output signal power level (average power of the signal) is maintained. For example, the next burst may occur at a higher power level as shown in FIG. Compared to FIG. 11, all of the signals in FIG. 12 are suitably scaled to achieve a higher average power output.

The integration of amplitude modulation for a phase-modulated signal is often desirable because these signals can occupy and often occupy a smaller bandwidth than purely phase-modulated signals, even though it may complicate the signal generation method. Do. Referring to FIG. 13, a block diagram for a polar modulation structure using a high-efficiency amplifier of the type described above is shown. The polar modulation structure may perform any desired modulation. A data signal is applied to a modulation encoder that generates amplitude and phase signals. The phase signal is applied to a phase-modifiable carrier generator, to which a tuning signal is also applied. The resulting signal is then amplified by a non-linear power amplifier of the type previously described. On the other hand, the amplitude signal is applied to the amplitude driver. The amplitude driver also receives a power control signal. In response, the amplitude driver generates an operating voltage that is applied to the non-linear amplifier. The amplitude driver and the non-linear amplifier can be realized in the same manner as shown in Fig. 7 described previously, as shown in Fig. 13 by dashed lines.

The modulation schemes described so far are suitable for use in cellular telephone handsets among other applications. A similar need for high-efficiency RF signal generation exists in cellular telephone base stations. However, base stations operate at much higher power than handsets. The following structure can be used to achieve high-power, high-efficiency RF signal generation.

Referring to Figure 14, a first high power, high efficiency, amplitude modulated RF amplifier includes a plurality of switch mode power amplifier (SMPA) blocks, for example, It is realized together. The RF signal to be amplified is commonly input to all the SMPA blocks. Individual control signals for each of the SMPA blocks are generated by an amplitude driver in response to the amplitude input signal. The output signals of the SMPA blocks are summed to form the resulting single output signal.

The manner of operation of the amplifier of Fig. 14 can be understood with reference to Fig. The left side shows the total amplitude signal applied to the amplitude driver. And the SMPA drive signals output by the amplitude driver to be applied to the respective SMPA are shown on the right side. Note that the sum of the individual drive signals yields the overall amplitude signal.

An alternative embodiment of a high-power amplifier is shown in FIG. In this embodiment, instead of generating separate drive signals for each SMPA, a common drive signal is generated and applied to all the SMPAs in common. At a given instant in time, the common drive signal is caused to have a value that is one-nth of the total amplitude signal applied to the amplitude driver when N is a number of SMPA's. The results are shown in Fig. Again, note that the sum of the individual drive signals yields the overall amplitude signal.

Referring now to FIG. 18, a block diagram of an RF switched mode amplifier according to another embodiment is shown. The RF input signal is applied to a non-reactive driving circuit. The driving circuit is connected to an active device to drive an active device switch. The active device switch is coupled to a load network that generates an RF output signal for application to a load, such as, for example, an antenna. Preferably, the active device switch is applied to the active device switch via a rapid time variable power supply, realized by a series combination of a switched mode power supply and a linear regulator, such that the operating voltage of the active device switch is changed do. By changing the operating voltage in a control manner, power control, burst control and modulation can be achieved as previously described.

The active device switch may be a bipolar transistor or a FET transistor. Referring to FIG. 19, a schematic diagram of a portion of an RF switch mode amplifier in which the active device switch is a bipolar transistor with collector, emitter, and base terminals is shown. The collector of the bipolar transistor N1 is connected to the collector of the bipolar transistor N1 through the RF choke L, And is also connected to the output matching network. The emitter of the bipolar transistor N1 is connected to the circuit (AC) ground.

The base of the bipolar transistor N1 is connected to the emitter of another bipolar transistor N2 (driver transistor) in the Darlington scheme. The collector of the driver transistor (N2) ) And is also connected to the bypass capacitor. Associated with the driver transistor N2 is, in the illustrated embodiment, a bias network comprising three resistors R1, R2 and R3. A resistor R1 is connected from the emitter of the driver transistor to the circuit ground. The other resistor R2 is connected to the ground from the base of the driver transistor. The final resistor R3 is connected from the base of the driver transistor N2 Lt; / RTI > The RF input signal is input to a DC isolation capacitor ( To the base of the driver transistor.

Referring to FIG. 20, the output network includes an impedance-matching transmission line TL and a capacitor ) Can be taken.

The RF input voltage signal is a sinusoid as shown by waveform (1) in FIG. The input voltage is shifted upwards to produce a voltage at the base of the driver transistor N2, which is illustrated by waveform 2. The emitter voltage of the driver transistor N2, shown by waveform 3, Drop and is applied to the base of the switching transistor N1. At the beginning of the positive half-cycle, the driver transistor N2 has an output (emitter) voltage that is below the sufficient turn-on voltage of the switching transistor N1 to turn off the switching transistor N1, And acts as an emitter follower. When the signal increases, the driver transistor N2 turns on the switching transistor N1 and drives the switching transistor to a saturation state as shown in FIG. A current flows through the RF choke L and the switching transistor N1, and the output voltage flows through the capacitor Is discharged as shown in Fig. Near the end of the positive half-cycle, the output voltage of the driver transistor N2 falls below the turn-on voltage of the switching transistor N1, which turns off the switching transistor. The value of the resistor R1 is selected such that the switching transistor N1 is quickly cut off. Current continues to flow through the RF choke L, ) So that the output voltage is increased.

Referring to FIG. 24, a schematic diagram of a portion of an RF switch mode amplifier in which the active device switch is a FET transistor (MESFET, JFET, PHEMT, etc.) having drain, source and gate terminals is shown. The drain of the FET transistor Ml is connected to an operating voltage (< RTI ID = 0.0 > And is also connected to the output network. The source of the FET transistor is connected to the circuit (AC) ground.

The gate of the FET transistor is connected to a power source (< RTI ID = 0.0 > And connected to a pair of bipolar transistors (driver transistors) connected in a push-pull configuration through a DC isolation capacitor Cl. The driver transistors include an NPN transistor N1 and a PNP transistor P1. The collector of the NPN driver transistor (N1) ) And is also connected to the bypass capacitor. The collector of the PNP driver transistor < RTI ID = 0.0 > P1 < / RTI & ) And is also connected to the bypass capacitor. The bases of the driver transistors are connected in common. Resistors R2 and R3 having a large resistance value connect the common node to each power supply rail.

The additional NPN bipolar transistor N2 is connected in a common base configuration. The emitter of the additional bipolar transistor is connected via a resistor R4 And is connected to the RF input signal via a capacitor C3. The collector of the additional bipolar transistor is coupled through an inductor (L2) And is also connected to the bypass capacitor.

Referring to Fig. 25, input voltage waveforms 1-4 for the circuit of Fig. 24 are shown. The input voltage (1) is 1 Shifted down (generating voltage 2) and then applied to the emitter of the bipolar transistor N2. A large voltage swing 3 is generated in the collector of the bipolar transistor N2 by the action of the inductor L2. The voltage swing is shifted downward to produce a voltage (4) applied to the bases of the driver transistors at the node (N). In operation, the additional bipolar transistor N2 is initially turned off during the positive half-cycle. A current flows in the capacitor C2 connected to the bases of the transistor pair through the inductor L2 causing the NPN transistor N1 to turn on and the PNP transistor P1 to turn off ). The DC separation capacitor (C1) Which is charged from the power supply, raising the gate potential of the FET M1 and causing the FET M1 to be turned on (Fig. 27). During the negative half-cycle, the additional bipolar transistor N2 is turned on. The current flows through the inductor L2, through the additional transistor N2, It flows to the rail. Further, a current flows from the base of the PNP transistor P1 and turns on the transistor. The DC isolation capacitor (C1) discharges and lowers the gate potential of the FET (M1). The FET M1 is turned off. The output network operates in the same manner as previously described.

Referring now to FIG. 28, a schematic diagram for a multi-stage RF power amplifier in which the driver circuit described above can be used is shown. Coupling capacitor ( ), A capacitor ) And an inductor ) Is used to set the input impedance of the circuit. Driver stage ( ) And the final stage Are shown as FETs, although bipolar transistors may be used in other embodiments. The FET ( ) Is connected to the RF choke ) And capacitors Lt; RTI ID = 0.0 >(" . Similarly, the FET ( ) Is connected to the RF choke ) And capacitors Lt; RTI ID = 0.0 >(" .

The stages ( ) Are provided with respective gate bias networks. The stage ( ), The gate-bias network is at a common node < RTI ID = 0.0 > ), An inductor ), A capacitor ) And capacitors ). The stage ( ), The gate-bias network is at a common node < RTI ID = 0.0 > ), An inductor ), A capacitor ) And capacitors ).

The driver stage and the final stage are connected to an inductor ) And capacitors ), Which are connected by an interstage network shown here as values of the inductor and capacitor, Quot;) < / RTI > The final stage ( ) Is a capacitor ), An inductor ) And capacitors ) Connected to a conventional load network as described in this example, the values of the inductor and the capacitors being connected to the final stage ). ≪ / RTI >

In an exemplary embodiment, the component values are as follows, where the capacitance is measured as a picofarad and the inductance is measured as a nanohenry:

Capacitor pf Inductor nh Voltage V 27 8.2 3.3 10 33 3.2 0.01 33 -1.53 27 4.7 -1.27 27 NA 27 39 NA 15 27 2.7 0.01 27 1.5 5.6

In the example of Fig. 28, Operate in switch mode. Referring to FIG. 29, in node A, The input voltage to node B, The drain current of node C, ) At node D, the drain voltage of node ) At node E and the drain current at node E ≪ / RTI > are provided. The final stage, stage ( Note that the peak value of the gate voltage of the gate electrode (waveform A) is considerably larger than in the conventional designs. In such a configuration, the input drive of the switch may be high enough to reduce the operating voltage of the driver stage. In addition, the reduction reduces the DC supply power to the driver, which increases the PAE.

Using the described types of circuits, a PAE of 72% was measured at an output power of 2W.

Thus, power amplifier circuit configurations have been described that include driving circuits and multi-stage amplifier circuits that allow precise generation of desired RF waveforms with no need for feedback and with high power-adding efficiency.

Claims (21)

Voltage regulator means for generating a specific voltage within a voltage range in accordance with a control signal for performing at least one of level control, burst control and modulation; And And a final amplification stage having said specific voltage as a power supply voltage and wherein said final amplification stage is in a hard-on state and a hard-off state without operating said amplifier in a linear operating region for a definite percentage of time ) State, a power amplifier having a driving signal to be repeatedly driven between two states, Wherein the amplifier is controlled without continuous or frequent feedback adjustment. 3. The variable output RF power amplifier of claim 2, wherein the voltage regulator means comprises a first switch-mode converter stage and a second linear regulator stage. 3. The variable output RF power amplifier of claim 2, wherein the switch-mode converter stage provides coarse level control and the linear adjuster stage provides fine ramp control. 4. The variable output RF power amplifier of claim 3, wherein the power amplifier is hard-limited. 5. The variable output RF power amplifier of claim 4, wherein the power amplifier is any saturation amplifier selected from the group consisting of Class A, Class AB and Class C amplifiers. 4. The variable output RF power amplifier of claim 3, wherein the power amplifier is a switch-mode amplifier. 4. The variable output RF power amplifier of claim 3, wherein the power amplifier is a Class C amplifier. 3. The variable output RF power amplifier of claim 2, wherein the switch-mode converter stage provides level control and ramp control. 3. The variable output RF power amplifier of claim 2, wherein the linear regulating base provides ramp control and level control. 3. The apparatus of claim 2 further comprising means for receiving the control signal and responsive thereto for generating a first control signal for the switch-mode converter stage and a second control signal for the linear regulator stage, Variable output RF power amplifier. 3. The apparatus of claim 2, further comprising an amplitude driver responsive to a modulation signal to generate a first control signal for the switch-mode converter stage and a second control signal for the linear regulator stage, RF power amplifier. 3. The variable output RF power amplifier of claim 2, further comprising means responsive to a phase control signal to generate a carrier signal having phase modulation characteristics, wherein the carrier signal is applied to the RF power amplifier. 13. The variable output RF power amplifier of claim 12, wherein the modulating signal is an amplitude control signal and the RF signal is amplitude modulated. 14. The variable output RF power amplifier of claim 13, further comprising a modulation encoder responsive to a data signal for generating the amplitude control signal and the phase control signal. 15. The variable output RF power amplifier of claim 14, wherein the modulation encoder operates in a polar coordinate system. 3. The apparatus of claim 2, further comprising a plurality of amplifier modules and an amplitude driver for generating one or more amplitude drive signals in response to the total amplitude signal, A switch mode converter having a power input, a power output and a control input; A regulator having a power input, a power output, and a control input; An amplitude driver for generating a first control signal coupled to the control input of the switch mode converter in response to the modulation signal and a second control signal coupled to the control input of the regulator; And Comprising an RF power amplifier having a non-linear operable mode, The power input of the regulator being coupled to the power output of the switch-mode converter, the power output of the regulator supplying an operating voltage of the RF power amplifier, and the RF signal being common to all the RF power amplifiers And an amplitude drive signal is applied to each of the RF power amplifiers. 17. The variable output RF power amplifier of claim 16, wherein separate angular amplitude drive signals are generated for each of the RF power amplifiers. 17. The variable output RF power amplifier of claim 16, wherein a single amplitude drive signal is commonly applied to all of the RF power amplifiers. Generating a specific voltage according to a control signal for performing at least one of level control, burst control, and modulation; Applying the specific voltage to a power amplifier as a power supply voltage of a final amplification stage of the power amplifier; And Repeatedly driving the final amplification stage between the two states, a hard-on state and a hard-off state, without operating the amplifier in a linear operating region for a definite percentage of the time and, Wherein the amplifier is controlled without continuous or frequent feedback adjustments. 20. The method of claim 19, further comprising the step of applying an RF input signal to the RF amplifier, wherein the RF input signal is phase modulated. 21. The method of claim 20, further comprising: encoding data to polar coordinates to generate an amplitude signal and a phase signal; And Generating the RF input signal in accordance with the phase signal, Wherein the modulated signal is derived from the amplitude signal.