KR20030016017A - Method for fabricating of an array substrate for LCD - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device for improving image quality by reducing parasitic capacitance variations generated between data wirings and pixel electrodes.

According to the present invention, when a black matrix formed on an upper substrate is formed in advance by shielding bars formed below the separation area between the pixel electrode and the data wiring, the aperture ratio can be improved. It has an effect.

In addition, when the pixel electrode is patterned, a back exposure method may be used to prevent variation in a distance between the pixel electrode and the data wiring due to misalignment of the mask. Therefore, the parasitic capacitance C _DP generated between the pixel electrode and the data wiring and the deviation ΔC _DP between the parasitic capacitance can be prevented.

It is possible to manufacture a liquid crystal display device of vivid image quality by the above effects.

Description

Method for fabricating an array substrate for a liquid crystal display device {Method for fabricating of an array substrate for LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate for a liquid crystal display device (LCD), and particularly to an array substrate using an inorganic insulating film having a high dielectric constant as a protective film, which reduces parasitic capacitance variation ΔC _DP generated between data wiring and a pixel electrode. In addition, the present invention relates to a method of manufacturing an array substrate for improving the aperture ratio.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

1 is a view schematically showing a general liquid crystal display device.

As shown in the drawing, a general color liquid crystal display 11 includes a black matrix 6 formed between a color filter 7 and each of the color filters 7 and a common electrode 18 deposited on the color filter and the black matrix. ) Is formed of an upper substrate (5) formed thereon, a pixel region (P), a pixel electrode (17) formed on the pixel region, and a lower substrate (22) on which switching elements (T) and array wiring are formed. The liquid crystal 14 is filled between 5) and the lower substrate 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above. .

The pixel electrode 17 uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO).

The driving of the liquid crystal panel having the configuration as described above is due to the electro-optical effect of the liquid crystal.

In detail, the liquid crystal layer 14 is a dielectric anisotropic material having a spontaneous polarization characteristic, and when a voltage is applied, the arrangement direction of molecules is changed according to the direction of application of an electric field by forming a dipole by spontaneous polarization. Has

Therefore, the optical characteristic is changed according to this arrangement state, thereby causing electrical light modulation.

By the optical modulation of the liquid crystal, an image is realized by a method of blocking or passing light.

FIG. 2 is an enlarged plan view schematically illustrating a part of the array substrate in the configuration of FIG. 1.

The elements necessary for driving the liquid crystal layer 14 of FIG. 1 include a gate wiring 13 transmitting a scanning signal and a image signal, and an image signal. A thin film transistor T, which is a switching element connected to the data wiring 15, the gate wiring and the data wiring, and positioned at the intersection of the gate wiring 13 and the data wiring 15, and the thin film. It is a pixel electrode 17 connected to the transistor.

The thin film transistor T includes a gate electrode 31 connected to the gate wiring 13, a source electrode 33 and a drain electrode formed to overlap a predetermined area with the gate electrode 31 on the gate electrode 31. 35. The source electrode 33 and the drain electrode 35 are spaced apart from each other with a semiconductor layer 32 (hereinafter, referred to as an “active layer”) interposed therebetween.

The active layer 32 is generally formed using amorphous silicon (a-Si: H), and in some cases, may be formed of polysilicon.

In this case, the source electrode 33 is connected to the data line 15, and the drain electrode 35 is connected to the pixel electrode 17 positioned on the pixel area P.

Here, a part of the pixel electrode 17 extends to an upper portion of the gate line 13 defining the pixel area P to form a storage capacitor C _st (C) together with the gate line. Therefore, the configuration of the storage capacitor can be variously modified.)

In the above-described configuration, the gate wiring 13 functions as a first storage electrode, and the storage metal layer 26 in contact with the pixel electrode 17 functions as a second storage electrode.

In the above-described configuration, since the spaced area between the pixel electrode 17 and the data wiring 15 is a light leaking area, the black matrix 6 is disposed on the upper substrate 5 shown in FIG. It must be covered.

In this case, the black matrix 6 may include the case where the separation region is exposed by the misalignment of the upper substrate 5 and the lower substrate 22 and the pixel electrode and the data wiring due to the misalignment of the mask. It is common to design margins in case the separation distance between them is further increased.

A description with reference to FIG. 3 is as follows. FIG. 3 is a partial cross-sectional view of the liquid crystal display device taken along line III-III and IV-IV of FIG. 2 (the upper substrate corresponding to the cut lower substrate is simultaneously shown).

As shown, the protective film 16 is formed on the entire surface of the substrate 22 including the gate electrode 31, the active layer 32, and the thin film transistor T composed of the source electrode and the drain electrode 33, 35. Is formed.

In this case, the passivation layer 16 may be formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) or silicon oxide (SiO ₂ ).

The data line 15 is positioned below the passivation layer 16, and the pixel electrodes 17 are positioned on both sides of the data line 15.

In this configuration, since the data line 15 and the pixel electrode 17 cannot be superimposed in a plane to avoid signal interference with each other, the data line 15 and the pixel electrode 17 should be spaced apart from each other within a range not affecting each other.

Because the passivation layer 16 is made of an inorganic insulating material having a high dielectric constant, when the data line 15 and the pixel electrode 17 are configured to be too close or overlap each other, the pixel electrode 17 and the data line 15 This is because parasitic capacitance will be generated between and, and the parasitic capacitance will cause distortion of the pixel voltage applied to the pixel electrode 17.

In order to prevent such a phenomenon, the separation distance K between the data line 15 and the pixel electrode 17 should be basically 3 μm or more.

Accordingly, the pixel electrodes 17 are positioned to be spaced apart from each other by 3 μm or more on both sides of the data line 15.

As mentioned above, the distance between the data line 15 and the pixel electrode 17 should be masked by the black matrix 6 positioned between the color filter 7 of the upper substrate 5, wherein the black matrix ( 6) should be designed in consideration of the bonding error between the upper substrate 5 and the lower substrate 22 and an error due to misalignment of a mask (not shown) during patterning of the pixel electrode 17.

General bonding margin is designed to have a margin of 3㎛ ~ 5㎛ on both sides around the data wiring.

As a result, when viewed from an observer's perspective, an area in which no image except for the data line and the gate line is expressed is obtained by adding up the distance between the data line and the pixel electrode and the margin of the black matrix. It corresponds to the distance of 6 micrometers-8 micrometers on both sides, respectively.

When the total area of the liquid crystal panel is taken into consideration, the margin width of the black matrix decreases the aperture ratio, thereby degrading the image quality of the liquid crystal panel.

Accordingly, in order to reduce the separation distance between the data line and the pixel electrode, a method of using a transparent organic insulating material including benzocyclobutene (BCB) and an acrylic resin having a low dielectric constant is used as the passivation layer. Proposed.

However, since the organic insulating material is high in price, its use is limited.

Another cause of deterioration of the image quality of the liquid crystal panel is due to a non-uniform distance between the data line and the pixel electrode due to a misalignment of a mask during a photo-lithography process of patterning the pixel electrode. This is due to the parasitic capacitance generated (C _DP ) (total array substrate).

A method for solving such a problem of variation in parasitic capacitance due to misalignment of a mask has been proposed in Korean Patent Laid-Open Publication No. 2000-74752.

A description with reference to FIGS. 4A and 4B is as follows.

4A and 4B illustrate only a back exposure process for patterning a pixel electrode during the array substrate manufacturing process of Korean Patent Publication No. 2000-74752. (The illustrated figure shows a data wiring area and a storage area of FIG. 2. (C))

As shown, a gate insulating film 12 is formed on the gate wiring 13, and a data wiring 15 is formed on the gate insulating film 12, and at the same time, the gate wiring of the storage region C is formed. An island-shaped storage metal layer 26 is formed on the upper portion of 13.

The passivation layer 16 is formed on the data line 15 and the storage metal layer 26.

The passivation layer 16 is formed of one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ).

Next, the transparent metal layer 17a is formed by depositing a transparent metal on the entire surface of the substrate 22 on which the passivation layer 16 is formed.

A negative photo-resist is applied on the transparent metal layer 17a to form a negative PR layer 40.

The negative PR layer 40 has a characteristic that a portion that receives light is not developed.

A mask 46 having a transmissive region corresponding to the storage region C is positioned on the substrate 22 on which the PR layer is formed.

Next, the PR layer 40 is exposed by irradiating light L1 and L2 from the upper and lower portions of the substrate 22.

Therefore, when the PR layer 40 having the exposure process is completed, the transparent metal layer 17a positioned on the gate line 13 and the data line 15 is exposed.

However, the transparent metal layer positioned on the gate wiring 13 of the storage area C is not exposed. This is because the front exposure is performed using the mask 46 while the back exposure is in progress.

As shown in FIG. 4B, when the exposed transparent metal layer 17a is etched, the exposed transparent metal layer 17a is disposed on the pixel region P while being in contact with the drain electrode (not shown), and part of the transparent metal layer 17a is planar with the gate wiring 13. The pixel electrodes 17 overlapping each other are formed.

At this time, the distances R and L between the data line 15 and the pixel electrodes 17 located on both sides of the data line 15 are the same. Therefore, the separation distance between the pixel electrode 17 and the data wiring 15 can be constant for the entire area of the liquid crystal panel.

However, in the second example of the related art, the distance between the data line 15 and the pixel electrode 17 may be configured to be constant, but the back exposure using the gate line 13 and the data line 15 as light blocking means. Since the method is used, the separation distance between the data wiring 15 and the pixel electrode 17 is very short.

Therefore, since the second conventional example uses an inorganic insulating film having a high dielectric constant as a protective film, the image quality is expected to be deteriorated by the parasitic capacitance generated between the data wiring 15 and the pixel electrode 17.

According to an exemplary embodiment of the present invention, in the structure of an array substrate using an inorganic insulating film as the passivation layer 16, the bonding margin of the black matrix is reduced, and the data line 15 and the pixel electrode 17 are reduced. The purpose is to improve the image quality and aperture ratio of the liquid crystal panel by constantly designing the separation distance therebetween.

To this end, a method of constructing a shielding bar below the spaced distance between the pixel electrode 17 and the data line 15 is proposed.

1 is an exploded perspective view schematically showing a general transmissive liquid crystal display device;

FIG. 2 is a plan view schematically illustrating a part of an array substrate for a liquid crystal display device according to a first example of the related art.

3 is a cross-sectional view according to a first example of the related art taken along III-III and IV-IV of FIG. 2,

4A through 4B are cross-sectional views illustrating a pixel electrode forming process according to a data wiring region and a storage region of FIG.

5 is a schematic cross-sectional view of a portion of an array substrate for a liquid crystal display device according to a first embodiment of the present invention;

6 is a cross-sectional view taken along the line VIII-VIII of FIG. 5,

7A to 7D are cross-sectional views illustrating a process sequence according to the first embodiment of the present invention by cutting VI-VI, VIII-VIII of FIG. 6,

8 is a schematic cross-sectional view of a portion of an array substrate for a liquid crystal display device according to a second embodiment of the present invention;

9 is a cross-sectional view taken along the line VIII-VIII of FIG. 8,

10A to 10C are cross-sectional views taken along the line VIII-VIII of FIG. 8 and according to the process sequence according to the second embodiment of the present invention.

<Brief description of the main parts of the drawing>

100: substrate 102: gate wiring

104: gate electrode 106a, 106b: shielding bar

114: source electrode 116: drain electrode

118 data wiring 120 storage metal layer

132 pixel electrode

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method including: preparing a substrate; Defining a region where a gate wiring and a data wiring are to be formed on the substrate; Forming a plurality of gate wirings formed in one direction on the substrate in the gate wiring region and two shielding bars configured in one direction and spaced apart from each other by a predetermined distance in the region where the data wiring is to be formed; Forming a gate insulating film, which is a first insulating film, on the substrate including the gate wiring and the shielding bar; Defining a pixel area on the gate insulating layer to perpendicularly intersect the gate line, and forming a data line on the two shielding bars; Forming a protective film, which is a second insulating film, on the entire surface of the substrate on which the gate wiring, the data wiring, and the thin film transistor are formed; Forming a transparent electrode layer on the passivation layer, and coating a negative photoresist on the transparent electrode layer to form a photoresist layer; Placing a mask formed of a transmissive portion on a portion of the thin film transistor and a portion of a gate wiring defining the pixel region on the substrate on which the photoresist layer is formed, and irradiating light from the upper and lower portions of the substrate; Wow; By developing the photoresist layer exposed by the irradiated light, the exposed transparent electrode layer is etched to form a pixel electrode positioned on the pixel region, partially in contact with the thin film transistor, and partially extending over the gate wiring. It includes a step.

The thin film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode.

In the above-described configuration, the pixel electrode is configured to be in contact with the drain electrode.

The pixel electrode and the shielding bar are formed to be spaced apart from each other by a predetermined interval, and the shielding bar and the data wiring are formed to overlap a predetermined area.

At this time, the width of the overlapped area of the data line and the shielding bar is 1 μm.

As another example, the pixel electrode and the shielding bar may be formed to overlap a predetermined area, and the data wiring and the shielding bar may be formed to be spaced apart by a predetermined distance.

In this case, the width of the overlapped area between the shielding bar and the pixel electrode is 1 μm.

The shielding bar is characterized in that the width of 3㎛.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

Example

A feature of the present invention is to design a shielding bar below the distance between the data line and the pixel electrode, and to use the back exposure method in the photolithography process of forming the pixel electrode.

5 is a plan view schematically illustrating some pixels of an array substrate for a liquid crystal display according to the present invention.

As shown, the array substrate 100 according to the present invention is configured by crossing the gate wiring 102 and the data wiring 118 defining the pixel region P, and the switching point is a switching element at the intersection of the two wirings. The thin film transistor T is constituted.

At this time, the width of the data line 118 is designed to have a width of about 8.0㎛.

The thin film transistor T includes a gate electrode 104, an active layer 110, a source electrode 114, and a drain electrode 116.

The source electrode 114 is electrically connected to the data line 118, and the gate electrode 104 is electrically connected to the gate line 102.

The pixel region P constitutes a pixel electrode 132 in contact with the drain electrode 116, and an area in which one side of the pixel electrode 132 extends above the gate wiring 102 is an auxiliary capacitor. It becomes the denial storage capacitor (C).

In this case, a part of the gate wiring 102 functions as a first storage electrode, and the storage metal layer 120 in contact with the pixel electrode 132 functions as a second storage electrode.

As shown in the drawing, the shielding bars 106a and 106b are formed between the data line 118 and the pixel electrode 132, and the shielding bars 106a and 106b are formed on the gate line 102. And the same layer and the same material as the gate electrode 104.

At this time, the width of the shielding bars (106a, 106b) is designed to about 3㎛.

Hereinafter, the relationship between the data line, the pixel electrode, and the shield bar will be described with reference to FIG. 6.

6 is a cross- sectional view taken along the line VI-VI of FIG. 5. (This is a data wiring area of the array substrate.) (The structure of the upper substrate is shown together with the portion cut along line VI-VI of FIG. 5 above. .)

As shown in the drawing, the separation distance K between the data wiring 118 and the pixel electrode 132 having a width F of 8 µm is spaced apart by a distance of 3 µm to 5 µm according to a general design.

Unlike the conventional configuration, the shielding bars 106a and 106b designed to have a width E of about 3 μm are formed under an area corresponding to the separation distance between the data line 118 and the pixel electrode 132. The pixel electrode 132 is formed through back exposure in which mask alignment is not necessary.

Therefore, the separation distance between the pixel electrode 132 and the data wiring 118 can be configured to be constant.

With the configuration of the array substrate as described above, the black matrix 202 of the upper substrate 200 may be configured without considering the bonding margin.

That is, since the shielding bars 106a and 106b existing between the pixel electrode 132 and the data wiring 118 serve as the black matrix 202, the black matrix 202 extends to the separation distance. Not only does it need to be configured, it is not necessary to configure the width as much as the separation distance in consideration of the bonding error.

Therefore, when designing the black matrix 202, only the effects of the reflected light of the metal patterns constituting the array substrate 100 need to be considered, so that the regions corresponding to both sides of the data wiring are each 3 µm to 3 µm. It is possible to design by reducing the 5㎛.

Therefore, it is possible to obtain a result that the opening ratio is improved by the margin width.

In this case, a distance G of at most 1 μm (0.5 μm to 1 μm) exists between the shielding bars 106a and 106b and the pixel electrode 132, but the upper substrate 200 and the array substrate 100 are present. Even if the distance of 1 占 퐉 is not shielded by the black matrix 202 due to the bonding error of, it does not have a great influence on displaying an image.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to a first embodiment of the present invention will be described with reference to FIGS. 7A to 7D.

FIG. 7A to FIG. 7D are cross-sectional views illustrating the process of cutting VI-VI, VIII-VIII of FIG. 5.

As shown in FIG. 7A, one selected from the group of conductive metals including aluminum (Al), aluminum alloy, chromium (Cr), molybdenum (Mo), tungsten (W), etc. is deposited on the transparent insulating substrate 100. The gate wiring 102 and the gate electrode 104 are formed by patterning.

At the same time, the bar-shaped shielding bars 106a and 106b long in one direction are configured to be spaced apart at predetermined intervals in the region D where the data wiring is to be formed in a subsequent process.

At this time, the width of the shielding bars (106a, 106b) is designed to have a width of about 3㎛.

Next, one selected from the group of inorganic insulating materials including silicon oxide (SiO ₂ ) and silicon nitride (SiN _x ) is deposited on the entire surface of the substrate 100 on which the gate electrode 104 and the like are formed. The gate insulating film 108 is formed.

Next, pure amorphous silicon (a-Si: H) and impurity amorphous silicon (n + or p + Si: H) are stacked on the gate insulating layer 108, and then patterned to form an island-like active layer 110. The ohmic contact layer 112 is formed.

The ohmic contact layer 112 may be formed by depositing pure amorphous silicon and then doping with impurity ions.

When ion doping, the dopant can be composed of P type and N type. If dopant is doped with Group 3 elements such as B ₂ H ₆ , it is a P-type semiconductor, and Group 5 elements such as PH ₃ Doping acts as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device.

Next, as shown in FIG. 7B, chromium (Cr), copper (Cu), antimony (Sb), and tungsten (2) are formed on the entire surface of the substrate 100 on which the active layer 110 and the ohmic contact layer 112 are formed. And depositing and patterning one selected from the group of conductive metals including W) and aluminum alloy to form source and drain electrodes 114 and 116 overlapping the ohmic contact layer 112. The data line 118 that contacts and crosses the gate line 102 to define the pixel region P is formed.

At this time, the width of the data line is designed to have a width of about 8㎛.

The data wiring 118 is formed over two shielding bars 106a and 106b spaced apart from each other, so that both sides of the data wiring 118 are in planar area with the shielding bars 106a and 106b on both sides. It becomes the shape comprised overlapping.

While forming the source electrode 114 and the drain electrode 116, a storage metal layer 120 of an island is formed on a portion of the gate wiring 102.

After forming the source and drain electrodes 114 and 116 spaced apart from each other by a predetermined distance, the process of removing the ohmic contact layer 112 exposed by the spaced distance between the two electrodes is performed.

Next, as shown in FIG. 7C, an inorganic insulating material group including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 on which the source and drain electrodes 114 and 116 are formed. One selected from among them is deposited to form a protective film 122 which is a second insulating film.

Next, the passivation layer 122 is patterned to form a drain contact hole 124 exposing the drain electrode 116 and a storage contact hole 126 exposing a portion of the storage metal layer 120.

Next, one selected from the group of transparent conductive materials including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the patterned protective layer 122 to form a transparent electrode layer 132a. To form.

In the process of photo-lithography of the transparent electrode layer 132a, first, a negative photo-resist is applied to form a PR layer 128, and a back exposure during the process of exposing the PR layer. And front exposure simultaneously.

The negative PR has a characteristic that a portion to which light is not irradiated is developed by a developer.

As shown, the back exposure irradiating the light L1 from the lower part of the substrate 100 does not require a mask, but only an opaque metal layer formed on the upper part of the substrate 100, that is, the gate wiring 102 and the data. The wiring 118, the source electrode 114, the drain electrode 116, and the shielding bars 106a and 106b serve to block the mask.

Therefore, the PR layer 128 positioned at the portion where the light is blocked is developed by a developer.

In this case, the upper exposure may be performed simultaneously, because a transparent pixel electrode contacting the drain electrode 116 must be present on the drain electrode 116, and the storage capacitor C is a front gate of the storage capacitor C. This is because it is configured as a storage on gate.

In the shear gate method, the transparent electrode layer 132a must remain to the upper portion of the gate wiring 102.

Therefore, during the upper exposure, the substrate 100 includes a mask 130 including a portion of the drain electrode 116 on which the drain contact hole 124 is formed and a portion corresponding to the storage region C. The transmissive portion M is formed on the substrate 100. ) Is positioned on the upper side of the mask 130 and the light L2 is irradiated from the upper portion of the mask 130 to perform an exposure process.

Next, the PR layer 128 in which the exposure process is completed is developed to etch the exposed transparent electrode.

In this way, as shown in FIG. 7D, one side contacts the drain electrode 116 and the other side contacts the storage metal layer 120 to form a transparent pixel electrode 132 positioned in the pixel region P. FIG. can do.

In this case, the pixel electrode 132 is patterned by the back exposure using the data wiring 118 and the shielding bars 106a and 106b formed on both sides of the data wiring 118 as a mask. One side of 132 and one side of the shielding bars 106a and 106b are formed on a substantially vertical line.

The shielding bars 106a and 106b and the pixel electrode 132 have a maximum distance of 1 μm due to the diffraction effect of light during a photo-lithography process.

In this case, the separation distance between the pixel electrode 132 and the data wiring 118 is constant with respect to the entire substrate, and the separation distance is configured to have a distance of about 3 μm to 5 μm as a general design.

As described above, when the black matrix is formed on the upper substrate (not shown), since it is not necessary to consider a bonding margin of 3 μm to 5 μm unlike the related art, the opening ratio can be secured as much.

In addition, since the distance between the pixel electrode and the data wiring can be uniformly designed through the back exposure, the parasitic capacitance (C _DP ) and the parasitic capacitance generated in the liquid crystal panel due to mask misalignment when the pixel electrode is patterned The deviation ΔC _DP can be prevented from occurring.

Hereinafter, the second embodiment is a modified embodiment of the first embodiment, in which the array substrate is manufactured by changing the configuration of the shielding bar.

Second Embodiment

Unlike the first embodiment, the second embodiment of the present invention is configured to overlap the shielding bar and the pixel electrode with a predetermined area.

8 is a plan view schematically illustrating a portion of an array substrate for a liquid crystal display according to a second embodiment of the present invention.

Compared with the configuration of FIG. 5 shown in the first embodiment, only a structure in which the shielding bar overlaps with the pixel electrode is different, so a detailed description of the planar configuration will be omitted.

In the following description, the same configuration uses the same reference numerals as the configuration of FIG. 5.

As shown, the data line 118 and the shielding bars 106a and 106b are spaced apart at a maximum of 1 μm, and the shielding bars 106a and 106b and the pixel electrode 132 have a width of at most 1 μm. Overlap by H).

In this case, the distance K between the pixel electrode and the data wiring is in the range of 3 μm to 5 μm.

As described above, when designing a black matrix on the upper substrate, there is no need to consider a margin for compensating for errors caused by misalignment and mask misalignment.

Hereinafter, the relationship between the data line, the pixel electrode, and the shield bar will be described with reference to FIG. 9.

9 is a partial cross-sectional view of the liquid crystal display panel taken along the line VIII-VIII of FIG. 8.

(The area cut along the line VII-VII of FIG. 8 is a data wiring region, and together shows the configuration of the upper substrate.)

As shown in the drawing, the distance K between the data line 118 and the pixel electrode 132 is spaced apart by a distance of 3 μm to 5 μm according to a general design.

A characteristic of the second embodiment is that, unlike the first embodiment, the shielding bars 106a and 106b overlap with the pixel electrode.

At this time, there is a maximum distance of 1 μm (0.5 μm to 1 μm) between the shielding bars 106a and 106b and the data wiring 118, but this area is always shielded with a black matrix.

Therefore, when designing the black matrix 202, only the effects of the reflected light of the metal patterns constituting the array substrate 100 need to be considered, so that margins of upper and lower plate bonding misalignment of about 3 μm to 5 μm can be avoided. There is no need to consider.

Therefore, it is possible to obtain a result that the opening ratio is improved by the margin width.

In the above-described configuration, the pixel electrode 132 uses the back exposure method in the same manner as in the first embodiment. In order to pattern the pixel electrode to overlap the shielding bar through the back exposure method, the pixel electrode 132 is manufactured by the following process. do.

Hereinafter, a manufacturing process of an array substrate for a liquid crystal display device according to a second embodiment of the present invention will be described with reference to FIGS. 10A to 10C.

(The process sequence is the same as that of the first embodiment. Therefore, in the second embodiment, only the process of the data wiring area, which is the core of the present invention, will be described.)

10A to 10C are diagrams It is a process sectional drawing which cut | disconnects along VII-VII of 8, and shows it according to a process sequence.

First, as shown in FIG. 10A, the gate electrode (not shown), the gate wiring (not shown), and the shielding bars 106a and 106b are formed on the substrate 100 during the array substrate process according to the present invention. A gate insulating film 108 is formed as a first insulating film, and data wirings 118 are formed in a region between the shielding bars 106a and 106b on the gate insulating film 108.

In this case, shielding bars 106a and 106b formed at both sides of the data line 118 are spaced apart from the data line 118 at a distance of at most 1 μm.

Next, a protective film 122 which is a second insulating film is deposited by depositing one selected from the group of inorganic insulating materials including silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ) on the entire surface of the substrate 100 including the data line 118. ).

Next, a transparent one of the transparent conductive metal group including indium-tin-oxide and indium-zinc-oxide is deposited on the passivation layer 122 to make it transparent. The electrode layer 132a is formed.

Next, a PR layer 128 is formed by applying a negative type photo-resist (hereinafter, referred to as “PR”) on the transparent electrode layer 132a.

Next, as described above in the first embodiment, a mask (not shown) is placed on the substrate 100 and the upper exposure and the back exposure are simultaneously performed. The data wiring 118 region is affected by the back exposure. Only the back exposure process will be described.

As shown, unlike the first embodiment, exposure is performed by varying the angle of light.

That is, when the horizontal direction is called the x-axis and the vertical direction is the y-axis, when the light L1 is irradiated with a predetermined angle to the left with respect to the y-axis, the PR layer on the substrate is as shown. It is exposed along the inclined dotted lines Q1 and Q2.

Accordingly, the portion of the exposure area (transparent area), which is exposed along the dotted line Q1 on one side of the data line 118, occupies the PR area R1 located above a part of the shielding bar 106b. Include.

Therefore, in this part, since PR is not removed during the process of developing the PR layer 128, the transparent electrode 132a beneath it remains.

Next, as shown in FIG. 10B, light is irradiated with a tilt as opposed to the case of FIG. 10A.

When the horizontal direction is referred to as the x-axis and the vertical direction is referred to as the y-axis, when the light is irradiated at a predetermined angle to the right with respect to the y-axis, the PR layer on the upper part of the substrate is inclined by the dotted line (as shown). It is exposed along Q3, Q4).

Accordingly, when light is irradiated, a portion of the exposure area (transparent area) occupied by the exposed area along the dotted line Q ₃ on one side of the data line, in particular, is a PR area located above a part of the shielding bar 106a. (R2).

Therefore, in this part, since the PR layer is not removed during the process of developing the PR, the lower transparent electrode remains.

Therefore, after the exposure process of FIGS. 10A and 10B is completed and the PR layer 128 is developed, the PR layer remains on the pixel region and a part of the shielding bars 106a and 106b. You can get the result.

When the metal layer exposed between the patterned PR layers is etched, as shown in FIG. 10C, the width H of the overlapped area of the pixel electrode 132 and the shielding bars 106a and 106b is 1 μm at the maximum. Configure to

The overlapping area of the pixel electrode 132 and the shielding bars 106a and 106b may be controlled by adjusting the irradiation angle of the light when the light is irradiated.

Through the above-described first and second embodiments, an array substrate for a liquid crystal display device according to the present invention can be manufactured, and the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the spirit of the present invention. And variations are possible.

By introducing the present invention as described above, manufacturing an array substrate for a liquid crystal display device has the following effects.

First, since a separate shielding bar is formed under the spaced area between the data wiring and the pixel electrode of the lower substrate of the liquid crystal panel, when the black matrix of the upper substrate is designed, the separation even when a bonding error occurs. There is no need to set the margin as much as distance.

Therefore, there is an effect of improving the aperture ratio of the liquid crystal panel.

Second, since the photolithography process of etching the pixel electrode performs a back exposure process, the separation distance between the data line and the pixel electrode is constant for the entire liquid crystal panel.

Therefore, since the change in parasitic capacitance ΔC _DP does not appear for the entire liquid crystal panel with respect to the change in the separation distance, there is an effect of preventing distortion of the pixel voltage applied to the pixel electrode.

The liquid crystal panel of the image quality described by the above effect can be produced.

Claims (8)

Preparing a substrate; Defining a region where a gate wiring and a data wiring are to be formed on the substrate; Forming a plurality of gate wirings formed in one direction on the substrate in the gate wiring region, and two shielding bars formed in one direction in the region where the data wiring is to be formed and spaced apart from each other by a predetermined distance; Forming a gate insulating film, which is a first insulating film, on the substrate including the gate wiring and the shielding bar; Defining a pixel area on the gate insulating layer to perpendicularly intersect the gate line, and forming a data line on the two shielding bars; Forming a protective film, which is a second insulating film, on the entire surface of the substrate on which the gate wiring, the data wiring, and the thin film transistor are formed; Forming a transparent electrode layer on the passivation layer, and coating a negative photoresist on the transparent electrode layer to form a photoresist layer; Placing a mask formed of a transmissive portion on a portion of the thin film transistor and a portion of a gate wiring defining the pixel region on the substrate on which the photoresist layer is formed, and irradiating light from the upper and lower portions of the substrate; Wow; After developing the photoresist layer exposed by the irradiated light, the exposed transparent electrode layer is etched to etch the pixel electrode positioned on the pixel region and partially in contact with the thin film transistor and partially extending over the gate wiring. Forming steps Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 1, The thin film transistor is a liquid crystal display device array substrate manufacturing method comprising a gate electrode, an active layer, a source electrode and a drain electrode. The method according to any one of claims 1 to 2, And the pixel electrode is in contact with the drain electrode. The method of claim 1, And a pixel electrode and a shielding bar spaced apart from each other by a predetermined distance, and the shielding bar and the data wiring overlap a predetermined area. The method of claim 4, wherein A method of manufacturing an array substrate for a liquid crystal display device, wherein the width of the overlapping area between the data line and the shielding bar is 1 μm. The method of claim 1, And a pixel electrode and a shielding bar overlapping a predetermined area, and the data wiring and the shielding bar are spaced a predetermined distance apart. The method of claim 6, And a width of the overlapping area between the shielding bar and the pixel electrode is 1 μm. The method of claim 1, The shielding bar has a width of 3㎛ array substrate manufacturing method for a liquid crystal display device.