KR20030024862A - Method to descramble the data mapping in memory circuits - Google Patents

Abstract

The method for automatically generating a logical hardware test pattern in a memory circuit is based on a given physical pattern. The method of the present invention includes inverse transformation from a given set of logical data patterns. Since the method of the present invention is performed automatically, no information on data scrambling inside the memory circuit is required.

Description

METHOD TO DESCRAMBLE THE DATA MAPPING IN MEMORY CIRCUITS}

In memory circuits (eg, static random access memory (SRAM), dynamic random access memory (DRAM, etc.), data is generally stored in a matrix of memory elements. The data values of the memory device may be exclusively modified (write operation) or accessed (read operation) using the interface of the memory circuit. During the read command, an address is provided to this interface. This address is then processed by the memory circuit, and the data located at this address is passed to the data output. In contrast, the write command stores externally provided data at the address provided with the data.

Therefore, the memory circuit performs two kinds of memory addressing. One address describes the physical location (called "physical address") of the storage element. Another address is an address (called a "logical address") that must be provided to the interface of the memory circuit to access a particular storage element. In previous generations of memory, the relationship between physical and logical addresses was simple, meaning that two parts of the logical address (typically called rows and columns) are the x and y coordinates of the storage element (i.e. physical Because it has a transparent relationship to the address).

However, recent structures of memory circuits have gradually hampered the extraction of transparent mapping relationships between logical and physical addresses. Non-trivial mapping is summarized under the term "data scrambling". In general, data scrambling can occur for several reasons, including the following:

-Twisted bit line.

Word line addressing and segmentation.

Layout mirroring.

Multiplexing and de-multiplexing of the data package in burst mode.

Wrap type dependency (interleaving vs. sequential).

The combination of these data scrambling makes it nearly impossible to extract the logical address for a given physical address. However, this is a prerequisite for hardware testing because the storage elements of the memory matrix are only accessed through the interface of the memory circuits. In particular, some characteristic physical data patterns, such as stripes, checker boards, blankets, etc., are performed on memory matrices to identify problems caused by coupling and substrate noise. In addition, the hardware test must be able to extract the physical location of the fault when the data on the logical interface is wrong.

Given the size of current memory circuits, it is clear that the generation and analysis of test patterns should be performed automatically. However, because the development of underlying generation algorithms is hindered by data scrambling, the pattern generation techniques currently used (based on procedural programming) are insufficient.

The present invention relates generally to a method of addressing in a memory circuit, and more particularly, to a method of simplifying the testing of a memory circuit by overcoming the mapping problem between physical and logical data patterns (ie, data scrambling).

The above described and other objects, aspects and advantages can be well understood from the detailed description of the preferred embodiment of the present invention with reference to the following drawings.

1 is a block diagram illustrating a data flow for generating a physical array data pattern and converting it to a logical data pattern for testing and analyzing a MOS memory array in accordance with the present invention.

2 illustrates a method of inputting a known physical data pattern into the layout of an array through a data mapping technique in accordance with the present invention.

3 is a flow diagram illustrating logic for generating a logical data pattern from a known physical data pattern.

It is an object of the present invention to provide an automatic pattern generation and analysis method for performing a hardware test of a memory circuit.

According to the present invention, automatic generation of logical hardware test patterns is provided based on a given physical pattern. The method of the present invention includes inverse transformation from a given set of logical data patterns. Since the method is performed automatically, it does not require information about data scrambling inside the memory circuit.

Implementations of the invention require the following elements:

A pattern viewer and generator representing a graphical user interface (GUI), which enables the graphical definition of values stored in memory elements. It also provides a library with a predetermined standard pattern, such as a checker board. In addition to the definition of the pattern, the module also allows you to view the patterns stored in the memory circuit.

Layout of the memory matrix (or array). This part is extracted from the memory design. Basically, this gives the geometric location (ie x and y coordinates) of each storage element.

A flattened array netlist (typically created by the layout versus schematic tool) carries a link between the hierarchical name of each storage element and its geometric location. .

A hierarchical netlist of memory circuits performed by the logic simulator.

The logic simulator performs read and write commands on the netlist to model the operation of the memory circuit. It also provides the ability to set initial conditions on a circuit node (such as the voltage of a storage element) before the simulation begins. Similarly, the ability to read the final condition of the circuit node at the end of the simulation is supported.

The pattern server (and / or tester RAM) serves as an intermediate store between the hardware tester and the logic simulator. Data is exchanged in address and data pairs, simply describing the data values stored at a particular logical address.

The hardware tester generates and measures electrical signals at the pins of the memory device.

The bitmap analyzer can compare physical data patterns. Mismatch between the input pattern and the extracted pattern can be analyzed.

Referring to the drawings, in particular with reference to FIG. 1, a data flow of pattern generation and pattern analysis of the present invention is shown in a block diagram. The pattern viewer and generator 10 provides a graphical user interface (GUI), which allows the user 3 to view the input and stored data patterns of the data patterns. This interface allows the user to enter and view data through a graphical definition of the values stored in the memory array. It also stores a library with predetermined standard patterns such as checker board patterns, stripe patterns, random patterns, blanket patterns, and the like. The data pattern can be in the form of a table with rows and columns such as those of the memory allocation to be tested.

The layout 11 of the memory array is made by software or an operator in step 100, and creates a physical design of the memory array using conventional layout tools. The resulting memory array physical layout generally includes many levels and shapes used to create a mask for fabricating the memory array.

Each cell of the memory array physical layout 11 is mapped using predetermined data from a table stored in the pattern generator module 10. The mapping technique is via software that automatically writes data "1" or "0" to each cell in the array through step 101.

Data mapping from the pattern generator 10 to the physical layout 11 is shown in detail in FIG. 2. For example, checker board patterns from a library are loaded into the pattern generator. A software program is used to perform one-to-one data mapping from the pattern viewer to the physical layout. When data mapping is complete, the physical layout module will ensure that all cells have a checker board data pattern.

The data pattern stored in the layout 11 is sent to the input deck 12A in step 102 to define the initial condition of each cell of the array. Each initial condition includes an entire cell address path indicating its value and the logical location of the cell. The data flow process 102 is accomplished using a Layout Versus Schematic (LVS) tool known to those skilled in the art.

Existing LVS software can perform cross-reference checks on the wiring schematics of the circuit layout. The purpose of the LVS check is to assess the degree of agreement with the wiring schematics of the layout. This tool is stored in an array of layouts and can be modified to send a data pattern to the input deck that lists the cell's initial conditions. For example, data stored in an array of physical layouts can be converted into a flattened form with all the hierarchical paths of each cell, where the hierarchical paths can be found at any path, any subarray, at any row and column address. Indicates if it is located. After mapping is done by software, all initial conditions of all cells with known data patterns are passed to input deck 12A. More specifically, all physical data patterns are now recorded with the deck's initial conditions and ready for simulation. These initial conditions are entered into the simulator 13 in step 103.

In order to perform the simulation, a netlist 5 is generated from the memory circuit wiring diagram 4 in step 97, which is done using existing software for that purpose. For example, a Cadence tool can be used to generate a netlist from the wiring schematic. Examples of netlists and input decks generated by the cadence tool for a simple circuit are described below.

Input deck

Stimulus:

vvintvint! gnd! DC vint

Vclockclockgnd! Pulse 0 vint 0n 1n 1n 5n 10n

VRASRASgnd! Pwl 0 vint 10n vint 11n 0V 20n 0V 21n vint

VCASCASgnd! Pwl 0 vint 30n vint 31n 0V 40n 0V 41n vint

VWEWEgnd! Pwl 0 vint 30n vint 31n 0V 40n 0V 41n vint

.........

Initial Condition:

.ic v (xBank <1> .xBlock <1> .xCell <0000> .vCell) = 0

.ic v (xBank <1> .xBlock <1> .xCell <0001> .vCell) = vint

.ic v (xBank <1> .xBlock <1> .xCell <0002> .vCell) = 0

.ic v (xBank <1> .xBlock <1> .xCell <0003> .vCell) = vint

.........

Run Control Parameters

.TRAN 0.1n 1u

Netlist

***************************

* GLOBAL Net Declarations

***************************

.global GND!

***************************

* Main Circuit Netlist:

*

Block: LP_SRAM-schematic

* Library: hsu_sonic

* Last Time Saved: Sep 12 10:53:53 2000

****************************

mT6VsupplySWnet025 GND! HVTNFET w = '1.000u' | = '120.000n'

res_0net025net027r-'. 1'

vfanout_0net027 net037 DC = 0 * Fanout

fanout_0net027 gnd! vfanout_0 '25.000K-1' * Fanout

cap_0VsupplyGND! c = '1.000p'

mT3 highlow net037 net037 PFET w = '170.000n' | = '140.000n'

mT2lowhigh net037 net037 PFET w = '170.000n' | = '140.000n'

mT1highlow GND! GND! NFET w = '230.000n' | = '120.000n'

mT0lowhigh GND! GND! NFET w = '230.000n' | = '120.000n'

.probe tran v (SW)

.probe tran v (Vsupply)

.probe tran v (net037)

.probe tran v (net025)

.probe tran v (high)

.probe tran v (net027)

.probe tran v (low)

Thus, the netlist is a circuit wiring schematic compiled into a character form that the simulator 13 can recognize in step 96 and provided to the simulator 13.

However, in order to read the data stored in the memory array, the memory array must be preloaded with a known data pattern. The initial condition stored in the input will cause the simulator 13 to load the data into an array. This is done by providing an initial condition to be preloaded into the array. If the array is preloaded with a known data pattern, the simulator 13 may perform an array read simulation. Existing logic simulators 13, for example Starsim, Powermill, VHDL or Verilog, can be used for array read simulation.

In summary, as shown in FIG. 3, the modified LVS tool extracts initial data values from the arrangement layout 31. Then, by merging the netlist and the initial condition 32, the logic simulator 33 tool can perform a full array read simulation of the memory array 34. Each read cell data having a logical address from the array is stored in the pattern server 14.

The pattern server 14 serves as an intermediate reservoir between the hardware tester 15 and the simulator 13. The data stored in the pattern server 14 includes two fields: address and data value, which describe the data value stored at a particular logical address. A first embodiment of the present invention for converting a known physical array data pattern into a corresponding logical data pattern is completed. The logical data pattern may be in the form of a bitmap or a table.

The process of testing a memory array using known physical data patterns

In step 106, the information stored in the pattern server 14 is input to the tester, which uses the information including the logical address to process the DRAM array on the wafer hardware 16 (e.g., memory chips on the wafer). Program and write data values to each cell. After the array has been programmed and a period of time has passed, the data is read by the tester at step 206. The result from the hardware tester 15 generates a read address and measures the electrical signal of the cell located at those addresses. The address is then stored in pattern server 14 in the form of a logical bitmap at step 205. This logical bitmap from the tester can be compared to the logical bitmap generated in step 105 and used to program the data into hardware 16 to detect defects. However, this will not give information of the physical location fault bit. Therefore, this logical bitmap measured from hardware must be continuously converted to a physical bitmap so that the defect location in the array can be determined.

In step 205 the logical bitmap is output from the hardware tester 15 to the pattern server 14, in step 204 it is converted into a stimulus 17 form for write simulation, and the stimulus 17 is output to the simulator 13 in step 207. The same simulator 13 and netlist 5 may be used to write the logical data pattern to the memory array and generate an output deck 12B at step 203. The data stored in the output deck has a physical address similar to that of the input deck 12A described above. The data stored in output deck 12B is transferred to layout 11 at step 202 using the same modified LVS tool, but in the reverse direction.

In step 201, a simple software program similar to that described above in step 101 is used to map the pattern viewer and generator 10 into a physical bitmap or table form. Read data from the hardware is now shown to the user 3.

In step 99 the bitmap analyzer 9 interacts with the pattern viewer and generator 10, and in step 98, the physics between the original input pattern and the pattern read from the hardware using the matching function 8. You can compare data patterns. Inconsistencies between the input pattern and the tested pattern can be displayed and analyzed.

Based on this structure, the characteristics of the manufactured memory circuit can be easily checked regardless of which data scrambling is used. First, the user of the method of the present invention selects the physical data pattern to be applied to the memory chip using the GUI of the pattern viewer and generator 10. Then, the physical map of the data is converted into an initial condition to the logic simulator 13 for the corresponding storage element in the netlist using the flattened netlist 5 and the circuit layout module 11. After assigning the initial conditions, a simulation is performed to read the memory applying all possible addresses for the memory model. As a result, a set of (address, data) pairs representing a logical data pattern corresponding to the initial physical data pattern is obtained. The contents of this look-up table are written to the actual memory hardware using the hardware tester 15. After writing to the memory hardware is complete and a certain wait time has elapsed, the tester reads the memory by applying all possible addresses. These results are stored as (address, data) pairs in the pattern server 14. The latency is generally less than the retention time of the memory cell. During this wait time, some cells may malfunction due to certain types of defects. If the wait time is greater than the designed cell hold time, most of the cells will be defective. The latency can vary from 0 ms to 100 ms. This test is commonly used to determine cell retention time.

At this point it is possible to identify the logical address of the fault by comparing (address, data) pairs of write and read operations. However, to determine the physical location of the defect, data scrambling must be reversed again. Thus, the extracted (address, data) pairs during the read operation from the actual hardware are written to the array using the simulation model.

At the end of the simulation, the contents of all storage elements are extracted directly from the hierarchical cross-section netlist 5. These values are mapped to their physical locations using the flattened netlist and memory layout module 11. Finally, the resulting physical data pattern is displayed by the pattern viewer and generator 10. In addition, a bitmap analyzer 9 can be used to compare the initial physical pattern and the extracted pattern to display areas with bit defects.

The method of the present invention is useful when the memory circuit uses complex data scrambling. In particular, it helps in circuit testing where hardware defects must be placed in the layout. Since the method of the present invention eliminates the need for any manual analysis, it will significantly speed up the development of hardware test patterns. This can be used as a black box tool in a test environment where the only interface to the user is a graphical pattern generator and viewer. Inside this interface, test technicians can visually set up and analyze test patterns regardless of the data scrambling used. From the designer's point of view, this method assists in associating physical data patterns with logical data patterns, thus supporting the evaluation of data scrambling.

While the invention has been described by one preferred embodiment, those skilled in the art will recognize that the invention may be modified within the spirit and scope of the appended claims.

Claims (12)

A method of generating a logical hardware test pattern in a memory array circuit, Generating a graphical user interface (GUI) that enables a visual definition of values stored in a memory element of a memory circuit and displays a pattern stored in the memory circuit, Providing a geometric location of each storage element of said memory circuit, Providing a link between the hierarchical name of each storage element and its geometric location, Providing a hierarchical representation of said memory arrangement circuitry in the form of a netlist that can be performed by a logic simulator, Modeling the operation of the memory circuit in a logic simulator by performing read and write commands on the netlist, Providing intermediate storage between a hardware tester and the logic simulator, where data is exchanged with a pair of address and data describing the data value stored at a particular logical address; Generating and measuring an electrical signal at a pin of the memory circuit by the hardware tester. Way. The method of claim 1, Generating the graphical user interface may include manual input of data patterns. Way. The method of claim 1, Generating the graphical user interface may include selecting a predetermined data pattern. Way. The method of claim 3, wherein The predetermined data pattern is selected from the group consisting of a checker board pattern, a stripe pattern, a random pattern and a blanket pattern. Way. The method of claim 1, Providing the geometric location of each storage element of the memory circuit is performed by a mapping technique that automatically writes data "1" or "0" in each cell of the array. Way. The method of claim 1, Providing a link between the hierarchical name of each storage element and its geometric location is performed using a layout versus schematic (LVS) tool. Way. The method of claim 1, Providing a hierarchical representation of the memory array circuitry in the form of a netlist is performed by compiling circuit wiring schematics into a test form that the simulator can identify. Way. The method of claim 1, Outputting a logical bitmap generated from the measured electrical signal, Converting the logical bitmap into a stimulus for the logic simulator and generating a physical address corresponding to the logical bitmap; Mapping a physical bitmap for display in the graphical user interface, and allowing a user to view and analyze inconsistencies between an input physical pattern and the tested physical pattern. Way. The method of claim 8, Automatically analyzing a difference between the input logic pattern and the tested logic pattern; Way. In a system for automatic pattern generation and analysis used to test memory array circuits, A pattern viewer and generator that displays a graphical user interface (GUI) that enables visual definition of values stored in memory elements of the memory array circuitry and displays patterns stored in the memory array circuitry, A layout of the memory array extracted from the design of the memory array circuit providing the geometric location of each storage element, Flattened array netlist, created by layout versus schematic (LVS) tools, providing a hierarchical name for each storage element and its geometric location, Hierarchical representation of a memory array circuit in the form of a netlist executable by a logic simulator, A logic simulator executing read and write instructions on the netlist, setting initial conditions on a circuit node, and reading the final condition of the circuit node at the end of the simulation to model the operation of the memory array circuit, A pattern server acting as an intermediate repository between the hardware tester and the logic simulator, where data is exchanged with address and data pairs describing data values stored at a particular logical address, A hardware tester for generating and measuring an electrical signal at a pin of a memory array circuit after a predetermined time after the known data in the array is programmed, A bitmap analyzer that compares physical data patterns to analyze discrepancies between input patterns and extracted patterns system. The method of claim 10, The predetermined time is less than the designed cell hold time system. The method of claim 10, The predetermined time varies from 0 ms to 100 ms to determine the cell hold time. system.