KR20030049352A - Method of manufacturing a semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a semiconductor device, comprising: forming an isolation film on a semiconductor substrate separated into a high voltage device region and a low voltage device region; Forming a first gate oxide film and a first polysilicon layer on the high voltage device region; Forming a second gate oxide film and a second polysilicon layer on the entire structure; Performing a predetermined etching process to form a first gate electrode on the low voltage device region, and forming a second gate electrode on the high voltage device region; And forming a source / drain region in the semiconductor substrate on both sides of the first and second gate electrodes.

Description

Method of manufacturing a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a dual gate oxide using a high dielectric material.

Thermal oxide film and rapid thermally grown SiO ₂ are used as gate oxide films of CMOS (Complementary Metal-Oxide-Semiconductor) currently in mass production in semiconductor devices. In recent years, as the design rule decreases, the thickness of the gate oxide film has decreased to 25 to 30 GPa or less, which is a limit of direct tunneling of the silicon oxide film, and in 0.10 탆 technology, the gate oxide film is used as a gate oxide film. A thickness of 10 to 15 mm 3 is expected.

However, when the thickness of the gate oxide film is reduced due to high integration, static power consumption of the device is increased due to an increase in off currennt due to direct tunneling, thereby adversely affecting device operation. Accordingly, in recent years, studies have been actively conducted to employ high-k dielectric materials (eg, ZrO ₂ , HfO ₂ , Al ₂ O ₃ , TiO _2, etc.) as gate oxide films.

1A to 1F are cross-sectional views illustrating a method of forming a dual gate oxide film according to the prior art.

Referring to FIG. 1A, a semiconductor device is generally driven by receiving a high voltage or a low voltage from an external source, and is divided into a high voltage device driven at a high voltage and a low voltage device driven at a low voltage. Accordingly, the semiconductor substrate 10 is divided into a region in which a high voltage element is formed (high voltage element region) and a region in which a low voltage element is formed (low voltage element region) in order to simultaneously implement a high voltage element and a low voltage element. Determined at circuit design time.

The device isolation layer 12 is formed by performing a shallow trench isolation (STI) process using an isolation (ISO) mask on the semiconductor substrate 10 defined as the high voltage device region and the low voltage device region. In this case, the semiconductor substrate 10 is divided into an active region and an inactive region (ie, an isolation layer region). Subsequently, a well ion implantation process using a well ion implantation mask is performed on the entire structure to form the well region 14 in the active region of the semiconductor substrate 10.

1B and 1C, a thermal oxidation process is performed on the entire structure to form a first gate oxide film 16 having a thick thickness among the dual gate oxide films. Subsequently, after the photoresist is deposited on the entire structure, an exposure process using a photo mask is performed to form the photoresist pattern 18 to open the low voltage device region. Subsequently, an etching process using the photoresist pattern 18 as a mask is performed to pattern the first gate oxide film 16 to form the first gate oxide film 16 only on the active region of the high voltage device region.

Referring to FIG. 1D, a predetermined photoresist strip process is performed to remove the photoresist pattern 18 to form a second gate oxide film 20 having a thin thickness among the dual gate oxide films only on the active region of the low voltage device region. Next, the polysilicon layer 22 for gate electrodes is formed on the whole structure.

Referring to FIG. 1E, the polysilicon layer 22 and the first gate oxide layer 16, the polysilicon layer 22, and the second gate oxide layer 20 may be sequentially subjected to an etching process using a mask for a gate electrode pattern. The first gate electrode 24 for the high voltage device is formed on the active region of the high voltage device region, and the second gate electrode 26 for the low voltage device is formed on the active region of the low voltage device region. As a result, a dual gate electrode including the first gate electrode 24 and the second gate electrode 26 is formed.

Referring to FIG. 1F, a low concentration ion implantation process (P ⁻ or N ⁻ ) 28 is formed by performing a low concentration ion implantation process to form a shallow junction in the active region of the semiconductor substrate 10. At this time, the first and second gate electrodes 24 and 26 are doped with predetermined ions by a low concentration ion implantation process.

Subsequently, predetermined deposition and etching processes are sequentially performed to form spacers 30 for lightly doped drain (LDD) high temperature low pressure dielectric (HLD) on sidewalls of the first and second gate electrodes 24 and 26. . Subsequently, a high concentration ion implantation process is performed to form a high concentration junction region (P ⁺ or N ⁺ ) 32 and then a heat treatment process is performed to form the high concentration junction region 32 and the first and second gate electrodes 24 and 26. A self align silicide (SALICIDE) 34 is formed on the top.

As described above, in the prior art, when the dual gate oxide film is formed, the thick first gate oxide film is first formed, and then only the oxidation time is changed through the mask process to form the second gate oxide film having a thin thickness. Doing. However, such a technique cannot secure stable process margins as semiconductor circuits are highly integrated, and technologies are developed to significantly reduce the size of the gate oxide film. In addition, problems such as direct tunneling of the gate oxide film, ion penetration, increase of leakage current, and deterioration of device reliability may occur, which may cause a big problem in device characteristics. As a result, the semiconductor device manufacturing process may be adversely affected.

Accordingly, the present invention has been made to solve the above problems, by forming a gate oxide film of a high voltage device using a high-k dielectric material, and forming an insulating film between the gate oxide film and the polysilicon layer for the gate electrode of the polysilicon layer It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing interfacial properties and defects and improving device reliability.

In addition, the present invention is to manufacture a semiconductor device capable of realizing a dual gate oxide film having different characteristics by forming a gate oxide film of a high voltage device using a high-k dielectric material, and forming a gate oxide film of a low voltage device by a thermal oxidation process Another purpose is to provide a method.

1A to 1F are cross-sectional views of a semiconductor device shown for explaining a conventional method of manufacturing a semiconductor device.

2A to 2I are cross-sectional views of a semiconductor device for explaining the method of manufacturing the semiconductor device according to the embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100: semiconductor substrate 12, 102: device isolation film

14, 104: Well region 16, 106: First gate oxide film

20, 116: second gate oxide film 22: polysilicon layer

24, 122: first gate electrode 26, 124: second gate electrode

28, 126: low concentration junction region 30, 128: spacer

32, 130: high concentration junction region 34, 132: salicide

108: first insulating film 114: second insulating film

110: first polysilicon layer 118: second polysilicon layer

18, 112, 120: photoresist pattern

In order to achieve the above object, the present invention comprises the steps of forming an isolation layer on a semiconductor substrate separated into a high voltage element region and a low voltage element region; Forming a first gate oxide film and a first polysilicon layer on the high voltage device region; Forming a second gate oxide film and a second polysilicon layer on the entire structure; Performing a predetermined etching process to form a first gate electrode on the low voltage device region, and forming a second gate electrode on the high voltage device region; And forming a source / drain region in the semiconductor substrate on both sides of the first and second gate electrodes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views of a semiconductor device for explaining a method of forming a gate oxide film according to an embodiment of the present invention.

Referring to FIG. 2A, a device isolation layer 102 is formed by performing a shallow trench isolation (STI) process using an isolation (ISO) mask on a semiconductor substrate 100 defined as a high voltage device region and a low voltage device region. In this case, the semiconductor substrate 100 is divided into an active region and an inactive region (ie, an isolation layer region). Subsequently, a well ion implantation process using a well ion implantation mask is performed on the entire structure to form the well region 104 in the active region of the semiconductor substrate 100.

Referring to FIG. 2B, a thick first gate oxide layer 106 is formed in the dual gate oxide layer using a high dielectric material layer over the entire structure. In this case, any one of ZrO ₂ , HfO ₂ , Al ₂ O ₃ , and TiO ₂ may be used as the high dielectric material layer. Subsequently, the first insulating film 108 is formed on the first gate oxide film 106 in consideration of the interface characteristics and the defect prevention with the first polysilicon layer formed by a subsequent process.

2C and 2D, a first polysilicon layer 110 for a gate electrode of a high voltage device is formed on the entire structure. Subsequently, after the photoresist is deposited on the entire structure, an exposure process using a photo mask is performed to form the first photoresist pattern 112 to open the low voltage device region. Subsequently, an etching process using the first photoresist pattern 112 as a mask is performed to pattern the first polysilicon layer 110, the first insulating layer 108, and the first gate oxide layer 106 to activate the high voltage device region. The first polysilicon layer 110, the first insulating layer 108, and the first gate oxide layer 106 patterned only on the region are sequentially formed.

Referring to FIG. 2E, a second photoresist layer is formed on the first polysilicon layer 110 by performing a predetermined photoresist strip process to remove the first photoresist pattern 112 and performing a thermal oxidation process on the entire structure. While forming 114, a second gate oxide film 116 having a small thickness among the dual gate oxide films is formed on the active region of the low voltage device region.

2F and 2G, the second polysilicon layer 118 for the gate electrode of the low voltage device is formed on the entire structure. Subsequently, after the photoresist is deposited on the entire structure, an exposure process using a photomask is performed to form a second photoresist pattern 120 for forming a final dual gate electrode.

Referring to FIG. 2H, a second polysilicon layer 118, a second insulating layer 114, and a first polysilicon layer formed in the high voltage device region by performing an etching process using the second photoresist pattern 120 as a mask. 110, the first insulating layer 108 and the first gate insulating layer 106 are sequentially etched, and the second polysilicon layer 118 and the second gate insulating layer 116 formed in the low voltage device region are sequentially etched. Subsequently, the second photoresist pattern 120 is removed by the photoresist strip process to form the second gate electrode 124 of the low voltage device on the low voltage device region.

Subsequently, after forming a third photoresist pattern (not shown) to open the high voltage device region, an etching process is performed to sequentially form the second polysilicon layer 118 and the second insulating layer 114 formed on the high voltage device region. It removes and forms the 1st gate electrode 122 of a high voltage element.

Referring to FIG. 2I, a low concentration ion implantation process (P ⁻ or N ⁻ ) 126 is formed by performing a low concentration ion implantation process to form a shallow junction in the active region of the semiconductor substrate 100. In this case, the first and second gate electrodes 122 and 124 are doped with predetermined ions by a low concentration ion implantation process.

Subsequently, predetermined deposition and etching processes are sequentially performed to form spacers 128 for lightly doped drain (LDD) high temperature low pressure dielectric (HLD) on sidewalls of the first and second gate electrodes 122 and 124. . Subsequently, a high concentration ion implantation process is performed to form a high concentration junction region (P ⁺ or N ⁺ ) 130 and then a heat treatment process is performed to form the high concentration junction region 130 and the first and second gate electrodes 122 and 124. A self align silicide (SALICIDE) 132 is formed on the top.

The present invention forms a gate oxide film of a high voltage device using a high-k dielectric material, and forms an insulating film between the gate oxide film and the polysilicon layer for the gate electrode, thereby preventing interfacial characteristics and defects of the polysilicon layer, as well as reliability of the device. Can improve.

In addition, the present invention may implement a dual gate oxide film having different characteristics by forming a gate oxide film of a high voltage device using a high-k dielectric material and forming a gate oxide film of a low voltage device by performing a thermal oxidation process.

Claims (9)

Forming an isolation layer on the semiconductor substrate which is divided into a high voltage device region and a low voltage device region; Forming a first gate oxide film and a first polysilicon layer on the high voltage device region; Forming a second gate oxide film and a second polysilicon layer on the entire structure; Performing a predetermined etching process to form a first gate electrode on the low voltage device region, and forming a second gate electrode on the high voltage device region; And Forming a source / drain region in the semiconductor substrate on both sides of the first and second gate electrodes. The method of claim 1, And the gate oxide film is formed of a high dielectric material layer. The method of claim 2, The high dielectric material layer is a method of manufacturing a semiconductor device, characterized in that any one of the material of ZrO ₂ , HfO ₂ , Al ₂ O ₃ , TiO ₂ . The method of claim 1, And forming an insulating film between the first gate oxide film and the first polysilicon layer. The method of claim 1, And the second gate oxide film is formed by a thermal oxidation process. The method of claim 1, And the first gate electrode is formed of the second insulating film and the second polysilicon layer. The method of claim 1, And the second gate electrode is formed of the first insulating film and the first polysilicon layer. The method of claim 1, Forming the source / drain regions may include forming a low concentration junction region in the semiconductor substrate on both sides of the first and second gate electrodes; Forming spacers on both sidewalls of the first and second gate electrodes; And Forming a high concentration junction region on the low concentration junction region using the spacer as a mask. The method of claim 1, And forming a salicide layer on the source / drain regions and the first and second gate electrodes by performing a heat treatment process after forming the source / drain regions.