KR20030050999A - Flash eeprom and method for fabricating the same - Google Patents

Abstract

The present invention discloses a flash ypyrom and a method of manufacturing the same. The disclosed flash ypyrom includes: a silicon substrate having recesses having a predetermined depth; A source region formed in the bottom portion of the groove and a substrate portion on the side thereof, and a drain region formed in the side substrate surface on the upper portion of the groove; A tunnel oxide film formed on a surface of the groove and a source / drain region at different thicknesses; A floating gate formed on the tunnel oxide film on the inner wall of the groove; A control gate insulating film formed on the floating gate and the tunnel oxide film; A control gate formed to bury the recess; A control gate electrode formed on the control gate; An isolation layer surrounding the recess and formed at the same height as the control gate electrode; A word line formed on the control gate electrode and a device isolation layer adjacent thereto; A planarization layer formed on the word line and the device isolation layer; A source line contact plug and a bit line contact plug formed in the planarization layer and the device isolation layer to be in contact with the source region and the drain region, respectively; And a bit line and a source line formed to contact the source line contact plug and the bit line contact plug on the planarization layer, respectively.

Description

FLASH EEPROM AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a flash ypyrom, and more particularly, to a flash ypyrom formed vertically in the groove and a manufacturing method thereof.

Flash EEPROM (Erasable Programmable Read-Only Memory) and Programmable Eras (EPROM) and Programmable Eraser (EPROM) are electrically programmed and erased as systems become smaller, lighter and more portable. It is one of the non-volatile memory devices manufactured by taking advantage of the electrically erasable programmable ROM (EEPROM).

This flash Y pyrom realizes a bit storage state as one transistor, and electrically performs program and erase operations. Here, "flash" implies that the entire memory block or large block is erased at the same time during the erase operation.

In such flash Y pyrom, program and erase are performed using a 12V / 5V power supply. In particular, the program operation uses hot electrons by an external high voltage, and the erase operation is FN (Fowler-Nordheim). ) Tunneling is used.

1 is a cross-sectional view of a flash Y pyrom cell prepared according to the prior art.

As shown, the flash Y pyrom cell has a structure in which the floating gate 3 and the control gate 5 are largely stacked, and a thin tunnel oxide film 2 is interposed between the substrate 1 and the floating gate 3. The control gate insulating film 4 is interposed between the floating gate 3 and the control gate 5. In addition, source and drain regions 6 and 7 are formed in the region of the substrate 1 on both sides of the gate.

In the flash Y pyrom cell having such a structure, the source electrode 6 plays a role of erasing electrons accumulated in the floating gate 3, and the tunnel oxide film 2 is charged in the floating gate 3. Is formed to a thickness of about 100 kW so as to be tunneled and erased through the overlapping region with the source region 6 by the high voltage applied to the source region 6.

On the other hand, the write (wite or program) operation in the flash Y pyrom is caused by the high voltage generated in the channel near the drain region 7 due to the application of a positive high voltage to the control gate 5 and the drain region 7. Hot elecrtons with energy are injected into the floating gate 3 by jumping over the potential barrier of the tunnel oxide film 2 and carried out.

However, the conventional flash Y pyrom as described above has a limitation in high integration because it is difficult to reduce the channel length due to the reduction of the design rule.

In addition, the conventional flash Y pyrom has a small contact area between the gates due to the arrangement of the floating gate and the control gate in a simple stacked structure, so that it is difficult to improve the program and erase characteristics.

Accordingly, an object of the present invention is to provide a flash Y pyrom and a method for manufacturing the same, which are designed to solve the above problems and to allow for high integration and improved characteristics.

1 is a cross-sectional view of a flash Y pyrom cell prepared according to the prior art.

2 is a plan view of a flash Y pyrom according to an embodiment of the present invention.

3A to 3F are cross-sectional views illustrating a process of cutting according to the AA ′ line of FIG. 2 to illustrate a method for manufacturing a flash Y pyrom according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

11 silicon substrate 12 pad oxide film

13: first mask pattern 14: groove

15a: source region 15b: drain region

16 tunnel oxide film 17 floating gate

18: control gate insulating film 19: control gate

20: control gate electrode 21: second mask pattern

22: trench 23: word line

24 planarization film 25 bit line

26: source line

Flash Y pyrom of the present invention for achieving the above object, the silicon substrate having a recess of a predetermined depth; A source region formed in the bottom portion of the groove and a substrate portion on the side thereof, and a drain region formed in the side substrate surface on the upper portion of the groove; A tunnel oxide film formed on a surface of the groove and a source / drain region having a different thickness; A floating gate formed on the tunnel oxide film on the inner wall of the groove; A control gate insulating film formed on the floating gate and the tunnel oxide film; A control gate formed to bury the recess; A control gate electrode formed on the control gate; An isolation layer surrounding the recess and formed at the same height as the control gate electrode; A word line formed on the control gate electrode and a device isolation layer adjacent thereto; A planarization layer formed on the word line and the device isolation layer; A source line contact plug and a bit line contact plug formed in the planarization layer and the device isolation layer to be in contact with the source region and the drain region, respectively; And a bit line and a source line formed to contact the source line contact plug and the bit line contact plug on the planarization layer, respectively.

The flash Y pyrom of the present invention further includes a hot carrier generation enhancement region formed under the drain region.

In the flash Y pyrom of the present invention, the groove is preferably provided with a rectangular groove, and the tunnel oxide film is formed on the source / drain region so that it is thicker than the wall of the groove.

In addition, the method of manufacturing a flash Y pyrom of the present invention, forming a groove of a predetermined shape and depth in the silicon substrate; Performing ion implantation of different energies twice in the substrate portion on the bottom of the groove and its side and on the substrate surface on the upper side of the groove to form source and drain regions, respectively; Forming a tunnel oxide film having a different thickness on the inner wall of the groove and a source / drain region through a thermal process; Depositing a first conductive film on the tunnel oxide film; Blanket etching the first conductive film to form a floating gate on the tunnel oxide film of the inner wall of the groove; Forming a control gate insulating film on the floating gate and the tunnel oxide film; Depositing a second conductive film so as to completely fill the groove on the control gate insulating film; Polishing the second conductive film and the control gate insulating film until the tunnel oxide film is exposed so that a control gate is formed in the groove; Forming a control gate electrode at a predetermined height on the control gate using the control gate material as a seed; Selectively etching the tunnel oxide layer, the drain region, the substrate, and the source region to form a trench defining a device isolation region; Depositing an insulating film on said resultant such that said trench is completely buried; Forming an isolation layer by polishing the insulating layer until the control gate electrode is exposed; Forming a word line on the control gate electrode and the isolation layer; Forming a planarization layer on the word line and the isolation layer; Forming first and second contact plugs in the planarization and isolation layers, the first and second contact plugs contacting the source and drain regions, respectively; And forming a source line and a bit line contacting the first and second contact plugs, respectively, on the planarization layer.

The method of manufacturing a flash y-pyrom according to the present invention further includes forming a hot carrier generation enhancement region before or after the formation of the drain region.

In the method of manufacturing a flash y-pyrom of the present invention, the groove is formed into a rectangular groove, and the tunnel oxide film is formed thicker than the inner wall of the groove on the source and drain regions.

The method may further include forming a trench on the control gate electrode and the isolation layer; forming a mask pattern defining an isolation region on the control gate electrode and the isolation layer; First etching the device isolation layer region not covered by the mask pattern, the tunnel oxide layer, the drain region, and the substrate below the mask pattern as an etch mask; And etching a predetermined thickness of the source region exposed by the primary etching in a secondary manner, wherein the secondary etching preferably etches a thickness of 200 to 500 mm 3.

According to the present invention, since each cell is formed vertically in the groove, it is possible to reduce the cell area to achieve high integration, and also to increase the contact area between the gates and greatly influence the thickness reduction vector of the tunnel oxide film. It can be expected to improve the characteristics by not receiving.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view of a flash Y pyrom according to an embodiment of the present invention.

As shown, several grooves 14 are provided in the substrate, and each groove 14 includes a tunnel oxide film 16, a floating gate 17, a control gate insulating film 18, and a control gate 19. It is installed along the wall in turn.

The word line 23 extends in one direction while being in contact with the control gate electrode 20 of each cell, and the bit line 25 is in contact with the drain region (not shown) of each cell. It extends in the direction which intersects with.

In addition, a source line 26 extends in parallel with and after several bit lines 25, which are in contact with the source region (not shown) via the source line contact SC.

Since the flash Y pyrom according to the present invention having such a structure is installed vertically in the groove, it is possible to secure a desired channel length only by increasing the depth of the groove, thus greatly increasing the design rule. Since it is not affected, it is very advantageous for high integration.

In addition, since the conventional flash Y pyrom has a structure in which the floating gate and the control gate are simply stacked, there is a limitation in improving the coupling capacitance ratio between the gates. The area is relatively increased, resulting in an improved coupling capacitance recipe, resulting in improved program and erase characteristics.

In addition, since it is not greatly influenced by the change in the thickness of the tunnel oxide film, the reliability of the device can be ensured.

3A to 3F are cross-sectional views illustrating processes according to the line AA ′ of FIG. 2 to illustrate a method for manufacturing a flash y-pyrom cell according to an embodiment of the present invention.

Referring to FIG. 3A, a silicon substrate 11 having a p-well (not shown) is formed inside a surface according to a known method. Thereafter, a pad oxide film 12 is formed on the substrate 11 through a thermal process, and a mask film, for example, a photoresist film is coated on the pad oxide film 12, and the first groove for forming grooves is exposed. The mask pattern 13 is formed.

Subsequently, the recess 14 is formed by etching the exposed pad oxide layer region and the lower silicon substrate region by a predetermined depth using the first mask pattern 13 as an etch barrier. In this case, the etching is performed by a reactive ion etching (RIE) method, in particular, the groove 14 is preferably formed to a depth corresponding to the desired channel length. In addition, the groove 14 is preferably formed as a rectangular groove.

Referring to FIG. 3B, in a state in which the first mask pattern and the pad oxide film are removed, the ion implantation process of different energies is performed twice in succession so that the source region 15a is formed at the bottom of the groove 14 and the substrate portion of the side surface thereof. And the drain region 15b is formed in the substrate portion on the upper outer side of the recess 14.

Referring to FIG. 3C, the resultant is thermally oxidized and nitridated until the step, so that the silicon oxide film (SiO 2) is formed on the wall surface of the groove 14 and the surface of the source region 15a and the drain region 15b. A tunnel oxide film 16 is formed. In this case, the tunnel oxide film 16 formed on the surface of the exposed source and drain regions 15a and 15b is relatively thicker than that formed on the wall surface of the recess 14, depending on the doping concentration dependency. 5-7 times or more thick. In addition, portions of the surfaces of the exposed source and drain regions 15a and 15b are oxidized together.

Subsequently, a conductive film for a floating gate, preferably a polysilicon film, is deposited on the tunnel oxide film 16, and then anisotropic dry etching with a blanket without use of an etching mask is performed on the sidewall of the groove 14 to form a floating gate ( 17). Then, after depositing a control gate insulating film 18, such as an ONO film, on the tunnel oxide film 16 and the floating gate 17, on the ONO film 18 so that the recess 14 is completely embedded. In the state of depositing a control gate conductive film, preferably, a polysilicon film, the conductive film and the insulating film are formed by a known chemical mechanical polishing (CMP) process until the tunnel oxide film 16 is exposed. Polishing to achieve surface planarization and at the same time to form a control gate 19 in the recess 14.

Referring to FIG. 3D, polysilicon 20 is selectively grown on exposed control gate 19 with seed as the control gate material. Since the polysilicon 20 serves as a control gate electrode in the manufactured flash ypyrom cell, reference numeral 20 denotes a control gate electrode.

Referring to FIG. 3E, the second mask pattern 21 defining the device isolation region is formed by applying, exposing and developing the photoresist on the resultant layer up to the above step. Then, the tunnel oxide layer region and the drain region and the substrate region below which are not covered by the second mask pattern 21 are first etched, and then some thickness of the source region exposed by the first etch, for example, the surface The trench 22 is formed by secondly etching a thickness of 200 to 500 mm 3 from the second.

Referring to FIG. 3F, in a state in which the second mask pattern is removed, an oxide film is thickly deposited on the resultant material up to the step so that the trench is completely buried, and then, in a CMP process until the control gate electrode 20 is exposed. The oxide film is polished to form the device isolation film 22. Subsequently, a word line conductive film is deposited on the device isolation layer 22 and the control gate electrode 20, and patterned to form a word line 23 in contact with the control gate electrode 20. Thereafter, after the planarization film 24 is deposited on the word line 23 and the device isolation layer 22, the surface of the word line 23 and the device isolation layer 22 is polished and polished to make the CMP process smooth.

Next, a portion of the planarization film 24, the device isolation film 22, the control gate insulating film 18, and the tunnel oxide film 16 is selectively etched to form a contact hole exposing the drain region 15b. A plug conductive film is embedded in the contact hole to form a bit line contact plug 25. At this time, although not shown, a contact hole for exposing a portion of the source region 15a is formed together when the contact hole is formed, and the source region 15a is exposed when the bit line contact plug 25 is formed. A conductive film is also embedded in the contact hole formed so as to form a source contact plug together.

Subsequently, in a state in which a predetermined conductive film, such as a polysilicon film, is deposited on the contact plug 25 and the planarization film 24, the bit line 26 contacted with the bit line contact plug 25 by patterning it. And a source line contacted with the source contact plug, thereby completing the flash Y pyrom of the present invention.

The flash Y pyrom of the present invention prepared according to the above process, as described above, is formed vertically in the groove, can be very advantageously applied to high integration, and also has a great effect on the thickness change of the tunnel oxide film Of course, the contact area between the gates can be increased, thereby improving its characteristics.

Meanwhile, in the above-described embodiment of the present invention, the device isolation film is formed after the control gate is formed, but it is also possible to perform the process early, for example, before the well formation.

In addition, in the embodiment of the present invention, the source and drain regions are formed after the grooves are formed, but it is also possible to perform the grooves before the grooves are formed.

In addition, a hot carrier generation enhancement region may be formed immediately before or after the formation of the drain region, wherein the region is formed of PSG or BPG as well as ion implantation. It can be formed by use.

Therefore, this invention can be implemented in various changes in the range which does not deviate from the summary.

As described above, according to the present invention, by implementing a flash Y pyrom in the groove, it is possible to secure a desired channel length without being influenced by the reduction of the design rule, and thus high integration can be achieved.

In addition, since the present invention implements a flash Y pyrom in the recess, it is possible to increase the contact area between the floating gate and the control gate, thereby improving the characteristics of the program and erase.

In addition, since the present invention implements a flash Y pyrom in the recess like the concept of a trench capacitor, it is possible to facilitate the implementation of a system on a chip (SOC).

Claims (10)

A silicon substrate having grooves of a predetermined depth; A source region formed in the bottom portion of the groove and a substrate portion on the side thereof, and a drain region formed in the side substrate surface on the upper portion of the groove; A tunnel oxide film formed on a surface of the groove and a source / drain region at different thicknesses; A floating gate formed on the tunnel oxide film on the inner wall of the groove; A control gate insulating film formed on the floating gate and the tunnel oxide film; A control gate formed to bury the recess; A control gate electrode formed on the control gate; An isolation layer surrounding the recess and formed at the same height as the control gate electrode; A word line formed on the control gate electrode and a device isolation layer adjacent thereto; A planarization layer formed on the word line and the device isolation layer; A source line contact plug and a bit line contact plug formed in the planarization layer and the device isolation layer to be in contact with the source region and the drain region, respectively; And And a bit line and a source line formed to contact the source line contact plug and the bit line contact plug on the planarization layer, respectively. The flash Y pyrom according to claim 1, wherein the groove is a rectangular groove. The flash Y pyrom according to claim 1, wherein the tunnel oxide film is formed thicker than the inner wall of the groove on the source and drain regions. The flash ypyrom of claim 1, further comprising a hot carrier generation enhancement region formed under the drain region. Forming grooves of a predetermined shape and depth in the silicon substrate; Performing ion implantation of different energies twice in the substrate portion on the bottom of the groove and its side and on the substrate surface on the upper side of the groove to form source and drain regions, respectively; Forming a tunnel oxide film having a different thickness on the inner wall of the groove and a source / drain region through a thermal process; Depositing a first conductive film on the tunnel oxide film; Blanket etching the first conductive film to form a floating gate on the tunnel oxide film of the inner wall of the groove; Forming a control gate insulating film on the floating gate and the tunnel oxide film; Depositing a second conductive film so as to completely fill the groove on the control gate insulating film; Polishing the second conductive film and the control gate insulating film until the tunnel oxide film is exposed so that a control gate is formed in the groove; Forming a control gate electrode at a predetermined height on the control gate using the control gate material as a seed; Selectively etching the tunnel oxide layer, the drain region, the substrate, and the source region to form a trench defining a device isolation region; Depositing an insulating film on said resultant such that said trench is completely buried; Forming an isolation layer by polishing the insulating layer until the control gate electrode is exposed; Forming a word line on the control gate electrode and the isolation layer; Forming a planarization layer on the word line and the isolation layer; Forming first and second contact plugs in the planarization and isolation layers, the first and second contact plugs contacting the source and drain regions, respectively; And Forming a source line and a bit line in contact with the first and second contact plugs on the planarization layer, respectively. 6. The method of claim 5, wherein the groove is formed as a rectangular groove. The method of claim 5, wherein the tunnel oxide film is formed on the source and drain regions thicker than the inner wall of the groove. The method of claim 5, wherein the forming of the trench comprises: Forming a mask pattern defining an isolation region on the control gate electrode and the isolation layer; First etching the device isolation layer region not covered by the mask pattern, the tunnel oxide layer, the drain region, and the substrate below the mask pattern as an etch mask; And And etching second a predetermined thickness of the source region exposed by the primary etching. 9. The method of claim 8, wherein the secondary etching is characterized in that the etching of the thickness of 200 ~ 500Å. 6. The method of claim 5, further comprising forming a Hot Carrier Generation Enhancing region before or after formation of the drain region.