KR20040001947A - Method for fabricating Semiconductor device - Google Patents
Method for fabricating Semiconductor device Download PDFInfo
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- KR20040001947A KR20040001947A KR1020020037281A KR20020037281A KR20040001947A KR 20040001947 A KR20040001947 A KR 20040001947A KR 1020020037281 A KR1020020037281 A KR 1020020037281A KR 20020037281 A KR20020037281 A KR 20020037281A KR 20040001947 A KR20040001947 A KR 20040001947A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000003990 capacitor Substances 0.000 claims abstract description 43
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000012790 adhesive layer Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims abstract description 9
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 230000000149 penetrating effect Effects 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 239000010408 film Substances 0.000 description 54
- 239000010409 thin film Substances 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910052721 tungsten Inorganic materials 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- 101100537266 Caenorhabditis elegans tin-13 gene Proteins 0.000 description 1
- 229910019899 RuO Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Memories (AREA)
Abstract
본 발명은 캐패시터의 전극으로 사용된 금속과 절연막의 접착층을 선택적으로 제거하는 방법에 있어서 안정적인 공정을 도입하여 효율적인 고집적 반도체 장치 제조방법을 제공하기 위한 것으로, 이를 위해 본 발명은 활성영역이 형성된 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 관통하여 상기 기판의 활성영역과 연결하는 콘택플러그를 형성하는 단계; 상기 콘택플러그 영역을 포함하는 상기 층간절연막 상부에 접착층으로 Al2O3막을 형성하는 단계; 상기 Al2O3막 상부로 캐패시터 절연막을 형성하는 단계; 및 상기 콘택플러그 영역이 노출되도록 상기 캐패시터 절연막 및 상기 Al2O3막을 플라즈마 가스를 이용하여 건식식각 공정으로 제거하는 단계를 포함하는 반도체 제조방법이 제공된다.The present invention is to provide a method for manufacturing an efficient integrated semiconductor device by introducing a stable process in the method for selectively removing the adhesive layer of the metal and the insulating film used as the electrode of the capacitor. Forming an interlayer insulating film on the substrate; Forming a contact plug penetrating the interlayer insulating layer and connecting to the active region of the substrate; Forming an Al 2 O 3 film as an adhesive layer on the interlayer insulating film including the contact plug region; Forming a capacitor insulating film over the Al 2 O 3 film; And removing the capacitor insulating film and the Al 2 O 3 film by a dry etching process using a plasma gas so that the contact plug region is exposed.
Description
본 발명은 반도체 제조기술에 관한 것으로, 특히 반도체 소자의 접착층형성에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to forming an adhesive layer of a semiconductor device.
반도체 소자, 특히 DRAM(Dynamic Random Access Memory)의 반도체 메모리의 집적도가 증가함에 따라 정보 기억을 위한 기본 단위인 메모리 셀의 면적이 급격하게 축소되고 있다.As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.
이러한 메모리 셀 면적의 축소는 셀 캐패시터의 면적 감소를 수반하여, 센싱 마진과 센싱 속도를 떨어뜨리고, α-입자에 의한 소프트 에러(Soft Error)에 대한 내구성이 저하되는 문제점을 유발하게 된다. 따라서, 제한된 셀 면적에서 충분한 정전용량을 확보할 수 있는 방안이 필요하게 되었다.Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.
캐패시터의 정전용량(C)은 하기의 수학식 1과 같이 정의된다.The capacitance C of the capacitor is defined as in Equation 1 below.
여기서, ε은 유전률, As는 전극의 유효 표면적, d는 전극간 거리를 각각 나타낸 것이다.Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.
따라서, 캐패시터의 정전용량을 늘리기 위해서는 전극의 표면적을 넓히거나, 유전체 박막의 두께를 줄이거나, 유전률을 높여야 한다.Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.
이 중에서 전극의 표면적을 넓히는 방안이 제일 먼저 고려되어 왔다. 컨케이브 구조, 실린더 구조, 다층 핀 구조 등과 같은 3차원 구조의 캐패시터는 모두 제한된 레이아웃 면적에서 전극의 유효 표면적을 증대시키기 위하여 제안된 것이다.그러나, 이러한 방법은 반도체 소자가 초고집적화 되면서 전극의 유효 표면적을 증대시키는데 한계를 보이고 있다.Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures such as concave structures, cylinder structures, multi-layer fin structures, etc. are all proposed to increase the effective surface area of the electrode in a limited layout area. Shows a limit to increase
그리고, 전극간 거리(d)를 최소화하기 위해 유전체 박막의 두께를 감소시키는 방안은 유전체 박막의 두께가 감소함에 따라 누설전류가 증가하는 문제 때문에 역시 그 한계에 직면하고 있다.In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.
따라서, 근래에 들어서는 주로 유전체 박막의 유전율의 증대를 통한 캐패시터의 정전용량 확보에 초점을 맞추어 연구, 개발이 진행되고 있다. 전통적으로, 실리콘산화막이나 실리콘질화막을 유전체 박막 재료로 사용한 소위 NO(Nitride-Oxide) 구조의 캐패시터가 주류를 이루었으나, 최근에는 Ta2O5, (Ba,Sr)TiO3(이하 BST라 함) 등의 고유전체 물질이나, (Pb,Zr)TiO3(이하 PZT라 함), (Pb,La)(Zr,Ti)O3(이하 PLZT라 함), SrBi2Ta2O9(이하 SBT라 함), Bi4-xLaxTi3O12(이하, BLT라 함) 등의 강유전체 물질을 유전체 박막 재료로 적용하고 있다.Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta 2 O 5 , (Ba, Sr) TiO 3 (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO 3 (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O 3 (hereinafter referred to as PLZT), SrBi2Ta2O 9 (hereinafter referred to as SBT), Bi Ferroelectric materials such as 4-x La x Ti 3 O 12 (hereinafter referred to as BLT) are applied as the dielectric thin film material.
이러한 고유전체 물질 또는 강유전체 물질을 유전체 박막 재료로 사용하는 고유전체 캐패시터 또는 강유전체 캐패시터를 제조함에 있어서, 고유전체 물질 또는 강유전체 물질 특유의 유전 특성을 구현하기 위해서는 유전체 주변 물질 및 공정의 적절한 제어가 수반되어야 한다.In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.
일반적으로, 고유전체 캐패시터나 강유전체 캐패시터의 상, 하부전극 물질로서 노블메탈(noble metal) 또는 이들의 화합물, 예컨대 Pt, Ir, Ru, RuO2, IrO2등을 사용하고 있다.In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO 2 , IrO 2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.
그러나, 캐패시터의 상,하부전극으로 금속막을 사용함으로서, 금속막과 절연막과의 접착문제가 반도체 소자의 캐패시터의 제조시에 새로운 문제점으로 대두되고 있다. 금속막은 그 특성상 절연막으로 사용되는 산화막등과 접착특성이 열화되기 때문이다.However, by using a metal film as the upper and lower electrodes of the capacitor, the problem of adhesion between the metal film and the insulating film has emerged as a new problem in manufacturing the capacitor of the semiconductor device. This is because the metal film is deteriorated in adhesion properties with an oxide film or the like used as an insulating film due to its characteristics.
도1a 내지 도1d는 종래기술에 의한 반도체 장치의 캐패시터 하부전극과 캐패시터 절연막간의 접착층을 형성하는 제조방법을 나타내는 공정단면도이다.1A to 1D are cross-sectional views showing a manufacturing method for forming an adhesive layer between a capacitor lower electrode and a capacitor insulating film of a semiconductor device according to the prior art.
먼저 도1a에 도시된 바와 같이, 반도체기판(10)상에 층간절연막(11)을 형성한 후, 층간절연막(11)을 관통하여 반도체기판(10)의 활성영역(도시안됨)과 연결되는 콘택홀을 형성한다. 콘택홀을 텅스텐으로 매립하여 리세스(recess)된 텅스텐플러그(12)를 형성하고, 텅스텐플러그(12)상에 베리어(barrier) 메탈로 티타늄나이트라이드(이하 TIN이라 함)(13)을 형성한다. 베리어 메탈은 후속 열공정시 산소가 하부구조로 침투하는 것을 막아주는 층이다.First, as shown in FIG. 1A, after forming the interlayer insulating film 11 on the semiconductor substrate 10, the contact penetrates the interlayer insulating film 11 and is connected to an active region (not shown) of the semiconductor substrate 10. Form a hole. The contact hole is filled with tungsten to form a recessed tungsten plug 12, and a titanium nitride (hereinafter referred to as TIN) 13 is formed on the tungsten plug 12 with a barrier metal. . Barrier metal is a layer that prevents oxygen from penetrating the substructure during subsequent thermal processes.
이어서 도1b에 도시된 바와 같이, 캐패시터 하부전극과 층간절연막(11)과의 접착을 위한 접착층으로 Al2O3막(14)를 형성하고, Al2O3막(14) 상으로 캐패시터 절연막(15)를 형성한다.Subsequently, as shown in FIG. 1B, an Al 2 O 3 film 14 is formed as an adhesive layer for adhesion between the capacitor lower electrode and the interlayer insulating film 11, and the capacitor insulating film is formed on the Al 2 O 3 film 14. 15).
이어서 도1c에 도시된 바와 같이, 캐패시터가 형성될 영역의 캐패시터 절연막(15)를 선택적으로 제거한다.Subsequently, as shown in FIG. 1C, the capacitor insulating film 15 in the region where the capacitor is to be formed is selectively removed.
이어서 도1d에 도시된 바와 같이, 텅스텐 콘택플러그(12) 상부의 TIN(13)이 노출되도록 Al2O3막(14)을 습식식각 방식으로 제거한다. 이 때 주로 HF를 이용하여습식방식으로 Al2O3막(14)을 식각하기 때문에 등방성의 식각특성을 피할 수 없다.As shown in FIG. 1D, the Al 2 O 3 film 14 is removed by a wet etching method so that the TIN 13 on the tungsten contact plug 12 is exposed. At this time, since the Al 2 O 3 film 14 is mainly etched using HF, the isotropic etching characteristics cannot be avoided.
그러나 등방성 식각을 하여 Al2O3막(14)을 제거하게 되면, 산화막등으로 형성되는 캐패시터절연막(15)도 손실되는 현상이 생기고, 도1d의 'A'에 이 현상이 도시되어 있다.However, when the Al 2 O 3 film 14 is removed by isotropic etching, the capacitor insulating film 15 formed of an oxide film or the like is also lost, and this phenomenon is illustrated in 'A' of FIG. 1D.
이 때 HF의 농도 변화에 따라 수평 및 수직방향의 캐패시터 절연막의 손실또한 변하므로 공정안정성 측면에서도 관리하기 힘든 공정이다.In this case, the loss of the capacitor insulating film in the horizontal and vertical directions also changes according to the change in HF concentration, which makes it difficult to manage the process stability.
점점더 고집적으로 반도체 소자가 제조되어 셀 사이즈가 축소됨에 따라서 캐패시터 절연막의 손실은 집적도 측면에서 큰 문제점으로 나타난다.As semiconductor devices are manufactured more and more densely and the cell size is reduced, the loss of the capacitor insulating film is a big problem in terms of integration.
본 발명은 캐패시터의 전극으로 사용된 금속과 절연막의 접착층을 선택적으로 제거하는 방법에 있어서 안정적인 공정을 도입하여 효율적인 고집적 반도체 장치 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide an efficient method for manufacturing a highly integrated semiconductor device by introducing a stable process in a method for selectively removing an adhesive layer of a metal and an insulating film used as an electrode of a capacitor.
도1a 내지 도1d는 종래기술에 의한 반도체 제조방법을 나타내는 공정단면도.1A to 1D are process cross-sectional views showing a semiconductor manufacturing method according to the prior art.
도2a 내지 도2d는 본 발명의 바람직한 실시예에 따른 반도체 제조방법을 나타내는 공정단면도.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor in accordance with a preferred embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판20: substrate
21 : 층간절연막21: interlayer insulating film
22 : 텅스텐플러그22: tungsten plug
23 : TIN막23: TIN film
24 : Al2O3막24: Al 2 O 3 membrane
25 : 캐패시터 절연막25 capacitor capacitor
상기의 목적을 달성하기 위한 본 발명은 활성영역이 형성된 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 관통하여 상기 기판의 활성영역과 연결하는 콘택플러그를 형성하는 단계; 상기 콘택플러그 영역을 포함하는 상기 층간절연막 상부에 접착층으로 Al2O3막을 형성하는 단계; 상기 Al2O3막 상부로 캐패시터 절연막을 형성하는 단계; 및 상기 콘택플러그 영역이 노출되도록 상기 캐패시터 절연막 및 상기 Al2O3막을 플라즈마 가스를 이용하여 건식식각 공정으로 제거하는 단계를 포함하는 반도체 제조방법이 제공된다.The present invention for achieving the above object is a step of forming an interlayer insulating film on a substrate on which an active region is formed; Forming a contact plug penetrating the interlayer insulating layer and connecting to the active region of the substrate; Forming an Al 2 O 3 film as an adhesive layer on the interlayer insulating film including the contact plug region; Forming a capacitor insulating film over the Al 2 O 3 film; And removing the capacitor insulating film and the Al 2 O 3 film by a dry etching process using a plasma gas so that the contact plug region is exposed.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.
도2a 내지 도2d는 본 발명에 의한 바람직한 실시예에 따른 반도체 제조방법을 나타내는 도면이다.2A to 2D are diagrams illustrating a semiconductor manufacturing method according to a preferred embodiment of the present invention.
먼저 도2a에 도시된 바와 같이, 반도체기판(20)상에 층간절연막(21)을 형성한 후, 층간절연막(21)을 관통하여 반도체기판(20)의 활성영역(도시안됨)과 연결되는 콘택홀을 형성한다. 콘택홀을 텅스텐으로 매립하여 리세스(recess)된 텅스텐플러그(22)를 형성하고, 텅스텐플러그(22)상에 베리어(barrier) 메탈로 티타늄나이트라이드(이하 TIN이라 함)(23)을 형성한다. 베리어 메탈은 후속 열공정시 산소가 하부구조로 침투하는 것을 막아주는 층이다.First, as shown in FIG. 2A, after forming the interlayer insulating film 21 on the semiconductor substrate 20, the contact is connected to the active region (not shown) of the semiconductor substrate 20 through the interlayer insulating film 21. Form a hole. A contact hole is buried in tungsten to form a recessed tungsten plug 22, and a titanium nitride (hereinafter referred to as TIN) 23 is formed on the tungsten plug 22 with a barrier metal. . Barrier metal is a layer that prevents oxygen from penetrating the substructure during subsequent thermal processes.
이어서 도2b에 도시된 바와 같이, 후속공정에서 형성될 캐패시터 하부전극과 층간절연막(21)과의 접착을 위한 접착층으로 Al2O3막(24)를 형성한다.Subsequently, as shown in FIG. 2B, an Al 2 O 3 film 24 is formed as an adhesive layer for adhesion between the capacitor lower electrode and the interlayer insulating film 21 to be formed in a subsequent process.
이어서 도2c에 도시된 바와 같이, Al2O3막(24) 상으로 캐패시터 절연막(25)를형성한다.Subsequently, as shown in FIG. 2C, a capacitor insulating film 25 is formed on the Al 2 O 3 film 24.
이어서 도2d에 도시된 바와 같이, 캐패시터가 형성될 영역의 캐패시터 절연막(25) 및 Al2O3막(24)을 플라즈마를 이용한 건식식각 방식으로 제거한다. 건식식각방식은 습식방식과는 달리 측면방향으로 식각이 되지 않는 비등방성으로 식각이 되는 특성을 가지고 있고 식각가스에 따라 하부층에 대한 고선택비를 유지할 수 있다.Subsequently, as shown in FIG. 2D, the capacitor insulating film 25 and the Al 2 O 3 film 24 in the region where the capacitor is to be formed are removed by a dry etching method using plasma. Unlike the wet method, the dry etching method has an anisotropic etching property that cannot be etched laterally and maintains a high selectivity ratio for the lower layer according to the etching gas.
Al2O3막(24)을 식각하면서 절연막으로 사용되는 산화막 및 TIN막에 대해서 고선택비를 유지할 수 있도록, 건식식각공정시에 산소플라즈마를 기본하여 CL2, Ar 플라즈마를 첨가하여 실시한다. 이 때 TiN막(23) 및 캐패시터 절연막에 대한 고선택비를 유지하기 위해서 Cl2이 차지하는 가스비율은 [Cl2/O2+Cl2)]*100은 50%미만이 되게 한다.In order to maintain a high selectivity for the oxide film and the TIN film used as the insulating film while etching the Al 2 O 3 film 24, CL 2 , Ar plasma is added based on oxygen plasma during the dry etching process. At this time, in order to maintain a high selectivity for the TiN film 23 and the capacitor insulating film, the gas ratio occupied by Cl2 is made less than 50% of [Cl 2 / O 2 + Cl 2 )] * 100.
또한 Al2O3막(24)을 식각하기 위해서는 상당한 바이어스 파워가 필요한데, CCP(capacitively coupled plasma)인 경우에 RIE(Reactive Ion etching) 및 MERIE(Magnetic Enhancement Rie)로 하는 경우 50Watt이상으로 하고, ICP(Inductively Coupled Plasma) 또는 TCP(Transformer Coupled Plasma)인 경우에는 100Watt이상으로 한다. 이 때 웨이퍼 표면 혹은 장비내의 웰(Wall)에 증착된 후 파티클 소스로 작용할 우려가 있으므로, 가능한 저압력, 바람직하게 10mTorr 이하로 공정을 진행한다.In addition, a significant bias power is required to etch the Al 2 O 3 film 24. In the case of capacitively coupled plasma (CCP), when the reactive ion etching (RIE) and the magnetic enhancement lie (MERIE) are set to 50 Watt or more, the ICP In the case of (Inductively Coupled Plasma) or TCP (Transformer Coupled Plasma), it is set to 100 Watt or more. At this time, since it is likely to act as a particle source after being deposited on the wafer surface or the well in the equipment, the process is carried out at the lowest possible pressure, preferably 10 mTorr or less.
그러나 여기서 산소플라즈마를 사용하게 되면 TiN막(23)을 산화시켜 전도성을 잃게 할 수 있으므로 적절한 후속공정이 요구되는데, Ar,Xe,He를 사용하여 TiN막 산화층을 제거하는 후속공정을 실시한다. 이 때 Ar이 차지하는 가스비율[(Ar/O2+Ar)*100)]은 75% 미만이 되도록한다.However, if the oxygen plasma is used, since the TiN film 23 may be oxidized to lose conductivity, an appropriate subsequent step is required. A subsequent step of removing the TiN film oxide layer is performed using Ar, Xe, and He. At this time, the gas ratio [(Ar / O 2 + Ar) * 100) occupied by Ar is less than 75%.
또한, Al2O3 박막의 특성상 잔류물 문제를 해결하기 위해 공정에 사용되는 감광막의 두께를 최소화 해야 하며, 후속 감광막 제거공정에서는 통상적으로 사용되는 산소플라즈마를 이용하면 Al성분이 다시 산화되어 제거하기 곤란한 잔류물로 변하므로 솔벤트(solvent) 계열로 ACT-Series 및 EKC-Series 이용하여 습식 스트립 공정을 실시한다.In addition, due to the characteristics of the Al2O3 thin film, the thickness of the photoresist film used in the process should be minimized in order to solve the residue problem. In the subsequent photoresist removal process, the Al component is oxidized again by using oxygen plasma, which is commonly used. The wet strip process is carried out using the ACT-Series and EKC-Series as solvents.
이어서 후속 공정으로 캐패시터 하부전극, 유전체박막 및 상부전극을 형성하여 캐패시터를 완성한다.Subsequently, a capacitor lower electrode, a dielectric thin film, and an upper electrode are formed in a subsequent process to complete the capacitor.
전술한 본 발명에 의해 하부전극과 접촉되는 TiN막(23) 및 캐패시터 절연막(25)의 공정을 좀더 크리티컬하게 조절할 수 있으며, 또한 캐패시터 상부전극의 스텝커퍼리지(step coverage)에 안정성을 확보할 수 있다. 결국, 캐패시터 절연막(25)의 손실을 최소화 할 수 있으므로 고집적으로 반도체 장치를 제조할 수 있다.According to the present invention described above, the processes of the TiN film 23 and the capacitor insulating film 25 in contact with the lower electrode can be more critically controlled, and stability can be ensured in the step coverage of the capacitor upper electrode. have. As a result, since the loss of the capacitor insulating film 25 can be minimized, the semiconductor device can be manufactured highly integrated.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
본 발명에 따라 캐패시터 하부전극과 절연막간의 접착층을 형성하게 되면, 캐패시터 절연막의 손실을 최소화 할 수 있으므로 고집적 반도체 장치의 제조에 유리하다.According to the present invention, when the adhesive layer between the capacitor lower electrode and the insulating film is formed, the loss of the capacitor insulating film can be minimized, which is advantageous for the manufacture of highly integrated semiconductor devices.
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