KR20040008897A - Ferroelectric Random Access Memory hvaing open type diffusion barrier structure and Method for fabricating the same - Google Patents

Abstract

PURPOSE: A ferroelectric memory device having an open type diffusion barrier structure and its manufacturing method are provided to be capable of simplifying manufacturing processes. CONSTITUTION: A ferroelectric memory device is provided with a semiconductor substrate(31) having transistors, an interlayer dielectric(36) formed on the resultant structure, contact parts connected through the interlayer dielectric with drains(35b), and a stack structure formed at the upper portion of the interlayer dielectric and connected with the contact part. At this time, the stack structure is made of a diffusion barrier(43a), a lower storage node, a ferroelectric layer(48a), and an upper storage node. The ferroelectric memory device further includes an oxygen diffusion barrier(50a) for enclosing the stack structure, and an isolated insulating layer(51a) formed at the upper portion of the oxygen diffusion barrier.

Description

Ferroelectric random access memory hvaing open type diffusion barrier structure and method for fabricating the same

TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a ferroelectric memory device and a method for manufacturing the same.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory (FeRAM) device using such a ferroelectric thin film is a kind of nonvolatile memory device, which not only stores stored information even when power is cut off, but also operates at a speed of DRAM. It is comparable to the next generation memory device.

1 is a cross-sectional view of a ferroelectric memory device having a buried barrier film structure according to the prior art.

Referring to FIG. 1, an isolation layer 12 for isolation between devices is formed on a semiconductor substrate 11, and a gate oxide layer 13 and a word line 14 are formed on an active region of the semiconductor substrate 11. Source / drain 15a and 15b of the transistor are formed in the active region of the semiconductor substrate 11 on both sides of the word line 14.

A first interlayer insulating film ILD 16a is formed on the semiconductor substrate 11, and the tungsten plug 17 penetrates through the first interlayer insulating film 16a to the bit line contact hole reaching the source / drain 15a on one side. ) Is embedded, and the bit line 18 is connected to the tungsten plug 17.

As such, the storage node contact is formed by covering the second interlayer insulating film 16b over the semiconductor substrate 11 on which the transistor and the bit line are formed, and simultaneously penetrating the second interlayer insulating film 16b and the first interlayer insulating film 16a. TiN / Ti 19 and tungsten plug 20 are partially embedded in the hole, and TiN 21 is embedded in the remaining contact holes.

The lower electrodes stacked in the order of the iridium film 23, the iridium oxide film 24, and the platinum film 25 on the TiN 21 are connected, and the ferroelectric film 26 and the upper electrode 27 are stacked on the lower electrode. ) Is formed. Here, the iridium film 23 is an oxygen barrier film, the iridium oxide film 24 is an adhesive layer, and the platinum film 25 is a metal film which is a substantially lower electrode. On the other hand, in order to increase the adhesion between the iridium film 23 and the second interlayer insulating film, an alumina 22 as an adhesive layer is inserted.

The third interlayer insulating film 28 covers the entire surface including the upper electrode 27, and the barrier metal TiN 29 and TiN / Ti 30a are formed through contact holes formed through the third interlayer insulating film 28. ), Al (30b), and a metal wiring stacked in the order of TiN (30c), which is an antireflection film, is connected to the upper electrode (27).

The ferroelectric capacitor of FIG. 1 uses a platinum / iridium oxide / iridium film (25/24/23) stack as a lower electrode, and the TiN is interposed between the tungsten plug 20 and the iridium film 23 to improve the heat resistance of the structure. A diffusion barrier film such as (21) is applied.

In FIG. 1, the TiN 21 has a buried barrier structure completely embedded in the contact hole, because the TiN 21 has the weakest thermal stability.

However, in order to embed a diffusion barrier film such as TiN 21 in the storage node contact hole, a process becomes very complicated. That is, first, the tungsten film needs to be etched back. The tungsten film etchback process has a disadvantage of poor reproducibility, and there is no method for monitoring during the device manufacturing process. After the tungsten film etch back, TiN must be deposited to bury the top of the recessed tungsten plug. As such, in order to fill TiN in the storage node contact hole, chemical vapor deposition (CVD) is necessary. In addition, in the case of depositing TiN by chemical vapor deposition (CVD), if the thickness is increased by 1000 GPa or more, cracks may occur, thereby limiting the deposition thickness. In addition, a chemical mechanical polishing (CMP) process is additionally needed. After chemical mechanical polishing (CMP), an adhesive layer of alumina 22 is used to increase adhesion between subsequent lower electrodes and the interlayer insulating film. Since the adhesive layer is an insulator, the process is very complicated, such as an additional adhesive layer open mask and an etching process are required to expose the top of the plug.

In addition, in the stacked structure of the platinum film / iridium oxide film / iridium film (25/24/23) constituting the lower electrode, the interface between the platinum film 25 and the iridium oxide film 24 has a weak adhesive property, and in the capacitor patterning process, In this case, it is difficult to etch the upper electrode, the ferroelectric layer and the lower electrode of the stacked structure at one time. Therefore, the two-step etching process of etching the upper electrode first and the ferroelectric layer and the lower electrode later is applied. Very disadvantageous.

In addition, for the metallization process, after forming a capacitor, a contact etching process for depositing a third interlayer dielectric layer 28 and opening an area for metallization is required. After the contact etching process, a process of depositing and patterning TiN 29, a ferro-barrier, is required in order to suppress the deterioration of the capacitor due to metal wiring and the reaction between the platinum film, which is the upper electrode, and the aluminum film. However, this process also requires a capacitor contact process, which is disadvantageous in terms of density.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and fabricated a ferroelectric memory device to simplify the complicated process of embedding a diffusion barrier film between a lower electrode and a plug in a storage node contact in a storage node contact. The purpose is to provide a method.

In addition, another object of the present invention is to provide a high-density ferroelectric memory device having excellent thermal stability and excellent electrical characteristics.

1 illustrates a ferroelectric memory device having a buried barrier film structure according to the prior art;

2 is a cross-sectional view illustrating a ferroelectric memory device according to a first embodiment of the present invention;

3A to 3F are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the first embodiment shown in FIG. 2;

4 is a cross-sectional view illustrating a ferroelectric memory device according to a second embodiment of the present invention;

5A through 5F are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the second embodiment of FIG. 4;

Figure 6 is a plan view after the process of Figure 5f is made.

* Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: device isolation film

33: gate oxide film 34: word line

35a, 35b: source / drain regions 36: first interlayer insulating film

37: bit line contact 38: bit line

39: second interlayer insulating film 40a: TiN / Ti

41a: tungsten plug 43a: diffusion barrier film

44a: first iridium film 45a: iridium oxide film

46a: second iridium film 47a: first platinum film

48a: ferroelectric film 49a: second platinum film

50a: oxygen diffusion barrier film 51a: isolation insulating film

52: barrier metal 53: metal wiring film

The ferroelectric memory device of the present invention for achieving the above object is a semiconductor substrate having a transistor formed, an interlayer insulating film having a flat surface on the upper surface of the semiconductor substrate, a contact portion connected to the source / drain of the transistor through the interlayer insulating film, A stacked structure stacked on the interlayer insulating layer and connected to the contact portion, the lower electrode, the ferroelectric layer, and the upper electrode, the oxygen diffusion barrier film surrounding the side of the stacked structure, and the oxygen diffusion barrier film. And an insulating insulating film on the interlayer insulating film having a flat surface exposing the surface of the upper electrode, and a metal wiring formed on the upper electrode, wherein the oxygen diffusion barrier film is formed of the laminated structure. In the form of a spacer in contact with the side wall, or It characterized in that at the same time in contact with the side wall and the surface of the insulating film between layers of the stack group.

In the method of manufacturing a ferroelectric memory device of the present invention, forming an interlayer insulating layer on a semiconductor substrate on which a transistor is formed, etching the interlayer insulating layer to form a storage node contact hole reaching a source / drain region of the transistor; Embedding a plug in the storage node contact hole; forming a stacked structure stacked in order of a diffusion barrier film, a lower electrode, a ferroelectric film, and an upper electrode on the interlayer insulating film including the plug; Forming an oxygen diffusion barrier film in contact with the side of the stack structure and an isolation insulating film in contact with the oxygen diffusion barrier film having a flat surface exposing the upper electrode surface, and forming a metal wiring on the upper electrode; Characterized in that, the step of forming the laminated structure is the Depositing a diffusion barrier film on the interlayer insulating film including a lug, depositing a lower electrode and a ferroelectric film on the diffusion barrier film, and depositing an upper electrode on the ferroelectric film, a hard mask and a photoresist film on the upper electrode. Forming a stacked mask in the order of; and etching the upper electrode, the ferroelectric layer, the lower electrode, and the diffusion barrier layer at a time with the mask as an etching mask.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

In the embodiments described below, a method of manufacturing a ferroelectric memory device in which the diffusion barrier film between the tungsten plug and the lower electrode has an open barrier structure instead of a buried barrier layer structure is proposed.

2 is a cross-sectional view illustrating a ferroelectric memory device according to a first embodiment of the present invention.

Referring to FIG. 2, a first interlayer insulating film 36 and a second interlayer insulating film 39 are formed on the semiconductor substrate 31 on which the device isolation film 32 is formed, and the second interlayer insulating film 39 is formed as an interlayer insulating material. TiN / Ti 40a and tungsten plug 41a are buried in the storage node contact holes that simultaneously pass through the first interlayer insulating film 36. On the other hand, a gate oxide film 33 and a word line 34 are formed on the semiconductor substrate 31, and source / drain regions 35a and 35b are formed in the semiconductor substrate 31, and the first interlayer insulating layer 36 is formed. The bit line contact 37 and the bit line 38 are connected to the source / drain region 35a on one side thereof, and the TiN / Ti 40a and the tungsten plug 41a, which are barrier metals, are connected to the other source / drain 35b. )

The lower layer stacked on the tungsten plug 41a in the order of the diffusion barrier film 43a, the first iridium film 44a, the iridium oxide film 45a, the second iridium film 46a, and the first platinum film 47a. The ferroelectric capacitor of the stacked structure stacked in the order of the electrode, the ferroelectric film 48a and the upper electrode of the second platinum film 49a is connected.

The oxygen diffusion barrier film 50a is in contact with the sidewall of the ferroelectric capacitor, and the insulating diffusion film 51a surrounds the oxygen diffusion barrier film 50a. The flat surface exposes the upper electrode of the ferroelectric capacitor.

The barrier metal 52 and the metallization film 53 are directly connected to the second platinum film 49a as the upper electrode of the ferroelectric capacitor without contact.

In FIG. 2, the diffusion barrier film 43a is a film for preventing the interdiffusion between the first iridium film 44a and the tungsten plug 41a constituting the lower electrode, and includes TiN, TiAlN, TaN, TaAlN, TiSiN, TaSiN, RuTiN, RuTaN, CrTiN, or CrTaN is selected, and these diffusion barrier films 43a have a thickness of 50 kPa to 1000 kPa.

The oxygen diffusion barrier film 50a surrounding the ferroelectric capacitor is an insulating film excellent in oxygen diffusion preventing property, and the insulating insulating film 51a is an insulating film excellent in planarization property. For example, the oxygen diffusion barrier film 50a is selected from silicon nitride film (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), silicon oxynitride film (SiON), and these oxygen diffusion barrier films 50a are 100 to 3000Å thick.

As a result, the diffusion barrier layer 43a, which is a diffusion barrier layer between the tungsten plug 41a and the first iridium layer 44a constituting the lower electrode, has a structure in which the diffusion barrier layer 43a is opened out of the storage node contact hole, and also forms a stacked structure. The oxygen diffusion barrier film 50a surrounds the side surface of the film 43a.

3A to 3F are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the second embodiment of FIG. 2.

As shown in FIG. 3A, an isolation region 32 is formed on the semiconductor substrate 31 to define an active region, thereby defining an active region, and forming a gate oxide layer 33 and a word on the active region of the semiconductor substrate 31. Lines 34 are formed in sequence.

Next, impurities are implanted into the semiconductor substrate 31 on both sides of the word line 34 to form source / drain regions 35a and 35b of the transistor.

Although not shown in the drawings, spacers may be formed on both sidewalls of the word line 34, and thus source / drain regions 35a and 35b having a lightly doped drain (LDD) structure may be formed. That is, the LDD region is formed by ion implanting low concentration impurities using the word line 34 as a mask, and then spacers are formed on both side walls of the word line 34, and the high concentration impurities are formed using the word line 34 and the spacer as a mask. Ion implantation forms source / drain regions 35a and 35b in contact with the LDD region.

Next, after depositing and planarizing the first interlayer insulating layer 36 on the semiconductor substrate 31 on which the transistor is formed, the first interlayer insulating layer 36 is etched with a contact mask (not shown) to form one side source / drain region ( A bit line contact hole exposing 35a) is formed, and a bit line contact 37 embedded in the bit line contact hole is formed. Here, the bit line contact 37 may be formed by depositing tungsten (W) through etch back or chemical mechanical polishing (CMP).

Next, after the bit line conductive film is deposited on the entire surface, patterning is performed to form a bit line 38 connected to the bit line contact, and a second interlayer insulating layer 39 is deposited on the entire surface including the bit line 38. Flatten.

Next, the second interlayer insulating layer 39 and the first interlayer insulating layer 36 are simultaneously etched with a storage node contact mask (not shown) formed on the second interlayer insulating layer 39 to form the other source / drain region 35b. After forming the storage node contact hole to expose the TiN / Ti (40) and the tungsten film 41 is sequentially deposited on the entire surface including the storage node contact hole.

Here, TiN / Ti 40 is a barrier metal for preventing the diffusion of tungsten (W) in the subsequent tungsten plug, the formation method is as follows. For example, a Ti (100Å) and TiN (200Å) for one turn, the deposition after, 850 ℃ / N _2/20 seconds to conduct a rapid heat treatment under the condition of source / drain regions (35b) and ₂ (42) TiSi at the interface between the Ti To form. At this time, TiSi ₂ 42 forms an ohmic contact.

On the other hand, the tungsten film 41 is deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD) or electrochemical deposition (ECD) to a desired thickness in consideration of the size of the plug, the plug size is 0.30㎛ If the deposition is about 3000Å.

As shown in FIG. 3B, the tungsten film 41 and the TiN / Ti 40 are chemically mechanically polished until the surface of the second interlayer insulating film 39 is exposed to form TiN / Ti 40a in the storage node contact hole. An intervening tungsten plug 41a is embedded. As a result, the tungsten plug 41a completely fills the storage node contact hole.

Next, a diffusion barrier film 43 is deposited on the second interlayer insulating film 39 in which the tungsten plug 41a is embedded. Here, the diffusion barrier film 43 is a film for preventing the interdiffusion between the first iridium film 44 and the tungsten plug 41a forming the subsequent lower electrode, TiN, TiAlN, TaN, TaAlN, TiSiN, TaSiN, RuTiN , RuTaN, CrTiN or CrTaN, and these diffusion barrier films 43 have a thickness of 50 kV to 1000 kW using a vapor deposition method selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Is deposited.

On the other hand, after deposition of the diffusion barrier layer 43, heat treatment or plasma treatment may be performed to improve diffusion prevention characteristics and to densify the thin film. The heat treatment may be a known rapid thermal process (RTP) or furnace anneal. At the time of heat treatment, the atmosphere uses N ₂ , Ar, O ₂ or a mixture thereof. The heat treatment time is set to 5 minutes to 2 hours in the heat treatment, and 1 second to 10 minutes in the rapid heat treatment.

In the plasma treatment, the atmosphere is O ₂ , O ₃ , N ₂ , N ₂ O or NH ₃ .

Subsequently, a laminated film forming a lower electrode is formed on the diffusion barrier film 43, and the first iridium film 44, the iridium oxide film 45, the second iridium film 46, and the first platinum film 47 are formed. Deposition in order. At this time, the first iridium film 44 is 1000 m thick, the iridium oxide film 45 is 100 m thick, the second iridium film 46 is 50 m thick, and the first platinum film 47 is 1000 m thick. In this case, the first iridium film 44 serves as an oxygen barrier film, the iridium oxide film 45 serves as a glue layer, and the first platinum film 47 serves as a substantially lower electrode. As a result, the lower electrode has a quadruple structure in which the second iridium film 46 is inserted into the triple structure.

Here, the second iridium film 46 is another adhesive layer inserted for the purpose of improving the adhesion property between the iridium oxide film 45 and the first platinum film 47. In addition to the second iridium film 46, oxygen is added. An insufficiently formed IrO phase may be inserted, and the thickness of the adhesive layer forming the lower electrode is 10 kPa to 100 kPa.

As described above, the laminated film constituting the lower electrode is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), but preferably the first iridium film 44 is 500 kPa to 3000 kPa. It is deposited to a thickness, the iridium oxide film 45 is deposited to a thickness of 10 kPa to 1000 kPa, and the first platinum film 47 is deposited to be 100 kPa to 2000 kPa.

Next, after depositing a ferroelectric film 48 on the first platinum film 47 with a thickness of 1000 mW, the second platinum film 49 is deposited on the ferroelectric film 48 to a thickness of 1500 mW.

At this time, the ferroelectric film 48 has a thickness of 50 kPa to 2000 kPa using one vapor deposition method selected from chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic deposition (MOD) and spin coating (Spin coating). Deposition is performed using one selected from conventional SBT, PZT, and BLT, or one selected from SBT, PZT, SBTN, and BLT in which impurities are added or compositionally changed.

In addition to the second platinum film 49, the upper electrode may be a noble metal such as an iridium film Ir or a ruthenium film Ru, a metal nitride such as TiN, TaN, or WN, IrO ₂ , RuO ₂ , or LSCO. And an oxide electrode such as YBCO.

As shown in FIG. 3C, the second platinum film 49, the ferroelectric film 48, and the first platinum are simultaneously applied to the second platinum film 49 by simultaneously applying a photoresist mask or a photoresist mask and a hard mask (not shown). The film 47, the second iridium film 46, the iridium oxide film 45, the first iridium film 44, and the diffusion barrier film 43 are patterned at one time.

At this time, patterning may be performed using a thick photoresist film alone, but patterning is performed using a mask laminated in the order of the titanium nitride film 600 ', the platinum film 1000' and the photosensitive film 10000 '. Here, the titanium nitride film and the platinum film are used as a hard mask.

For example, after etching the hard mask of the platinum film, the titanium nitride film, and the second platinum film, which is the upper electrode, using the photoresist film as a mask, the surface of the platinum film is exposed when the photoresist film is removed. Using the platinum film as a mask, the ferroelectric film 48 exposed after etching the second platinum film 49 is etched, and the first platinum film 47 using the titanium nitride film exposed by the platinum film exhausted when the ferroelectric film 48 is etched. The second iridium film 46, the iridium oxide film 45, the first iridium film 44, and the diffusion barrier film 43 are etched at once.

When the hard mask and the photoresist mask are applied at the same time, all the films constituting the capacitor can be patterned in one mask process.

On the other hand, a possible mask is selected from photoresist film / iridium film / TiN, photoresist film / ruthenium film / TiN, photoresist film / platinum film / TaN or photoresist film / iridium film / TaN, and capacitors can be patterned at one time using these masks.

After the above-described patterning, the titanium nitride film applied as the hard mask is exhausted and the remaining diffusion barrier film 43a, the first iridium film 44a, the iridium oxide film 45a, the second iridium film 46a, and the first The platinum film 47a forms a lower electrode of a stacked structure, and the remaining second platinum film 49a forms an upper electrode.

As shown in FIG. 3D, since the side surface of the diffusion barrier film 43a having poor thermal stability is exposed after the above-described capacitor patterning process, the high temperature thermal process is not performed immediately after the patterning process. That is, the heat treatment of the high temperature oxidizing atmosphere such as crystallization heat treatment and recovery heat treatment of the ferroelectric film is not performed.

Next, immediately after the capacitor patterning, an oxygen diffusion barrier film 50 having excellent oxygen diffusion preventing property is deposited on the entire surface to suppress oxidation of the side surface of the diffusion barrier film 43a in a subsequent high temperature thermal process.

At this time, the oxygen diffusion barrier film 50 is selected from silicon nitride film (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), silicon oxynitride film (SiON), these oxygen diffusion barrier film 50 is a physical weather The deposition is performed at a thickness of 100 kPa to 3000 kPa using vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

On the other hand, heat treatment is carried out for the purpose of improving the oxygen diffusion preventing properties of the oxygen diffusion barrier film 50, the atmosphere during heat treatment is based on nitrogen, but is carried out in an inert gas atmosphere such as Ar, He, Ne. The heat treatment temperature is 300 ° C to 700 ° C, and the heat treatment or rapid heat treatment is used, and the heat treatment time is performed in the furnace for 10 minutes to 3 hours, and during the rapid heat treatment for 10 seconds to 10 minutes.

Next, the third interlayer insulating film 51 is deposited on the entire surface including the oxygen diffusion barrier film 50 until the space between the capacitors is sufficiently filled. At this time, the third interlayer insulating film 51 is selected from silicon oxides sourced from BPSG, PSG, SOG, or TEOS, and using chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin-on (Spin-On). After the deposition to a thickness of 1000Å to 10000Å, heat treatment is performed for the purpose of improving the densification and planarization characteristics. The heat treatment is a known diffusion furnace or rapid heat treatment, the temperature during the heat treatment is 500 ℃ to 800 ℃, the atmosphere during the heat treatment is N ₂ , Ar or O ₂ , the heat treatment time is 5 minutes to the diffusion furnace 2 hours and 10 seconds to 10 minutes for rapid heat treatment.

As shown in FIG. 3E, the surface of the second platinum film 49a serving as the upper electrode is exposed by etching or performing chemical mechanical polishing without a mask. At this time, since the third interlayer insulating film 51 is etched back or chemical mechanically polished under the condition of exposing the surface of the second platinum film 49a, the oxygen diffusion barrier film 50 on the second platinum film 49a is removed to form a capacitor. Remain in enclosed form. Hereinafter, the remaining oxygen diffusion barrier film is referred to as '50a' and the third interlayer insulating film is referred to as the insulating insulating film 51a. Here, the insulating insulating film 51a is because the remaining third interlayer insulating film insulates and isolates the adjacent capacitors.

After the etch back or chemical mechanical polishing as described above, a heat treatment process for crystallization of the ferroelectric film, which is a heat treatment process of an oxidation atmosphere having the highest temperature, is performed during the manufacturing process of the ferroelectric memory device. Such a heat treatment process generally refers to a heat treatment performed after deposition of the ferroelectric film and subsequent recovery anneal at a time.

For example, during the heat treatment, the temperature is 400 ° C. to 800 ° C., and the heat treatment atmosphere is O ₂ , N ₂ , Ar, O ₃ , He, Ne, Kr, and the heat treatment time is performed for 10 minutes to 5 hours. May be carried out several times using diffusion furnaces or rapid heat treatment devices or by mixing these devices.

As a result, the heat treatment for crystallization of the ferroelectric film is sufficient once, so that the anti-oxidation effect of the tungsten plug and the diffusion barrier film is large.

As shown in FIG. 3F, the barrier metal 52 and the metal wiring layer 53 are formed on the capacitor exposed after the isolation insulating layer 51a is formed. At this time, the barrier metal 52 and the metal wiring film 53 are laminated by arc (anti-reflection coating) -TiN / Al / TiN / Ti lamination, arc-TiN / Al / TiN lamination, TaN / Cu / TaN / It is selected from Ta lamination, TaN / Cu / TaN lamination, WN / W / WN lamination, WN / W / TiN lamination or WN / W / TiN / Ti lamination. The barrier metal and the metal wiring film are laminated using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

The reason why the metal wiring 53 is formed without the contact process is that it is difficult for the contact to be narrowly opened in order to perform the heat treatment process of the ferroelectric film 48a before the metal wiring process. The wiring process is performed.

4 is a cross-sectional view illustrating a ferroelectric memory device according to a second exemplary embodiment of the present invention.

Referring to FIG. 4, a first interlayer insulating film 66 and a second interlayer insulating film 69 are formed on the semiconductor substrate 61 on which the device isolation film 62 is formed, and the second interlayer insulating film 69 is formed. TiN / Ti 70a and tungsten plug 71a are buried in the storage node contact hole that simultaneously passes through the first interlayer insulating layer 66. Meanwhile, a gate oxide film 63 and a word line 64 are formed on the semiconductor substrate 61, and source / drain regions 65a and 65b are formed in the semiconductor substrate 61, and the first interlayer insulating layer 66 is formed. The bit line contact 67 and the bit line 68 are connected to one source / drain region 65a through the through hole, and the TiN / Ti 70a and the tungsten plug 71a are connected to the other source / drain 65b. do.

The lower layer stacked on the tungsten plug 71a in the order of the diffusion barrier film 73a, the first iridium film 74a, the iridium oxide film 75a, the second iridium film 76a, and the first platinum film 77a. Ferroelectric capacitors stacked in the order of the electrode, the ferroelectric film 78a and the upper electrode of the second platinum film 79a are connected.

The oxygen diffusion barrier film 80a in the form of a spacer surrounds the side surface of the ferroelectric capacitor while the upper electrode of the ferroelectric capacitor is exposed, and the insulating insulation film 81a surrounds the oxygen diffusion barrier film 80a.

The barrier metal 82 and the metallization film 83 are directly connected to the second platinum film 79a as the upper electrode of the ferroelectric capacitor without contact.

In FIG. 4, the diffusion barrier film 73a is a film for preventing mutual diffusion between the first iridium film 74a and the tungsten plug 71a constituting the lower electrode, and includes TiN, TiAlN, TaN, TaAlN, TiSiN, TaSiN, RuTiN, RuTaN, CrTiN, or CrTaN are selected, and these diffusion barrier films 73a have a thickness of 50 GPa to 1000 GPa.

The oxygen diffusion barrier film 80a surrounding the ferroelectric capacitor is an insulating film having excellent oxygen diffusion preventing characteristics, and the insulating insulating film 81a is an insulating film having excellent planarization characteristics. For example, the oxygen diffusion barrier film 80a is selected from silicon nitride film (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), and silicon oxynitride film (SiON). 3000Å thick.

As a result, the diffusion barrier layer 73a, which is a diffusion barrier layer between the tungsten plug 71a and the first iridium layer 74a constituting the lower electrode, is opened out of the storage node contact hole, and the diffusion barrier layer having the side surface is exposed. The oxygen diffusion barrier film 80a surrounds 73a.

5A through 5F are cross-sectional views illustrating a method of manufacturing the ferroelectric memory device according to the second embodiment of FIG. 4.

As shown in FIG. 5A, an isolation region 62 for device isolation is formed on the semiconductor substrate 61 to define an active region, and a gate oxide layer 63 and a word are formed on the active region of the semiconductor substrate 61. Lines 64 are formed in turn.

Next, impurities are implanted into the semiconductor substrate 61 on both sides of the word line 64 to form source / drain regions 65a and 65b of the transistor.

Although not shown in the drawings, spacers may be formed on both sidewalls of the word line 64, thereby forming source / drain regions 65a and 65b of the LDD structure. That is, the LDD region is formed by ion implanting low concentration impurities using the word line 64 as a mask, and then spacers are formed on both side walls of the word line 64, and the high concentration impurities are formed using the word line 64 and the spacer as a mask. Ion implantation forms source / drain regions 65a and 65b in contact with the LDD region.

Next, after depositing and planarizing the first interlayer insulating layer 66 on the semiconductor substrate 61 on which the transistor is formed, the first interlayer insulating layer 66 is etched with a contact mask (not shown) to form one side source / drain region ( A bit line contact hole exposing 65a) is formed, and a bit line contact 67 embedded in the bit line contact hole is formed. Here, the bit line contact 67 may be formed by depositing tungsten (W) through etch back or chemical mechanical polishing (CMP).

Next, a bit line conductive film is deposited on the entire surface, and then patterned to form a bit line 68 connected to the bit line contact 67, and a second interlayer insulating layer 69 is formed on the entire surface including the bit line 68. After deposition it is planarized.

Next, the second interlayer insulating layer 69 and the first interlayer insulating layer 66 are simultaneously etched with a storage node contact mask (not shown) formed on the second interlayer insulating layer 69 to form the other source / drain region 65b. After forming the storage node contact hole to expose the TiN / Ti 70 and the tungsten film 71 are sequentially deposited on the entire surface including the storage node contact hole.

Here, TiN / Ti 70 is a barrier metal for preventing the diffusion of tungsten (W) in the subsequent tungsten plug, the formation method is as follows. For example, Ti (100Å) and TiN was then depositing (200Å), 850 ℃ / N 2 / to the rapid heat treatment performed at a 20 second condition of source / drain regions (65b) and the ₂ (72) TiSi at the interface between the Ti To form. At this time, TiSi ₂ 72 forms an ohmic contact.

On the other hand, the tungsten film 71 is deposited using a chemical vapor deposition (CVD), atomic layer deposition (ALD) or electrochemical deposition (ECD) to a desired thickness in consideration of the size of the plug, the plug size is 0.30㎛ If the deposition is about 3000Å.

As shown in FIG. 5B, the tungsten layer 61 and the TiN / Ti 60 are chemically mechanically polished until the surface of the second interlayer dielectric layer 69 is exposed to form TiN / Ti 60a in the storage node contact hole. An intervening tungsten plug 61a is embedded. As a result, the tungsten plug 61a completely fills the storage node contact hole.

Next, a diffusion barrier film 73 is deposited on the second interlayer insulating film 69 in which the tungsten plug 71a is embedded. Here, the diffusion barrier film 73 is a film for preventing the interdiffusion between the first iridium film 74 and the tungsten plug 71a forming the subsequent lower electrode, TiN, TiAlN, TaN, TaAlN, TiSiN, TaSiN, RuTiN , RuTaN, CrTiN, or CrTaN, and the diffusion barrier film 73 is formed to have a thickness of 50 kV to 1000 kV by using a vapor deposition method selected from physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Is deposited.

On the other hand, after deposition of the diffusion barrier film 73, heat treatment or plasma treatment may be performed to improve diffusion prevention characteristics and to densify the thin film. The heat treatment uses a known rapid heat treatment (RTP) or a heat treatment, and the atmosphere during the heat treatment is N ₂ , Ar, O ₂ or a mixture thereof is used. The heat treatment time is set to 5 minutes to 2 hours in the heat treatment, and 1 second to 10 minutes in the rapid heat treatment.

In the plasma treatment, the atmosphere is O ₂ , O ₃ , N ₂ , N ₂ O or NH ₃ .

Next, a laminated film forming a lower electrode is formed on the diffusion barrier film 73, and the first iridium film 74, the iridium oxide film 75, the second iridium film 76, and the first platinum film 77 are formed. Deposition in order. At this time, the first iridium film 74 is 1000 kPa thick, the iridium oxide film 75 is 100 kPa thick, the second iridium film 76 is 50 kPa thick, and the first platinum film 77 is 1000 kPa thick.

In this case, the second iridium film 76 is an adhesive layer inserted for the purpose of improving the adhesion property between the iridium oxide film 75 and the first platinum film 77, and is in a state in which oxygen is deficient in addition to the second iridium film 76. An IrO phase may be inserted, and the thickness of the adhesive layer forming the lower electrode is 10 kPa to 100 kPa.

As described above, the laminated film constituting the lower electrode is deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), but preferably the first iridium film 74 is 500 kPa to 3000 kPa. The film is deposited to a thickness, the iridium oxide film 75 is deposited to a thickness of 10 kPa to 1000 kPa, and the first platinum film 77 is deposited to a thickness of 100 kPa to 2000 kPa.

Next, after depositing a ferroelectric film 78 on the first platinum film 77 with a thickness of 1000 mW, the second platinum film 79 is deposited on the ferroelectric film 78 to a thickness of 1500 mW.

At this time, the ferroelectric film 78 has a thickness of 50 kPa to 2000 kPa using one of the vapor deposition methods selected from chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic deposition (MOD), and spin coating (Spin coating). Deposition is performed using one selected from conventional SBT, PZT, and BLT, or one selected from SBT, PZT, SBTN, and BLT in which impurities are added or compositionally changed.

In addition to the second platinum film 79, the upper electrode may be a noble metal such as an iridium film Ir or a ruthenium film Ru, a metal nitride such as TiN, TaN, or WN, IrO ₂ , RuO ₂ , or LSCO. And an oxide electrode such as YBCO.

As shown in FIG. 5C, the second platinum film 79, the ferroelectric film 78, and the first platinum are simultaneously applied to the second platinum film 79 by simultaneously applying a photoresist mask or a photoresist mask and a hard mask (not shown). The film 77, the second iridium film 76, the iridium oxide film 75, the first iridium film 74, and the diffusion barrier film 73 are patterned at one time.

At this time, patterning may be performed by using a thick photoresist film alone, but patterning is performed using a mask laminated in the order of the titanium nitride film 600 ', the platinum film 1000' and the photosensitive film 10000 '. Here, the titanium nitride film and the platinum film are used as a hard mask.

For example, after etching the hard mask of the platinum film, the titanium nitride film, and the second platinum film, which is the upper electrode, using the photoresist film as a mask, the surface of the platinum film is exposed when the photoresist film is removed. Using the platinum film as a mask, the ferroelectric film 78 exposed after etching the second platinum film 79 is etched, and the first platinum film 77 using the titanium nitride film exposed by the platinum film exhausted when the ferroelectric film 78 is etched. The second iridium film 76, the iridium oxide film 75, the first iridium film 74, and the diffusion barrier film 73 are etched at once.

When the hard mask and the photoresist mask are applied at the same time, all the films constituting the capacitor can be patterned in one mask process.

On the other hand, a possible mask is selected from photoresist film / iridium film / TiN, photoresist film / ruthenium film / TiN, photoresist film / platinum film / TaN or photoresist film / iridium film / TaN, and capacitors can be patterned at one time using these masks.

After the above-described patterning, the titanium nitride film applied as the hard mask is exhausted and the remaining diffusion barrier film 73a, the first iridium film 74a, the iridium oxide film 75a, the second iridium film 76a, and the first The platinum film 77a forms a lower electrode of a stacked structure, and the remaining second platinum film 79a forms an upper electrode.

As shown in FIG. 5D, since the side surface of the diffusion barrier film 73a having poor thermal stability is exposed after the capacitor patterning process described above, the high temperature thermal process is not performed immediately after the patterning process. That is, the heat treatment of the high temperature oxidizing atmosphere such as crystallization heat treatment and recovery heat treatment of the ferroelectric film is not performed.

Next, immediately after the capacitor patterning, an oxygen diffusion barrier film 80 having excellent oxygen diffusion preventing property is deposited on the front surface, followed by a blank etchback, to be left in the form of a spacer surrounding the side of the ferroelectric capacitor, followed by high temperature heat. The side surface of the diffusion barrier film 73a is suppressed from being oxidized in the process.

At this time, the oxygen diffusion barrier film 80 is selected from silicon nitride film (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), silicon oxynitride film (SiON), these oxygen diffusion barrier film (80) is physical The deposition is performed at a thickness of 100 kPa to 3000 kPa using vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

On the other hand, heat treatment is performed for the purpose of improving the oxygen diffusion preventing properties of the oxygen diffusion barrier film 80, the atmosphere during heat treatment is based on nitrogen, but is carried out in an inert gas atmosphere such as Ar, He, Ne. The heat treatment temperature is 300 ° C. to 700 ° C., and the heat treatment or rapid heat treatment is used, and the heat treatment time is performed in the furnace for 10 minutes to 3 hours, and for rapid heat treatment for 10 seconds to 10 minutes.

Next, the third interlayer insulating film 81 is deposited on the entire surface including the oxygen diffusion barrier film 80 until the space between the capacitors is sufficiently filled. At this time, the third interlayer insulating film 81 is selected from silicon oxides sourced from BPSG, PSG, SOG, or TEOS, and using chemical vapor deposition (CVD), physical vapor deposition (PVD), and spin-on (Spin-On). After the deposition to a thickness of 1000Å to 10000Å, heat treatment is performed for the purpose of improving the densification and planarization characteristics. The heat treatment is a known diffusion furnace or rapid heat treatment, the temperature during the heat treatment is 500 ℃ to 800 ℃, the atmosphere during the heat treatment is N ₂ , Ar or O ₂ , the heat treatment time is carried out for 5 minutes to 2 hours in the diffusion furnace And rapid heat treatment for 10 seconds to 10 minutes.

As shown in FIG. 5E, the surface of the second platinum film 79a serving as the upper electrode is exposed by etching or performing chemical mechanical polishing without a mask. At this time, since the third interlayer insulating film 81 is etched back or chemical mechanically polished under the condition of exposing the surface of the second platinum film 79a, the oxygen diffusion barrier film 80 and the third interlayer insulating film 81 on the side of the ferroelectric capacitor. This part is further polished to remain in the form surrounding the capacitor. Hereinafter, the remaining oxygen diffusion barrier film is referred to as '80a' and the third interlayer insulating film is referred to as an insulating insulating film 81a. Here, the isolation insulating film 81a is because the remaining third interlayer insulating film insulates and isolates the neighboring capacitors.

The heat treatment process for crystallization of the ferroelectric film 78a, which is a heat treatment process of an oxidation atmosphere having the highest temperature, is performed during the manufacturing process of the ferroelectric memory device after the etch back or chemical mechanical polishing as described above. Such a heat treatment process generally refers to a heat treatment performed after deposition of the ferroelectric film and subsequent recovery anneal at a time.

For example, during the heat treatment, the temperature is 400 ° C. to 800 ° C., and the heat treatment atmosphere is O ₂ , N ₂ , Ar, O ₃ , He, Ne, Kr, and the heat treatment time is performed for 10 minutes to 5 hours. May be performed several times by using a diffusion furnace or a rapid heat treatment device, or by mixing these devices.

As a result, the heat treatment for crystallization of the ferroelectric film is sufficient once, so that the anti-oxidation effect of the tungsten plug and the diffusion barrier film is large.

As shown in FIG. 5F, the barrier metal 82 and the metal wiring layer 83 are formed on the capacitor exposed after the isolation insulating layer 81a is formed. At this time, the lamination of the barrier metal 82 and the metal wiring film 83 is performed by arc-TiN / Al / TiN / Ti lamination, arc-TiN / Al / TiN lamination, TaN / Cu / TaN / Ta lamination, and TaN / Cu lamination. / TaN lamination, WN / W / WN lamination, WN / W / TiN lamination or WN / W / TiN / Ti lamination. The barrier metal 82 and the metallization film 83 are laminated using chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). When the barrier metal 82 is inserted, the second platinum film 79a serving as the upper electrode and the Al of the metal wiring film 83 are prevented from reacting.

The reason why the metal wiring 83 is formed without the contact process is that it is difficult for the contact to be narrowly opened in order to perform the heat treatment process of the ferroelectric film 78a before the metal wiring process. The wiring process is performed.

FIG. 6 is a plan view after the process of FIG. 5F is performed. In order to minimize the effect of the metallization film 83 process on the ferroelectric capacitor, the metallization film 83 also serves as a plate line. Reference numeral 83 is connected without contact to the second platinum film 79a, which is the upper electrode of the ferroelectric capacitor. The ferroelectric capacitor is connected to the tungsten plug 71a.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has an effect of manufacturing a high-density ferroelectric memory device having excellent thermal stability and electrical characteristics and excellent reproducibility when manufacturing a ferroelectric memory device in which high temperature oxidizing atmosphere heat treatment is essential.

In addition, since the manufacturing process is very simple, there is an effect of improving the yield of the ferroelectric memory device and reducing the cost.

Claims (19)

A semiconductor substrate on which a transistor is formed; An interlayer insulating film having a flat surface over the semiconductor substrate; A contact portion connected to the source / drain of the transistor through the interlayer insulating layer; A stacked structure connected to the contact portion and stacked in an order of a diffusion barrier film, a lower electrode, a ferroelectric film, and an upper electrode formed on the interlayer insulating film; An oxygen diffusion barrier film surrounding a side surface of the laminated structure; An insulating insulating film on the interlayer insulating film having a flat surface that surrounds the oxygen diffusion barrier film and exposes the surface of the upper electrode of the stacked structure; And A metal wiring formed on the upper electrode A ferroelectric memory device, characterized in that consisting of. The method of claim 1, The oxygen diffusion barrier layer is a ferroelectric memory device, characterized in that the spacer in contact with the side wall of the laminated structure. The method of claim 1, And the oxygen diffusion barrier film is in contact with the sidewall of the stacked structure and the surface of the interlayer insulating film. The method of claim 1, The oxygen diffusion barrier film is a ferroelectric memory device, characterized in that selected from silicon nitride film, alumina or silicon oxynitride film. The method of claim 1, The diffusion barrier film is a ferroelectric memory device, characterized in that selected from TiN, TiAlN, TaN, TaAlN, TiSiN, TaSiN, RuTiN, RuTaN, CrTiN or CrTaN. The method of claim 1, The contact portion of the ferroelectric memory device, characterized in that the barrier metal and the tungsten plug is embedded with a flat surface. The method of claim 1, The lower electrode is stacked in the order of the first iridium film, the iridium oxide film and the platinum film, a ferroelectric memory device, characterized in that a second iridium film or an oxygen-deficient IrO phase is inserted between the iridium oxide film and the platinum film. The method of claim 1, The metal wiring, arc-TiN / Al / TiN / Ti lamination, arc-TiN / Al / TiN lamination, TaN / Cu / TaN / Ta lamination, TaN / Cu / TaN lamination, WN / W / WN lamination, WN / W / TiN lamination or A method of manufacturing a ferroelectric memory device, characterized in that selected from WN / W / TiN / Ti lamination. Forming an interlayer insulating film over the semiconductor substrate on which the transistor is formed; Etching the interlayer insulating layer to form a storage node contact hole reaching a source / drain region of the transistor; Embedding a plug in the storage node contact hole; Forming a stacked structure stacked on the interlayer insulating film including the plug in order of a diffusion barrier film, a lower electrode, a ferroelectric film, and an upper electrode; Forming an oxygen diffusion barrier film in contact with a side surface of the stack structure and an isolation insulating film in contact with the oxygen diffusion barrier film, the planar surface exposing the surface of the upper electrode of the stacked structure; And Forming a metal wiring on the upper electrode Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 9, Forming the oxygen diffusion barrier film and the isolation insulating film, Depositing the oxygen diffusion barrier film on the entire surface including the stacked structure; Depositing the isolation insulating film on the oxygen diffusion barrier film; And Chemical mechanical polishing or etch back until the surface of the laminate is exposed Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 9, Forming the oxygen diffusion barrier film and the isolation insulating film, Depositing the oxygen diffusion barrier film on the entire surface including the stacked structure; Forming the oxygen diffusion barrier film in the form of a spacer contacting sidewalls of the laminated structure through a blank etch back; Depositing the isolation insulating film on the entire surface where the oxygen diffusion barrier film is formed; And Chemical mechanical polishing or etch back until the surface of the laminate is exposed Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 9, Forming the laminated structure, Depositing a diffusion barrier film on the interlayer insulating film including the plug; Sequentially depositing a lower electrode and a ferroelectric film on the diffusion barrier film; Depositing an upper electrode on the ferroelectric film; Forming a mask stacked on the upper electrode in the order of a hard mask and a photoresist film; And Etching the upper electrode, the ferroelectric layer, the lower electrode, and the diffusion barrier layer at one time using the mask as an etching mask. Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 12, Depositing the diffusion barrier film, And depositing the diffusion barrier layer, followed by heat treatment or plasma treatment. The method of claim 12, Forming the mask, Forming a hard mask stacked on the upper electrode in the order of the first metal film and the second metal film containing nitrogen; And Forming a photoresist film on the hard mask Method of manufacturing a ferroelectric memory device, characterized in that it comprises a. The method of claim 14, The hard mask is selected from iridium film / TiN, ruthenium film / TiN, platinum film / TaN or iridium film / TaN manufacturing method of the ferroelectric memory device. The method of claim 9 or 12, The lower electrode may be stacked in the order of the first iridium film, the iridium oxide film, and the platinum film, and a second iridium film or an oxygen-deficient IrO phase may be inserted between the iridium oxide film and the platinum film. Manufacturing method. The method of claim 9, And said isolation insulating film is selected from silicon oxides sourced from BPSG, PSG, SOG, or TEOS. The method of claim 9, After the oxygen diffusion barrier film and the isolation insulating film are formed, A method of manufacturing a ferroelectric memory device, characterized in that to perform a heat treatment for crystallization of the ferroelectric film. The method of claim 9, The embedding of the plug in the storage node contact hole, Sequentially depositing a barrier metal and a tungsten film on the entire surface including the storage node contact hole; And Chemical mechanical polishing until the surface of the interlayer dielectric layer is exposed to form a tungsten plug filling the storage node contact hole Method of manufacturing a ferroelectric memory device, characterized in that it comprises a.