KR20040011918A - operation method of pixel cache architecture in three-dimensional graphic accelerator - Google Patents

Abstract

The present invention is to provide a method of operating a pixel cache structure that can significantly reduce the bandwidth buffer and access delay of the frame buffer, the existing fragment information having the same texture coordinate value as the newly input fragment and the pixel cache and Simultaneously accessing and detecting an NT buffer; comparing a depth value of the newly input fragment with a depth value of the detected existing fragment; and as a result of the comparison, a depth value of the newly input fragment If greater than the depth value of the existing fragment, storing the information of the newly entered fragment in the NT buffer, waiting for the next input new fragment to perform, and as a result of the comparison, the newly entered If the depth value of the fragment is smaller than the depth value of the existing fragment, storing the information of the newly entered fragment in the pixel cache Performing a read operation on a color value of a newly input fragment from the pixel cache, performing alpha mixing according to the color value, and storing the alpha mixed color value in the pixel cache. It is done by

Description

Operation method of pixel cache architecture in three-dimensional graphic accelerator}

The present invention relates to a three-dimensional graphics accelerator, and more particularly, to a pixel cache structure having a cache loading method based on a depth test result.

Recently, 3D graphics techniques have been introduced to the PC, and 3D graphics hardware, which can efficiently handle a large number of polygons and special effects such as light effects, has become the mainstream of the market in order to construct a more realistic and colorful screen. .

In particular, as games that provide high realism to users using 3D screens have received great response, research on this has made great progress.

As a result of this research, the performance of 3D graphics hardware has been rapidly developed.

1 is a view showing a three-dimensional graphics process according to the prior art.

As shown in FIG. 1, the 3D application software performs a real-time hardware accelerator in the 3D graphics accelerator 200 through an API (Application Program Interface) 100 and then passes to the display unit 500.

In this case, the 3D graphics accelerator 200 is largely composed of a geometry processing (300) and the rendering (rendering) process (400).

The geometry processing 300 mainly includes a process of converting an object of a 3D coordinate system according to a viewpoint and projecting the object into a 2D coordinate system.

When all three-dimensional data input for one frame is finished through the above process, the color value stored in the frame buffer is sent to the display unit 500 and output.

3D graphic images are mainly composed of points, lines, and polygons, and most 3D rendering processes mainly have a structure of processing triangles at high speed.

Accordingly, the rendering process 400 is pipelined for high performance processing, and is mainly composed of triangle setup processing per-triangle and edge-work processing per edge. walk processing and pixel rasterization processing performed per pixel.

The triangle setup process calculates values to be used in the edgework process and pixel rasterization process for the input triangle.

The edgework process finds the starting point and the ending point of the span along the edge of the triangle.

Where the start and end points of the span are the two intersections of the edges of the triangle for a given scanline, and the span is the set of pixels between these start and end points.

The pixel rasterization process is a part of generating a final color value for pixels constituting the span through interpolation with respect to the span.

Since the present invention proposes the operation of the pixel rasterization process, only the operation of the pixel rasterization process will be described here.

2 illustrates a pipeline process according to a general pixel rasterization process.

Referring to FIG. 2, the input fragment information includes color values generated through interpolation, three-dimensional position coordinates (x, y, z), texture coordinates, and the like.

Then, the texture read / filter unit 401 first reads four or eight texels from the texture cache 419 through the texture coordinates of the input fragment information and performs filtering to perform one filtering. Create a texel. In this case, the texel represents the minimum unit of texture data.

The texture mixer 403 then defines the generated one texel as one color by mixing color values of a plurality of texels read from the texture cache.

Next, the alpha inspection unit 405 inspects transparency, which is an alpha value of a fragment according to a newly input texel.

Subsequently, the depth reading unit 407 and the depth inspecting unit 409 perform a read operation on the depth value of the fragment at the current position from the pixel cache 421, and the depth value of the read fragment and the newly read fragment. Compares the depth value of the input fragment.

As a result of the comparison, if the depth value of the newly input fragment is smaller than the depth value of the current fragment, the depth value of the newly input fragment is stored in the pixel cache 421.

When the depth value of the newly input fragment is larger than the depth value of the current fragment, the newly input fragment is discarded in the pipeline.

Subsequently, the color reading unit 413 performs a read operation on the color value from the pixel cache 421, and mixes the color value read by the read operation by the alpha mixing unit 415 and the texture mixing unit 403. Alpha blending is performed on the color values.

Finally, the color writing unit 417 stores the alpha value mixed in the alpha mixing unit 415 in the pixel cache 421.

This rasterization process takes a significant portion of the total memory transfer in the texture data transfer and frame memory 423 access in the pixel processing pipeline stage, so that not only the bandwidth of the memory but also the delay due to the frame memory 423 access is achieved. Is an important factor.

In recent years, the 3D graphics accelerator 200, which is recently released, uses a cache memory in the middle, as shown in FIG. 2, in order to reduce the amount of texture transfer and frame buffer write. As the number of pixels to be processed increases, the amount of transmission of the texture cache 419 and the pixel cache 421 also increases exponentially.

The memory problem in 3D graphics hardware is one of the important factors affecting the performance improvement, but the analysis of memory data and access tendency and the study of memory structure have been neglected considerably.

In the previously published papers of Mitra and Chiuh, we briefly talk about texture traffic and memory bank utilization in the rasterization phase during dynamic workload analysis. Only researches such as texture prefetching techniques have been published, and the research on pixel caches is incomplete.

Accordingly, an object of the present invention is to provide a pixel cache structure that can significantly reduce the bandwidth problem and access delay of a frame buffer.

1 is a view showing a three-dimensional graphics processing process according to the prior art

2 is a diagram illustrating a pipeline process according to a general pixel rasterization process.

3 is a diagram illustrating a pipeline process according to pixel rasterization processing according to the present invention.

* Explanation of symbols for main parts of the drawings

100: API 200: 3D graphics accelerator

300: Geometry Processing 400: Rendering

401: texture read / filter unit 403: texture mixing unit

405: alpha inspection unit 407: depth reading unit

409: depth inspection unit 411: depth writing unit

413 color reading unit 415 alpha mixing unit

417: color writing section 419: texture cache

421 Pixel Cache 422 NT Buffer

423 frame memory 500 display unit

A characteristic of the method of operating the pixel cache structure in the 3D graphic accelerator according to the present invention for achieving the above object is that the pixel cache and NT to the existing fragment information having the same texture coordinate value as the newly input fragment Simultaneously accessing and detecting a buffer; comparing the depth value of the newly input fragment with the detected depth value of the existing fragment; and as a result of the comparison, the depth value of the newly input fragment If greater than the depth value of the existing fragment, storing the information of the newly entered fragment in the NT buffer, and waiting for the next input of the new fragment execution, the comparison result, the newly entered fragment If the depth value of the segment is smaller than the depth value of the existing fragment, storing the newly input fragment information in the pixel cache; Performing a read operation on a color value of a newly input fragment from a cell cache, performing alpha mixing according to the color value, and storing the alpha mixed color value in a pixel cache. .

In this case, the pixel cache stores only depth data that is successful in the depth check, and only the depth data that has failed in the depth check is stored in the NT buffer.

The data stored in the NT buffer is moved to the pixel cache if the depth check succeeds, and the data stored in the NT buffer remains in the NT buffer.

If the fragment information does not exist in the pixel cache and the NT buffer, the method further includes accessing a frame memory to detect the fragment information and storing the fragment information in the NT buffer. There is this.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of the pixel cache structure in the 3D graphics accelerator according to the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a pipeline process according to pixel rasterization processing according to the present invention.

As shown in FIG. 3, the pixel rasterization pipeline is the same as before, except that the cache structure includes the texture cache 419, the pixel cache 421, and the NT buffer 422.

The texture cache 419 and the pixel cache 421 are configured in a general cache structure, and the NT (Not Tested) buffer is composed of 8 or 16 entries of a fully associated cache.

When configured as described above, the operation of the pixel rasterization pipeline will be described in detail with reference to the accompanying drawings.

4 is a flowchart illustrating the operation of a pixel cache structure according to the present invention.

Referring to FIG. 4, first, when information including color values, three-dimensional position coordinates, and texture coordinates of a newly input fragment is input, the texture read / filter unit 401 selects a plurality of texels for the texture coordinates. A read operation from the texture cache 419 is performed and filtering is performed to generate one texel. And the texture mixing unit 403 mixes a plurality of color values into one (S10).

Subsequently, the alpha inspection unit 405 inspects the transparency of the generated texel, and simultaneously accesses the pixel cache 421 and the NT buffer 422 through the depth reading unit 407 to a position of a newly input fragment. Information of the corresponding existing fragment is detected (S20).

In this case, when there is no desired data in the pixel cache 421 and the NT buffer 422, that is, when the cache access fails, the depth reading unit 407 takes information of a desired existing fragment from the frame memory 423. The data is not stored in the pixel cache 421 but stored in the NT buffer 422 (S50).

The depth checker 409 compares the depth value of the existing fragment read from the pixel cache 421 or the NT buffer 422 with the depth value of the newly input fragment (S40) (S60). ).

That is, when the information of the existing fragment is in the pixel cache 421, the depth value of the existing fragment is read from the pixel cache 421, and the information of the existing fragment is read in the pixel cache 421. If it is not present in the NT buffer 422, the depth value of the existing fragment is read from the NT buffer 422 and then compared with the depth value of the newly input fragment.

As a result of the comparison, when the depth value of the newly input fragment is smaller than the depth value of the existing fragment, information of the newly input fragment through the depth writing unit 411 is transmitted to the pixel cache 421. Save (S80).

As a result of the comparison, when the depth value of the newly input fragment is larger than the depth value of the existing fragment, the information of the newly input fragment is stored in the NT buffer 422 through the depth writing unit 411. (S70).

At this time, in the state where the information of the newly input fragment is stored in the NT buffer 422, the current rendering process is stopped and waits for the next input of the new fragment to be performed (S100).

When the newly input fragment information is stored in the pixel cache 421, the color reading unit 413 performs a read operation on the color value from the pixel cache 421 and the alpha mixing unit 415. In FIG. 1, alpha mixing is performed on the color values read by the read operation and the color values mixed by the texture mixer 403. Subsequently, the color writing unit 417 stores the color value alpha-mixed by the alpha mixing unit 415 in the pixel cache 421 (S90).

In addition, by storing the data that is likely to be reused in the pixel cache while reducing the cache contamination caused by the data whose depth test result has failed, the efficiency of the storage space of the pixel cache can be increased, and the pixel can be improved. Can increase the success rate of the cache.

In other words, it is judged that the possibility of re-use is determined by the depth test result, and the data that has failed the depth check is kept in the NT buffer 422 for a certain time. Since M is small but has a higher probability of reuse than other data not used for depth checking, it is possible to reduce the access delay and bandwidth incurred when the failed data is reused.

Fig. 5 is a graph showing the failure rate of the pixel cache with and without the NT buffer.

In this case, FIG. 5 has an entry size of 64 bytes and 128 bytes, and the NT buffer 422 has a size capable of storing one and two fragment data.

In this case, the size of the pixel cache 423 indicates 16K bytes, 32K bytes and 64K bytes according to the embodiment.

Thus, it can be seen that the failure rate is smaller after using the NT buffer 422 than before, as shown in FIG. In this embodiment, the size of the NT buffer 422 is limited so that one and two fragment data are stored. However, increasing the size of the NT buffer 422 will result in greater efficiency.

As described above, the pixel cache structure of the 3D graphic accelerator according to the present invention has the following effects.

First, the cache success rate is increased by reducing cache pollution by loading only the depth data that is successful at the depth inspection, that is, data that is likely to be used again.

Second, the selection technique for the data to be loaded into the cache is simple. Depth checking is basically a process that is performed in the rendering process, so it is performed by checking only the result thereof, so that the hardware cost is low and the selection time for loading data into the cache is short.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (4)

Simultaneously accessing existing fragment information having the same texture coordinate value as the newly input fragment by accessing the pixel cache and the NT buffer simultaneously; Comparing the depth value of the newly input fragment with the detected depth value of the existing fragment; As a result of the comparison, if the depth value of the newly input fragment is larger than the depth value of the existing fragment, the information of the newly input fragment is stored in the NT buffer, and a new fragment execution is performed next. Waiting for As a result of the comparison, if the depth value of the newly input fragment is smaller than the depth value of the existing fragment, storing the information of the newly input fragment in the pixel cache; Performing a read operation on a color value of a newly input fragment from the pixel cache, performing alpha mixing according to the color value, and storing the alpha mixed color value in the pixel cache. A method of operating a pixel cache structure, characterized in that The method of claim 1, The pixel cache stores only depth data that is successful in depth checking, and only depth data that is failed in depth checking is stored in the NT buffer. The method of claim 1, The data stored in the NT buffer is moved to the pixel cache if the depth check succeeds, and if the depth check fails, the data is stored in the NT buffer. The method of claim 1, If the fragment information does not exist in the pixel cache and the NT buffer, the method further comprises accessing a frame memory to detect the fragment information and storing the fragment information in the NT buffer. How cache structures work