KR20050011463A - Method for forming contact hole of semiconductor device - Google Patents

Abstract

The present invention discloses a method for forming a contact hole in a semiconductor device. The disclosed method includes forming a gate having a hard mask in each of a cell region and a peripheral circuit region on a substrate, sequentially forming a buffer oxide layer, a buffer nitride layer, and a spacer oxide layer on the gate and the substrate; Etching the spacer oxide film, the buffer nitride film, and the buffer oxide film in the peripheral circuit region in order to form a spacer, removing the hard mask of the gate formed in the peripheral circuit region, and removing the spacer oxide film in the cell region. Depositing a spacer nitride film on said gate, sequentially forming a spacer nitride film and a first interlayer dielectric film on said substrate resultant, forming a landing plug between gates of said substrate cell region, Forming a second interlayer insulating film on the first interlayer insulating film including the landing plug; And etching the second interlayer insulating layer and the first interlayer insulating layer to simultaneously form a first contact hole for exposing a landing plug of a cell region and a second contact hole and a third contact hole for exposing a gate and a substrate of a peripheral circuit region, respectively. It includes a step. According to the present invention, the gate hard mask of the peripheral circuit region may be removed in advance to simultaneously form the bit line contact holes of the cell region and the peripheral circuit region.

Description

Method for forming contact hole of semiconductor device

The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of reducing the number of processes.

In recent years, as the integration of devices increases, the size of memory cells decreases gradually, so that margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller, and thus, capacitor contacts must be made smaller.

Also, as semiconductor integrated circuits are highly integrated, alignment margins between a plurality of wiring layers or contact holes are gradually decreasing. Furthermore, in the case where there is no margin in the design rule and the same pattern is repeated like a semiconductor memory cell, a method of reducing the area of the memory cell by forming contact holes in a self-aligned manner has been developed. This is to form a contact hole by using the step of the surrounding structure, because the contact hole of various sizes can be obtained without using a mask by the height of the surrounding structure, the thickness of the insulating material to be formed and the etching method, etc. It is used in a method suitable for the implementation of the semiconductor device to be miniaturized.

However, since the connection portions of the bit line contact holes in the cell region and the peripheral circuit region are different from each other, the degree of etching must also be different.

1 is a cross-sectional view of a bit line contact hole including a gate formed on a semiconductor substrate having a cell region and a peripheral circuit region.

In FIG. 1, the gate 105 formed in each of the cell region A and the peripheral circuit region B of the substrate 101 includes a gate poly film 102, a tungsten silicide film 103, and a nitride film made of a hard mask material. It can be understood as the laminated structure of 104). In general, the spacer of the gate to be formed is not shown.

Here, referring to the conventional method of forming the bit line contact hole, the first contact hole 109, which is the bit line contact hole of the cell region A, is connected to the landing plug 107 formed between the gates. In addition, the second contact hole 110 is etched in the bit line contact hole of the peripheral circuit region B to be connected to the tungsten silicide layer 103 at the lower portion thereof, and the third contact hole 111 is The second interlayer insulating film 108 and the first interlayer insulating film 106 are sequentially etched to be connected to the lower substrate 101.

However, in the bit line contact hole forming method, the first contact hole 110 of the cell region A should not be etched from the nitride film 104, which is a hard mask material of the gate, during the connection process with the landing plug 107. On the other hand, the second contact hole in the peripheral circuit region B must be etched and connected to a portion of the nitride film 104 for contact with the tungsten silicide film 103.

As a result, since the peripheral circuit region and the cell region have different process conditions when forming the bit line contact hole, the process of dividing the bit line contact hole between the cell region and the peripheral circuit region is inevitably performed. There is a problem that causes a cost increase.

Accordingly, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of simplifying a contact hole forming process, which has been made to solve the conventional problems as described above.

1 is a cross-sectional view illustrating a conventional method for forming a contact hole in a semiconductor device.

2A to 2H are cross-sectional views illustrating processes for forming a contact hole in a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

X: cell area Y: peripheral circuit area

201: semiconductor substrate 202: gate poly film

203: tungsten silicide film 204: hard mask

205: gate 206: buffer oxide film

207: buffer nitride film 208: spacer oxide film

209: first photoresist pattern 210: spacer

211: second photosensitive film pattern 212: spacer nitride film

213: first interlayer insulating film 214: landing plug

215: second interlayer insulating film 216: first contact hole

217: second contact hole 218: third contact hole

In order to achieve the above object, the present invention, forming a gate having a hard mask in each of the cell region and the peripheral circuit region on the substrate; Sequentially forming a buffer oxide film, a buffer nitride film, and a spacer oxide film on the gate and the substrate; Etching the spacer oxide film, the buffer nitride film, and the buffer oxide film in the peripheral circuit region in order to form a spacer; Removing the hard mask of the gate formed in the peripheral circuit area; Removing the spacer oxide film of the cell region; Depositing a spacer nitride film on the gate; Sequentially forming a spacer nitride film and a first interlayer insulating film on the substrate resultant; Forming a landing plug between gates of the substrate cell region; Forming a second interlayer insulating film on the first interlayer insulating film including the landing plug; And etching the second interlayer insulating layer and the first interlayer insulating layer to simultaneously form a first contact hole for exposing a landing plug of a cell region and a second contact hole and a third contact hole for exposing a gate and a substrate of a peripheral circuit region, respectively. It provides a method for forming a contact hole in a semiconductor device comprising the step of.

Here, the hard mask is made of a nitride film, and removing the hard mask of the peripheral circuit region is performed using H3PO4.

In addition, the remaining amount of the spacer oxide film when forming the spacer of the peripheral circuit region is 30 ~ 70Å thickness.

Further, the hard mask of the cell region has a residual amount of at least 1000 GPa after the formation of the contact hole.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention.

Referring to FIG. 2A, a gate poly film 202, a tungsten silicide film 203, and a hard mask 204 are sequentially deposited on a semiconductor substrate 201 having a cell region X and a peripheral circuit region Y. After that, the gate 205 is formed by etching it.

Referring to FIG. 2B, a buffer oxide film 206, a buffer nitride film 207, and a spacer oxide film 208 are sequentially formed on the gate 205 and the substrate 201.

Referring to FIG. 2C, the first photoresist layer pattern 209 exposing the peripheral circuit region is formed, and then the spacer oxide layer 208, the buffer nitride layer 207, and the buffer oxide layer 206 in the peripheral circuit region are hardened. The mask 204 is sequentially etched to expose the spacers 210. At this time, the remaining thickness (Rox: Remain Oxide) of the buffer oxide film 206 is etched with a target of 30 ~ 70Å.

Referring to FIG. 2D, the hard mask 204 of the peripheral circuit region gate is removed by etching with H 3 PO 4 solution, and then ion implanted with N + or P + to form a drain / source. Here, since the remaining thickness of the buffer oxide film 206 is 30 ~ 70Å, it protects the substrate during the hard mask etching and does not block the doping of ions during ion implantation.

Referring to FIG. 2E, the first photoresist pattern of the cell region is removed, and then cleaned on the entire surface of the substrate. At this time, the spacers of the left and right side portions of the etched hard mask are removed.

Next, the second photoresist layer pattern 211 exposing the cell region is formed and the spacer oxide layer in the cell region is removed.

Referring to FIG. 2F, a spacer nitride film 212 is formed on the gate 205 including the buffer nitride film 207 in the cell region and the spacer 210 in the peripheral circuit region. Then, a first interlayer insulating film 213 is formed on the substrate resultant.

Referring to FIG. 2G, a contact hole (not shown) is formed by etching between gates 205 of a cell region, and a conductive film is deposited to fill the contact hole. Next, the landing product 214 is formed by CMPing the substrate resultant. Then, a second interlayer insulating film 215 is formed on the substrate resultant.

Referring to FIG. 2H, a portion of the second interlayer dielectric layer 215 and the first interlayer dielectric layer 213 may be etched to expose the landing plug 214 and the tungsten silicide in the peripheral circuit region. The second contact hole 217 and the third contact hole 218 exposing the 203 and the substrate 201 are formed at the same time to form a contact hole of the semiconductor device according to the present invention.

In general, the process conditions for forming the bit line contact holes in the cell region and the peripheral circuit region are different. In detail, the bit line contact hole of the cell region is connected to the landing plug formed between the gates, and the bit line contact hole of the peripheral circuit region is connected to the tungsten silicide layer of the gate. Therefore, the hard mask of the gate formed in the cell region should not be etched, while the hard mask of the gate formed in the peripheral circuit region should be removed.

Therefore, in the present invention, since the hard mask 204 of the gate 205 formed in the peripheral circuit region Y is removed in advance, the etching process conditions are the same, so that the cell region X and the peripheral circuit region Y Bit line contact holes can be formed at the same time. In addition, since the remaining amount of the gate hard mask 204 in the cell region is about 1000 mV when the second contact hole 217 is formed, there is no problem.

As described above, when the gate hard mask of the peripheral circuit region is removed in advance, contact holes of the cell region and the peripheral circuit region may be simultaneously formed under the same process conditions.

Therefore, the processes that have been separately performed can be combined to simplify the bit line contact process and to improve productivity.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (4)

Forming a gate having a hard mask in each of the cell region and the peripheral circuit region on the substrate; Sequentially forming a buffer oxide film, a buffer nitride film, and a spacer oxide film on the gate and the substrate; Etching the spacer oxide film, the buffer nitride film, and the buffer oxide film in the peripheral circuit region in order to form a spacer; Removing the hard mask of the gate formed in the peripheral circuit area; Removing the spacer oxide film of the cell region; Depositing a spacer nitride film on the gate; Sequentially forming a spacer nitride film and a first interlayer insulating film on the substrate resultant; Forming a landing plug between gates of the substrate cell region; Forming a second interlayer insulating film on the first interlayer insulating film including the landing plug; And Etching the second interlayer insulating film and the first interlayer insulating film to simultaneously form a first contact hole exposing a landing plug of a cell region and a second contact hole exposing a gate and a substrate of a peripheral circuit region and a third contact hole, respectively; Method for forming a contact hole in a semiconductor device comprising the step. The method of claim 1, wherein the hard mask is formed of a nitride film, and the hard mask of the peripheral circuit region is removed using H 3 PO 4. The method of claim 1, wherein the remaining amount of the spacer oxide film is 30 to 70 Å in thickness when forming the spacers in the peripheral circuit region. 2. The method of claim 1, wherein the hard mask of the cell region has a residual amount of at least 1000 GPa after the formation of the contact hole.