KR20050011984A - Synchronous memory device for deleting glitch of data align signal - Google Patents

Abstract

The present invention is to provide a synchronous memory device that can align the input data stably by removing the glitch phenomenon of the falling align signal and the rising align signal for aligning the data input from the synchronous memory device, To this end, the present invention includes a data align signal generation unit for generating and outputting a rising align signal and a falling align signal, respectively, synchronized with the rising edge and the falling edge of the input data strobe signal; A data aligning unit which aligns the data continuously input in synchronization with the rising align signal and the falling align signal and outputs the data to the memory core area; And outputting a control signal for controlling the data align signal generation unit so that the rising align signal and the falling align signal can be generated and output only during a period in which the data is input, and activated in response to the falling align signal. And a data alignment signal ripple preventing portion outputting the control signal to be deactivated in response to the rising alignment signal.

Description

SYNCHRONOUS MEMORY DEVICE FOR DELETING GLITCH OF DATA ALIGN SIGNAL

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous memory device in which data is input and output in synchronization with an operation clock, and more particularly, to a circuit for preventing ripple of a data alignment signal for aligning input data.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from a memory chip has been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high-speed operation.

However, since the DL memory device needs to export or receive two data in one clock period, the data access method used in the conventional SDR synchronous memory device cannot be used to effectively perform this.

If the clock cycle is about 10 nsec, subtracting the rise and fall time (approximately 0.5 × 4 = 2) and the time to meet other specifications, etc., the two data continuously for about 6 nsec or less. This process is insufficient to be performed inside the memory device. Therefore, the memory device inputs and outputs data at the rising edge and the falling edge of the clock only when data is sent to or received from the outside, and is processed in synchronization with one edge of the clock in the memory device.

Therefore, a new data input / output method is required to receive data from a memory device and transmit the data to an internal core area or output data transmitted from the core area to the outside.

To do this, the data input buffer of the digital memory device prefetches and aligns two or four bits of data synchronized with the rising and falling edges, and then synchronizes the even or odd data with the rising edge of the main clock. To the inner core area.

On the other hand, when data is input to implement accurate timing of data input / output, a data strobe signal (hereinafter referred to as DQS) together with the data signal from a CPU or a memory controller external to the memory device. Is entered together.

1 is a block diagram showing a synchronous memory device according to the prior art.

Referring to FIG. 1, a synchronous memory device according to the related art includes a data input buffer 10 for receiving and buffering data input through a data input pad DQ PAD, and data buffered in the data input buffer 10. A data input latch unit 20 for latching the data, and a data alignment unit 30 for aligning the data latched by the data input latch unit 20 with 2 bits or 4 bits and outputting them (gio_od0, gio_od1, gio_ev0, gio_ev1); The data alignment unit (DQS signal input buffer 40) receives and buffers the DQS signal through the data strobe signal input pad (DQS pad) and the DQS signal (DQS_b) buffered in the DQS signal input buffer 40. A data align signal generator 50 for outputting a rising align signal dsrz and a falling align signal dsfz for aligning data at 30), and a rising align output from the data align signal generator. Incoming signal (dsrz) and pole And a data alignment signal anti-ripple prevention unit 60 for preventing the ring alignment signal dsfz from being rippled.

FIG. 2 is a circuit diagram showing the DQS signal input buffer 40 shown in FIG.

Referring to Figure 2, the DQS signal input buffer 40 is configured in the form of a conventional differential amplifier, compares the potential of the DQS signal with respect to the input reference voltage (Vref) and the output signal (DQS_b) according to the compared state ) Will be printed.

3 is a circuit diagram illustrating the data alignment signal generation unit 50 shown in FIG. 1.

Referring to FIG. 3, the data alignment signal generator 50 buffers the signal DQS_b output from the DQS signal input buffer 40 to the node A, and the inverters I1 and I2. Inverters I3, I4, and I5 which invert the signal of (A) and output the rising alignment signal dsrz, and inverts and transmits the signal of the node A, but selectively by the anti-ripple signal disdsz. Inverters MP3, MP4, MN4, MN5 delivered to node B, and inverters I6, 7, and I8 that invert the signal of node B and output the falling alignment signal dsfz.

FIG. 4 is a block diagram showing the data alignment signal ripple prevention part 60 shown in FIG.

Referring to FIG. 4, the data alignment signal ripple prevention unit 60 may include a data alignment signal detection unit for detecting a state of a falling alignment signal dsfz output from the data alignment signal generator 50. 62), an anti-ripple signal reset controller 61 for receiving a clock signal clkp4 buffering the operation clock of the synchronous memory device and resetting the anti-ripple signal disdsz, and a glee prevention signal reset controller 61. And a ripple prevention signal output unit 63 for combining the signal output from the data alignment signal detection unit 62 to output the ripple prevention signal 63 to the data alignment signal generation unit 50.

FIG. 5 is a circuit diagram showing each block of the data alignment signal ripple prevention unit 63 shown in FIG.

Referring to FIG. 5, the ripple prevention signal reset control unit 61 of the data alignment signal ripple prevention unit 63 receives a clock signal clkp4 and outputs an output signal at a low level at every predetermined interval to ripple. It is configured to turn on the MOS transistor MP5 of the prevention signal output section 63. Here, the switches S1, S2, S3, and S4, the inverters I11 and I12, and the inverters I13 and I14 turn on the MOS transistor MP5 of the anti-ripple signal output unit 63 using a clock signal. It was used as an option to adjust the interval.

The data alignment signal detection unit 62 is configured to turn on the MOS transistor MN6 of the anti-ripple signal output unit 63 by receiving the falling alignment signal dsfz and outputting the output signal at a high level every predetermined period. do.

When the output signal of the anti-ripple signal reset control unit 61 is at a low level, the anti-ripple signal output unit 63 latches the output signal to a high level to output the data to the data alignment signal generator and detects the data alignment signal. When the output signal of the ripple prevention signal reset control unit 61 is at the high level while the output signal of the unit 62 is at the high level, the ripple prevention signal disdsz is activated to be output at a high level.

The enable signals are generated when the write command is input to allow the data alignment signal ripple prevention unit 60 to operate.

In addition, the control signals cl6 and cl5 are signals for disabling the ripple prevention signal disdsz at a high level and outputting the signal at a high level at all times. This is because ripple of the data alignment signal does not occur at high frequencies.

6 is a waveform diagram showing a problem of a synchronous memory device according to the prior art. Hereinafter, operations and problems of the conventional memory device will be described with reference to FIGS. 1 to 6.

First, at every point in time at which the DQS signal is transitioned and input, the data is input to the data input buffer 10 through the data pad (DQS pad), buffered, and latched by the data input latch unit 20.

The DQS signal input buffer 40 compares the input DQS signal with the reference signal Vref and outputs the same to the data alignment signal generator 50. The data alignment signal generator 50 outputs the rising alignment signal dsrz and the DQS signal input buffer 40 synchronized with the rising transition point of the signal DQS_b output from the DQS signal input buffer 40. The falling alignment signal dsfz synchronized with the falling transition point of the DQS_b is output to the data alignment unit 30.

The data alignment unit 30 synchronizes the data latched by the data input latch unit 20 with the rising alignment signal dsrz and the falling alignment signal dsfz, and then synchronizes the operation clock with the buffered signal. Output to the memory core area.

Meanwhile, the DQS signal is clocked only while data is input and input through the data strobe signal input pad (DQS pad). The DQS signal should be maintained at a constant level after the data input is completed.

However, the DQS signal may be rippled and input even after the data input is completed due to termination of the memory module.

If the DQS signal is rippled even after the data is inputted, an unwanted falling alignment signal dsfz or a rising alignment signal dsrz occurs in the data alignment signal generation unit 50, causing the data alignment unit to ripple. Output to (20). An error may occur in the data alignment unit 30 due to an undesired falling alignment signal dsfz or a rising alignment signal dsrz.

To solve this problem, in the memory device, the data alignment signal ripple prevention unit 60 is provided such that the polling alignment signal dsfz or the rising alignment signal dsrz is input to the data alignment unit only during a data input period. have.

As shown in FIG. 3, the data alignment signal generator 50 generates a falling alignment signal dsfz using the signal DQS_b output from the DQS signal input buffer 40 and outputs the falling alignment signal dsfz to the data alignment unit. When the anti-ripple signal disdsz is activated at a low level and input, the polling alignment signal dsfz is no longer output.

4 and 5, the operation of the data alignment signal ripple prevention unit will be described. The ripple prevention signal reset control unit 61 activates the output signal to the high level whenever the clock signal clkp4 transitions to the low level. In addition, the data alignment signal detector 62 activates the output signal at a high level whenever the falling alignment signal dsfz transitions to a low level.

The anti-ripple signal output unit 63 outputs the anti-ripple signal disdsz when both the output signal of the anti-ripple signal reset control unit 61 and the output signal of the data alignment signal detection unit 62 are activated to a high level. Output at low level.

In addition, when the output signal of the anti-ripple signal reset control unit 61 is deactivated to a low level, the anti-ripple signal output unit 63 deactivates the anti-ripple signal disdsz to a high level and outputs the anti-ripple signal.

On the other hand, if the data alignment signal ripple prevention unit 60 as described above is configured, as shown in Figure 6 to the ripple prevention signal (disdsz) output from the data alignment signal ripple prevention unit 60 Glitch occurs like this (see X, Y in Fig. 6).

This is a period in which the rising alignment signal dsrz is at a high level when the morph transistor MN5 of the data alignment signal generator 50 is turned on after the ripple prevention signal disdsz is reset to a low level. In this case, the morph transistor MP3 of the data alignment signal generation unit 50 is turned on to cause a glitch phenomenon in the falling alignment signal dsfz.

When the polling alignment signal dsfz causes a glitch, the timing of processing the data to be aligned by the polling alignment signal dsfz is reduced, which makes it impossible to align the data stably. There is an error in the operation of the device.

The present invention has been proposed to solve the above problems, and it is possible to stably align the input data by eliminating the glitch of the falling align signal or the rising align signal for aligning the data input from the synchronous memory device. It is an object of the present invention to provide a synchronous memory device.

1 is a block diagram showing a synchronous memory device according to the prior art;

FIG. 2 is a circuit diagram showing a DQS signal input buffer shown in FIG.

FIG. 3 is a circuit diagram showing a data alignment signal generation unit shown in FIG. 1; FIG.

FIG. 4 is a block diagram showing a data alignment signal ripple preventing portion shown in FIG.

Fig. 5 is a circuit diagram showing each block of the data alignment signal ripple preventing portion shown in Fig. 4;

Fig. 6 is a waveform diagram showing a problem of the synchronous memory device according to the prior art.

Figure 7 is a block diagram of a synchronous memory device according to a preferred embodiment of the present invention.

FIG. 8 is a block diagram showing a data alignment signal ripple preventing portion shown in FIG.

FIG. 9 is a circuit diagram showing each block of the data alignment signal ripple preventing portion shown in FIG. 8; FIG.

FIG. 10 is a waveform diagram showing the operation of the memory device shown in FIG.

* Explanation of symbols on the main parts of the drawings

I1 ~ I47: Inverter

NOR1 ~ NOR4: NORGATE

ND1 to ND3: NAND Gate

T1 ~ T2: Transmission Gate

In order to achieve the above object, the present invention provides a data align signal generation unit for generating and outputting a rising align signal and a falling align signal, respectively, synchronized with a rising edge and a falling edge of an input data strobe signal; A data aligning unit which aligns the data continuously input in synchronization with the rising align signal and the falling align signal and outputs the data to the memory core area; And outputting a control signal for controlling the data align signal generation unit so that the rising align signal and the falling align signal can be generated and output only during a period in which the data is input, and activated in response to the falling align signal. And a data alignment signal ripple preventing portion outputting the control signal to be deactivated in response to the rising alignment signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

7 is a block diagram of a synchronous memory device according to a preferred embodiment of the present invention.

Referring to FIG. 7, the synchronous memory device according to the present exemplary embodiment includes a rising alignment signal dsrz synchronized to a rising edge and a falling edge of the data strobe signal DQS input through a data strobe signal input pad DQS pad. ) And a data alignment signal generator 500 for generating and outputting a falling alignment signal dsfz, respectively, and a rising alignment signal dsrz and polling of data continuously inputted through a data input pad DQS pad. The data aligning unit 300 aligns in synchronization with the alignment signal dsfz and outputs to the memory core area (gio_od0, gio_od1, gio_ev0, gio_ev1), and the rising alignment signal dsrz only during the data input period. And outputting a control signal disdsz for controlling the data alignment signal generation unit 500 so that the polling alignment signal dsfz is generated and outputted, and is activated in response to the polling alignment signal dsfz. And a ranging alignment signal (dsrz) data alignment signal rippling prevention unit 600 for outputting the control signal so that in response to a disable.

The data input buffer 100 and the data input latch unit 200 are blocks for buffering, latching, and transmitting the data input through the data input pad DQ pad to the data alignment unit 300. In addition, the DQS signal input buffer 400 is a block for comparing the DQS signal DQS inputted through the DQS input pad DQ pad with the reference signal Vref and then transmitting the data to the data alignment signal generator 500. to be.

FIG. 8 is a block diagram illustrating a data alignment signal ripple prevention unit illustrated in FIG. 7.

Referring to FIG. 8, the data alignment signal ripple prevention unit 600 controls the data alignment signal detection unit to control the control signal disdsz to be activated in response to the activation of the falling alignment signal dsfz. 620, a ripple prevention signal reset controller 610 for controlling the control signal disdsz to be deactivated in response to the activation of the rising alignment signal dsrz, and the data alignment signal detection unit 620. And an anti-ripple signal output unit 630 for outputting a control signal disdsz in response to the control of the anti-ripple signal reset controller 610.

FIG. 9 is a circuit diagram illustrating each block of the data alignment signal ripple prevention unit shown in FIG. 8.

Referring to FIG. 9, the ripple prevention signal reset control unit 610 of the data alignment signal ripple prevention unit 600 receives a clock signal clkp4 and outputs an output signal at a high level at a predetermined interval to ripple. The MOS transistor MN8 of the prevention signal output unit 630 is turned on, and on the other hand, when the rising align signal dsrz transitions to a high level by receiving the rising align signal dsrz, the MOS transistor (MN8) is turned on. MP8) is turned on. Here, the switches S9, S10, S11, and S12, the inverters I31, I32, and the inverters I35, I36 are connected to the anti-ripple signal output unit 630 by using a clock signal used as an operation clock of the memory device. It is used as an option to adjust the section to turn on the MOS transistor (MP8, MN8).

The data alignment signal detector 620 receives the polling alignment signal dsfz and outputs an output signal at a high level every predetermined period to turn on the MOS transistor MN9 of the anti-ripple signal output unit 630. It is composed.

When the morph transistor MP8 is turned on by the output signal of the anti-ripple signal reset control unit 610, the anti-ripple signal output unit 630 outputs a high level anti-ripple signal disdsz by latching it. When the morph transistors MN8 and MN9 are turned on by the output signals of the anti-ripple signal reset controller 610 and the data alignment signal detector 620, the anti-ripple signal disdsz is output at a low level. It is configured to.

FIG. 10 is a waveform diagram illustrating an operation of the memory device illustrated in FIG. 7. Hereinafter, the operation of the synchronous memory device according to the present embodiment will be described with reference to FIGS. 7 to 10.

First, at every point in time when the DQS signal DQS is transitioned and input, the data is input to the data input buffer 100 through the data pad DQS pad, buffered, and latched by the data input latch unit 20.

Meanwhile, the DQS signal input buffer 400 compares the input DQS signal DQS with the reference signal Vref and outputs the same to the data alignment signal generator 500. The data alignment signal generator 500 outputs the rising alignment signal dsrz and the DQS signal input buffer 40 synchronized with the rising transition point of the signal DQS_b output from the DQS signal input buffer 400. The falling alignment signal dsfz synchronized with the falling transition point of the DQS_b is generated and output to the data alignment unit 30.

The data alignment unit 300 aligns the data latched by the data input latch unit 200 in synchronization with the rising alignment signal dsrz and the falling alignment signal dsfz, and then outputs the data to the memory core area (gio_od0, gio_od1). , gio_ev0, gio_ev1). Although not shown, the signals gio_od0, gio_od1, gio_ev0, and gio_ev1 output to the memory core region are output in synchronization with the clock signal buffered in the operation clock of the memory device.

Meanwhile, the DQS signal DQS is clocked only while data is input and input through the data strobe signal input pad DQS pad. The DQS signal DQS should be maintained at a constant level after the data input is completed.

However, the DQS signal may be rippled and input even after the data input is completed due to termination of the memory module. As a result, an error may occur in the data alignment unit 30 due to an unwanted polling alignment signal dsfz or a rising alignment signal dsrz.

To solve this problem, in the memory device, the data alignment signal ripples such that the falling alignment signal dsfz or the rising alignment signal dsrz is input to the data alignment unit 300 only during a data input period. The prevention part 600 is provided.

The data alignment signal generator 500 is configured to output the falling alignment signal dsfz and the rising alignment signal dsrz in response to a control signal output from the data alignment signal ripple preventing unit 600.

8 and 9, the operation of the data alignment signal ripple prevention unit 600 will be described. The ripple prevention signal reset controller 610 turns on the MOS transistor MN8 of the ripple prevention signal output unit 630 whenever the clock signal clkp4 buffering the operation clock transitions to a low level. Each time the rising align signal dsrz transitions to a low level, the MOS transistor MP8 of the anti-ripple signal output unit 630 is turned on.

In addition, the data alignment signal detecting unit 620 activates the output signal to a high level whenever the falling alignment signal dsfz transitions to a low level so that the morph transistor MN9 of the anti-ripple signal output unit 630 is activated. Turn on.

When the morph transistor MP8 is turned on by the output signal of the anti-ripple signal reset control unit 610, the anti-ripple signal output unit 630 latches the high level anti-ripple signal disdsz. Outputs the ripple prevention signal disdsz to a low level when the MOS transistors MN8 and MN9 are turned on by the output signals of the ripple prevention signal reset controller 610 and the data alignment signal detector 620. Enable it and print it out. As a result, the control signal output from the data alignment signal ripple prevention part 600 is output in synchronization with the clock signal clkp4.

In the present invention, unlike the prior art, the anti-ripple signal reset controller 610 outputs not only the clock signal clkp4 but also information about the transition time of the rising alignment signal dsrz, and the anti-ripple signal output unit 630. ) Outputs the control signal disdsz at a high level using this (see Z in FIG. 10).

Therefore, unlike the prior art, the control signal is kept low for a predetermined period while being reset to high level, and thus the glitches of the falling alignment signal dsfz output from the data alignment signal generator 500 are changed. It does not occur (see Z in Fig. 10).

When the glitch of the falling alignment signal dsfz does not occur, the operation of aligning the input data and outputting the data to the memory core does not cause an error, thereby enabling stable operation of the memory device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the glitch phenomenon of the data alignment signal for aligning the data input from the synchronous memory device is eliminated, thereby preventing malfunction due to the glitch phenomenon, thereby enabling stable data alignment.

Claims (4)

A synchronous memory device for inputting and outputting data in synchronization with an operation clock, A data align signal generator for generating and outputting a rising align signal and a falling align signal synchronized with the rising edge and the falling edge of the input data strobe signal; A data aligning unit which aligns the data continuously input in synchronization with the rising align signal and the falling align signal and outputs the data to the memory core area; And Outputs a control signal for controlling the data align signal generation unit so that the rising align signal and the falling align signal can be generated and output only during a period in which the data is input, and is activated in response to the falling align signal. Data alignment signal ripple prevention unit for outputting the control signal to be deactivated in response to the rising alignment signal A synchronous memory device having a. The method of claim 1, The data alignment signal ripple prevention part A data alignment signal detector configured to control the control signal to be activated in response to the activation of the falling alignment signal; A ripple prevention signal reset control unit controlling the control signal to be deactivated in response to the activation of the rising alignment signal; And And an anti-ripple signal output unit configured to output the enable signal under the control of the data alignment signal detector and the anti-ripple signal reset controller. The method of claim 1, The data alignment signal ripple prevention part And receiving the control signal and outputting the control signal in synchronization with the operation clock. The method of claim 1, And a data strobe signal input buffer configured to receive and buffer the data strobe signal and output the buffered data strobe signal to the data alignment signal generator.