KR20050045179A - Method for forming plug of semiconductor device - Google Patents

Abstract

The present invention discloses a method of forming a plug of a semiconductor device which increases a contact area between an active region and a contact hole in a semiconductor manufacturing process using a borderless contact technology. The disclosed method includes providing a silicon substrate having an active region and a field region; Forming a trench isolation device in a field region of the silicon substrate; Recessing a part thickness of the device isolation layer; Forming a single crystal silicon film on the junction between the recessed device isolation layer and the silicon substrate by a selective epitaxial growth method; Dry etching the single crystal silicon layer to form a silicon spacer at a junction between the recessed device isolation layer and the silicon substrate; Forming a transistor by forming a gate electrode and a source / drain region on an active region of the silicon substrate; Selectively forming a silicide layer on surfaces of the gate electrode, source / drain regions, and silicon spacers; Sequentially forming a nitride film and an interlayer insulating film on the resultant product; Selectively etching portions of the interlayer dielectric layer and the nitride layer to form a borderless contact hole simultaneously exposing the source / drain region and the device isolation layer including the silicon spacers; And filling the borderless contact hole with a conductive layer to form a plug.

Description

TECHNICAL FOR FORMING PLUG OF SEMICONDUCTOR DEVICE

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a plug of a semiconductor device for increasing a contact area between a borderless contact hole and an active region.

As the integration of semiconductor devices proceeds, a decrease in cell size is accompanied, and a contact area is reduced by such a decrease in cell size, thereby making it difficult to secure contact margins. In recent years, contact margins have been secured by applying borderless contact technology. Here, the borderless contact technique is a technique of utilizing not only the junction region but also a part of the device isolation film as a contact region when forming a contact with the junction region.

A plug forming method of a conventional semiconductor device using the borderless contact technology will be briefly described with reference to FIG. 1 as follows.

In the conventional method of forming a plug of a semiconductor device, as shown in FIG. 1, first, a device isolation film 2 that defines an active region in place of a silicon substrate 1 through a known shallow trench isolation (STI) process is used. Form. Then, the gate electrode 4 having the gate oxide film 3 on the active region of the silicon substrate 1 and the spacers 5 on both sides, and the source / drain regions 6 on the lower substrates on both sides of the gate electrode 4. ) To form a transistor. In order to reduce contact resistance, a salicide process is performed to selectively form a silicide layer 7 on the surfaces of the gate electrode 4 and the source / drain region 6. Subsequently, a nitride film 8 is deposited on the resultant with a uniform thickness, and an interlayer insulating film 9 is formed on the nitride film 8.

Next, a portion of the interlayer insulating film 9 is selectively etched, and subsequently, the portion of the nitride film 8 exposed by etching the interlayer insulating film 9 is etched, so that the source / drain region 6 and the device isolation film ( A borderless contact hole h ₁ exposing 2) is simultaneously formed, and then a plug 10 is formed by filling a conductive film in the borderless contact hole h ₁ .

However, in the related art, since a fine process of controlling a contact hole having a size of 0.13 μm or less is generally performed, the contact area of the active area may be reduced when the contact area is adjusted in the contact hole. The problem is that the contact margin is reduced and the characteristics of the device are degraded.

Accordingly, the present invention has been made to solve the above problems, and after the recessed device isolation film formed through the STI process, selective epitaxial growth at the junction between the recessed device isolation film and the silicon substrate (Selective) A semiconductor device capable of increasing the area of the active region by forming a silicon spacer by the epitaxial growth method, and increasing the contact area between the borderless contact hole and the active region to secure contact margins and improve device characteristics. The purpose is to provide a method for forming a plug.

The method for forming a plug of a semiconductor device of the present invention for achieving the above object comprises the steps of providing a silicon substrate having an active region and a field region; Forming a trench isolation device in a field region of the silicon substrate; Recessing a part thickness of the device isolation layer; Forming a single crystal silicon film on the junction between the recessed device isolation layer and the silicon substrate by a selective epitaxial growth method; Dry etching the single crystal silicon layer to form a silicon spacer at a junction between the recessed device isolation layer and the silicon substrate; Forming a transistor by forming a gate electrode and a source / drain region on an active region of the silicon substrate; Selectively forming a silicide layer on surfaces of the gate electrode, source / drain regions, and silicon spacers; Sequentially forming a nitride film and an interlayer insulating film on the resultant product; Selectively etching portions of the interlayer dielectric layer and the nitride layer to form a borderless contact hole simultaneously exposing the source / drain region and the device isolation layer including the silicon spacers; And filling the borderless contact hole with a conductive layer to form a plug.

Here, when the device isolation layer is recessed, a thickness of about 50 to 1,000 Å is recessed, and the layer is wetted by using any one of diluted HF, BOE, HCl, NH 4 F and NH 4 OH solutions, or CxHyFz (x , y, z is 0, or natural water) and is recessed dry using a mixed gas in which at least one of Cl2, HBr, BCl3, N2, O2, Ar, and He gas is added. In addition, the single crystal silicon film is formed to a thickness of 20 ~ 900Å, when dry etching the single crystal silicon film, a gas containing a halogen group element is used as an etching gas. In addition, the conductive film is formed of any one of a single structure of any one of SiO 2, Si 3 N 4, and a SiON film, and any two or more laminated structures.

According to the present invention, by increasing the area of the active region by recessing the device isolation film formed through the STI process and forming a silicon spacer at the junction of the recessed device isolation film and the silicon substrate by a selective epitaxial growth method, The characteristics of the device can be improved by increasing the contact area between the lease contact hole and the active region.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views of respective processes for describing a method of forming a plug of a semiconductor device according to an exemplary embodiment of the present invention.

In the method for forming a plug of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 2A, first, a pad oxide film 12 and a pad nitride film 13 are formed on a silicon substrate 11 having an active region and a field region. Form in turn.

Then, as illustrated in FIG. 2B, a photoresist pattern 14 is formed on the pad nitride layer 13 to expose the field region of the silicon substrate 11. Subsequently, using the photoresist pattern 14 as an etch barrier, the pad nitride layer 13, the pad oxide layer 12 below the silicon substrate 11, and the silicon substrate 11 are sequentially etched. As a result, the silicon substrate 11 is etched. The trench 15 is formed in the field region of the trench.

In addition, as shown in FIG. 2C, in a state in which the photoresist pattern is removed, an oxide film, for example, an HDP (High Density Plasma) oxide film having excellent embedding characteristics is deposited on the resultant to completely fill the trench, and subsequently, the HDP. The oxide film is chemically mechanical polished (CMP) to form a trench isolation device 16 in the field region of the silicon substrate 11.

Then, the pad nitride film and the pad oxide film are removed. Then, a portion of the surface of the device isolation film 16, for example, about 50 to 1,000 GPa is recessed. Here, the device isolation layer is wet-recessed using any one of diluted HF (Diluted HF), BOE (Buffered Oxide Etchant), HCl, NH4F and NH4OH solution, or CxHyFz (x, y, z is 0, Alternatively, natural water) is recessed dry using a mixed gas in which at least one of Cl2, HBr, BCl3, N2, O2, Ar, and He gas is added.

Next, as shown in FIG. 2D, a single crystal silicon film (not shown) is formed at a junction between the recessed device isolation layer 16 and the silicon substrate 11 by a selective epitaxial growth method. The single crystal silicon film is subjected to dry etching using a plasma to form a silicon spacer 18 at a junction between the recessed device isolation layer 16 and the silicon substrate 11. Here, the single crystal silicon film is formed to a thickness of 20 ~ 900Å, the dry etching of the single crystal silicon film using a gas containing a halogen group element of the periodic table such as F, Cl as an etching gas. On the other hand, the formation of the silicon spacer by selective epitaxial growth and dry etching of the single crystal silicon film is repeated two or more times to further increase the area of the active region.

Although not shown in the drawing, in order to remove the layer damaged by the plasma during the dry etching of the single crystal silicon film, a light dry etching, a light oxide film forming and a removing process are sequentially performed on the damaged layer.

Then, as shown in FIG. 2E, the gate electrode 20 having the gate oxide layer 19 and the spacers 21 on both sides of the gate electrode 20 and the lower sides of the gate electrode 20 on the active region of the silicon substrate 11. Source / drain regions 22 are formed on the substrate to form transistors. In order to reduce contact resistance, a salicide process is performed to selectively select a silicide layer 23 on surfaces of the gate electrode 20, the source / drain regions 22, and the silicon spacers 18. To form. Subsequently, a nitride film 24 and an interlayer insulating film 25 are sequentially formed on the resultant product.

Next, a portion of the interlayer insulating film 25 is selectively etched, and subsequently, the nitride film 24 exposed by the interlayer insulating film 25 is etched, so that the source / drain region 22 and the silicon spacer ( A borderless contact hole h ₂ is formed to simultaneously expose the device isolation layer 16 including the 18, and the plug 26 is formed by filling the borderless contact hole h ₂ with a conductive film (not shown). do. The conductive film may be formed of a single structure of any one of SiO 2, Si 3 N 4, and SiON, or may be formed of at least two of the SiO 2, Si 3 N 4, and SiON films.

The semiconductor device according to the present invention manufactured through the above process is active by recessing the device isolation film formed through the STI process and forming a silicon spacer by a selective epitaxial growth method at the junction of the recessed device isolation film and the silicon substrate. In addition to increasing the area of the region, the contact area between the borderless contact hole and the active region can be increased to improve the device characteristics.

As described above, the present invention increases the area of the active region by recessing the device isolation layer formed through the STI process and forming a silicon spacer at a junction between the recessed device isolation layer and the silicon substrate by a selective epitaxial growth method. At the same time, a contact margin can be secured by increasing the contact area between the borderless contact hole and the active region, and the characteristics of the device can be improved.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1 is a cross-sectional view for explaining a plug forming method of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of forming a plug of a semiconductor device according to an embodiment of the present invention.

Explanation of symbols on main parts of drawing

11 silicon substrate 12 pad oxide film

13 pad nitride film 14 photosensitive film pattern

15 trench 16 device isolation film

18 silicon spacer 19 gate oxide film

20 gate electrode 21 spacer

22 source / drain region 23 silicide layer

24 nitride film 25 interlayer insulating film

26: plug h₂: borderless contact hole

Claims (7)

Providing a silicon substrate having an active region and a field region; Forming a trench isolation device in a field region of the silicon substrate; Recessing a part thickness of the device isolation layer; Forming a single crystal silicon film on the junction between the recessed device isolation layer and the silicon substrate by a selective epitaxial growth method; Dry etching the single crystal silicon layer to form a silicon spacer at a junction between the recessed device isolation layer and the silicon substrate; Forming a transistor by forming a gate electrode and a source / drain region on an active region of the silicon substrate; Selectively forming a silicide layer on surfaces of the gate electrode, source / drain regions, and silicon spacers; Sequentially forming a nitride film and an interlayer insulating film on the resultant product; Selectively etching portions of the interlayer dielectric layer and the nitride layer to form a borderless contact hole simultaneously exposing the source / drain region and the device isolation layer including the silicon spacers; And And embedding the borderless contact hole in a conductive film to form a plug. The method for forming a plug of a semiconductor device according to claim 1, wherein a thickness of about 50 to 1,000 GPa is recessed when the device isolation film is recessed. The method of claim 1, wherein the recess of the device isolation layer is wetted using any one of diluted HF, BOE, HCl, NH 4 F and NH 4 OH solutions. The CxHyFz (x, y, z is 0, or natural water) gas is one of Cl2, HBr, BCl3, N2, O2, Ar and He gas. A method of forming a plug of a semiconductor device, characterized in that it is recessed dry using an added mixed gas. The method of claim 1, wherein the single crystal silicon film is formed to a thickness of 20 ~ 900 막. The method of claim 1, wherein, during dry etching of the single crystal silicon film, a gas containing a halogen group element is used as an etching gas. The method for forming a plug of a semiconductor device according to claim 1, wherein the conductive film has any one of a single structure of any one of SiO2, Si3N4, and SiON films, and any two or more laminated structures.