KR20050069007A - Analog buffer and method for driving the same - Google Patents

Abstract

The present invention relates to an analog buffer and a method for driving the same. The present invention compares the level of an input signal to be charged to a data line with an output signal to be charged to a data line, thereby charging a current in the data line through a current switching unit or applying current from the data line. By discharging, the level of the input signal and the output signal are the same, and then the current switching unit is shut off, so that the leakage current can be cut off in the circuit standby mode except for charging and discharging of the data line. In the high resolution and large area liquid crystal display, even when the data line is heavily loaded, the comparator can be designed to a minimum size to minimize leakage current.

Description

ANALOG BUFFER AND METHOD FOR DRIVING THE SAME

The present invention relates to an analog buffer and a driving method thereof, and more particularly, to an analog buffer and a driving method thereof so as to minimize power consumption in driving a signal line of a flat panel display.

In general, among the screen display devices that display image information on the screen, the thin-film flat panel display device has been the subject of intensive development in recent years because of its advantages of being light and easy to use anywhere. In particular, liquid crystal displays have high resolution and are fast in reaction speeds sufficient to realize moving images, and thus are the most active studies.

The liquid crystal display device may artificially adjust the alignment direction of liquid crystal molecules having directionality by using polarization to transmit and block light by optical anisotropy according to the alignment direction of the liquid crystal. Use as a device. Recently, an active matrix form in which a plurality of pixels are arranged in a matrix form and selectively supplies image information to each pixel through a switching element such as a thin film transistor (TFT) provided in each pixel. type) is most commonly used because it provides excellent image quality.

The substrate used in the liquid crystal display is a transparent material that transmits light, and for example, a glass material having advantages in cost and processability is applied.

When the transistor is made of a polycrystalline silicon material having high electron mobility, the switching speed is fast and the size can be designed small. However, since the polycrystalline silicon is formed by a high temperature process, the transistor can be formed on a glass substrate of a liquid crystal display device. There will be no.

Therefore, the thin film transistor applied to the glass substrate of the liquid crystal display device is made of an amorphous silicon material which can be formed by a low temperature process.

On the other hand, since the driving unit of the liquid crystal display requires a very large number of switching elements to process digital signals, a plurality of integrated circuits (ICs) in which switching speeds are fast and small transistors are integrated at high density. It consists of

Therefore, the transistors applied to the driving unit of the liquid crystal display should be made of a polycrystalline silicon material formed by a high temperature process.

As described above, the thin film transistor applied to the substrate of the liquid crystal display device is made of an amorphous silicon material by a low temperature process, and the transistor applied to the driving part of the liquid crystal display device is made of a polycrystalline silicon material formed by a high temperature process.

Accordingly, the driving unit of the liquid crystal display may be manufactured by a plurality of integrated circuits separately on a separate single crystal silicon substrate, and the integrated circuits may be mounted on a tape carrier package (TCP) to form a tab automated bonding (TAB). ) Is connected to the substrate of the liquid crystal display device or mounted on the substrate of the liquid crystal display device in a chip-on-glass (COG) manner to be combined with the substrate.

However, as described above, when the driving unit of the liquid crystal display is combined with the substrate in a tab method or a chip-on-glass method, a space occupied by the driving unit of the liquid crystal display is required, thereby limiting the size and simplification of the liquid crystal display. In addition, various noises, electromagnetic interference (EMI), etc. are generated as the number and length of wires transmitting the driving signals increase, thereby reducing the reliability of the product and increasing the manufacturing cost of the liquid crystal display device. there was.

However, in recent years, with the development of research and development for forming the polycrystalline silicon at a low temperature process, the thin film transistor fabricated on the substrate of the liquid crystal display device can be manufactured from the polycrystalline silicon material, thereby making it possible to manufacture the substrate on the substrate of the liquid crystal display device. A driving circuit-integrated liquid crystal display device capable of embedding a driving unit in a device has been proposed.

1 is an exemplary view showing a schematic configuration of the driving circuit-integrated liquid crystal display device.

Referring to FIG. 1, in the liquid crystal display, the gate lines 20 that are regularly spaced apart from each other and the data lines 30 that are vertically spaced apart from each other are vertically intersected, and the gate lines 20 are intersected with each other. A liquid crystal display panel 10 in which pixels 40 are formed in a rectangular region where the data lines 30 cross each other; A gate driver 50 mounted on the liquid crystal display panel 10 to apply scan signals to the gate lines 20; The data driver 60 is mounted on the liquid crystal display panel 10 to apply a data signal to the data lines 30.

Each pixel 40 includes a pixel electrode and a thin film transistor, the thin film transistor including a gate electrode connected to the gate line 20 and a source electrode connected to the data line 30; And a drain electrode connected to the pixel electrode.

In addition, a gate pad part and a data pad part are formed at one end of the gate lines 20 and the data lines 30.

The gate driver 50 sequentially applies a scan signal to the gate lines 20 through the gate pad part, and the data driver 60 applies a data signal to the data lines 30 through the data pad part. By driving the pixels 40 of the liquid crystal display panel 10 separately, a desired image is displayed on the liquid crystal display panel 10.

The gate driver 50 and the data driver 60 mounted on the liquid crystal display panel 10 are simultaneously formed in the process of manufacturing the thin film transistor array substrate of the liquid crystal display panel 10.

As described above, the driving circuit-integrated liquid crystal display device increases in number and length of data lines and gate lines as high resolution and large area increase, thereby increasing load.

On the other hand, as the resolution and size of the liquid crystal display increase, the amount of data signals processed to drive the liquid crystal display increases significantly. Therefore, the driver of the liquid crystal display needs to be driven at a higher speed. Likewise, the load on the data lines and the gate lines increases, and thus a desired signal cannot be applied quickly.

Therefore, a high resolution and large area liquid crystal display requires an analog buffer capable of applying a desired signal quickly in response to the load of data lines and gate lines.

In general, transistors made of a single crystal silicon material have a small electrical difference, and thus an operational amplifier can be designed and applied to the analog buffer. The designed op amp has a large offset voltage and a large power consumption due to a static current, making it difficult to apply the analog buffer.

Accordingly, the driving circuit-integrated liquid crystal display device requires an analog buffer which is insensitive to the electrical characteristic difference of the transistors made of polycrystalline silicon, has a simple structure, reduces the area occupied, and has low power consumption.

Referring to the accompanying drawings, a conventional analog buffer as described above in detail as follows.

FIG. 2 is a diagram illustrating a conventional analog buffer. As shown in FIG. 2, an analog signal ANALOG_SIG is applied to a data line D1 through a first switch SW1 and a first capacitor C1. A comparator COMP1 correcting a voltage variation of the signal OUT_SIG; A second switch SW2 connected between an input terminal and an output terminal of the comparison unit COMP1; An output terminal of the comparison unit COMP1 and a third switch SW3 connected between the first switch SW1 and the first capacitor C1.

The first switch SW1 and the second switch SW2 are simultaneously turned on and off by the first control signal CS1, and the third switch SW3 is turned on and off by the second control signal CS2. do.

3 is a waveform diagram of the analog buffer shown in FIG. 2. Referring to this, driving of a conventional analog buffer will be described in detail as follows.

First, in the initialization period in which the first control signal CS1 is applied at high potential, the first switch SW1 is turned on so that the analog signal ANALOG_SIG is charged to the first capacitor C1, and the second switch SW2. ) Is also turned on to initialize the input and output of the comparator COMP1. In this case, since the second control signal CS2 is applied at a low potential, the third switch SW3 is blocked.

Therefore, in the initialization period, the first capacitor C1 is charged with the voltage Vana-Vth minus the threshold voltage Vth of the comparator COMP1 from the voltage value Vana of the analog signal ANALOG_SIG.

In addition, the third switch SW3 is turned on in the signal application section in which the second control signal CS2 is applied at high potential so that the voltage value Vana of the analog signal ANALOG_SIG is turned on. The output signal OUT_SIG is applied to the data line D1 through. In this case, since the first control signal CS1 is applied at a low potential, the first switch SW1 and the second switch SW2 are blocked.

The conventional analog buffer driven as described above stores an offset voltage in the first capacitor C1 in order to correct an error due to a difference in electrical characteristics of transistors designed in the comparator COMP1 during the initialization period. Initialize the input and output terminals of the comparator COMP1.

In the signal application section, the voltage value Vana of the analog signal ANALOG_SIG is applied to the data line D1 as an output signal OUT_SIG through the third switch SW3.

When the voltage of the output signal OUT_SIG applied to the data line D1 is changed, the comparator COMP1 changes the voltage of the input terminal and the voltage value of the analog signal ANALOG_SIG together with the first capacitor C1. It will raise or lower (Vana).

That is, when the voltage of the output signal OUT_SIG applied to the data line D1 rises, the voltage at the input terminal of the comparator COMP1 drops to the analog signal ANALOG_SIG together with the first capacitor C1. When the voltage Vana is pulled down and the voltage of the output signal OUT_SIG applied to the data line D1 falls, the voltage at the input terminal of the comparator COMP1 rises to increase the voltage of the first capacitor C1. In addition, the voltage value Vana of the analog signal ANALOG_SIG is increased.

As described above, the voltage value Vana of the analog signal ANALOG_SIG pulled up or pulled down is applied as an output signal OUT_SIG to the data line D1 through the third switch SW3, and thus the output signal OUT_SIG. Variation of the voltage is corrected, and the corrected voltage is applied to the data line D1.

However, in the conventional analog buffer as described above, the leakage current flows from the comparator COMP1 as the offset voltage is driven to the input terminal of the comparator COMP1, and the output terminal of the comparator COMP1 is output. In the case of a high-resolution and large-area liquid crystal display device having a large load of the data line D1 connected thereto, the comparator COMP1 should be designed to have a large leakage current, thereby increasing power consumption.

In fact, the inventors of the present invention drive the display panel through the above-described analog buffer, and as a result of the test, a leakage current of about 80 mA from the comparator COMPP1 in the state where an offset voltage is applied to the input terminal of the comparator COMP1. Was observed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide an analog buffer and a driving method thereof which can reduce power consumption in driving signal lines of a flat panel display.

The analog buffer for achieving the object of the present invention includes a comparison unit for outputting a control signal by comparing the input signal to be charged in the signal line of the display panel with the output signal charged in the signal line of the display panel; And a current switching unit for discharging a current from a signal line of the display panel or charging a current in a signal line of the display panel by a control signal of the comparator.

The analog buffer according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

4 is an exemplary view showing a block configuration of an analog buffer according to the present invention.

Referring to FIG. 4, the analog buffer according to the present invention compares an input signal IN to be charged to the data line D11 of the display panel with an output signal OUT to be charged to the data line D11 of the display panel. A comparator 110 for outputting a control signal C_OUT; The current switching unit 120 discharges a current from the data line D11 or charges a current in the data line D11 by the control signal C_OUT of the comparator 110.

5 is an exemplary view showing a circuit configuration of an analog buffer according to the first embodiment of the present invention.

Referring to FIG. 5, the comparison unit 110 receives a first comparison unit COMP11 that receives an input signal IN to be charged in the data line D11 through the first switch SW11 and the first capacitor C11. )Wow; A second switch (SW12) connected between an input terminal and an output terminal of the first comparator (COMP11) to initialize the input terminal and the output terminal; A second comparator COMP12 receiving the output signal of the first comparator COMP11 through a second capacitor C12 and outputting a control signal C_OUT; A third switch (SW13) connected between an input terminal and an output terminal of the second comparator (COMP12) to initialize the input terminal and the output terminal; The fourth switch SW14 applies an input signal IN charged in the first capacitor C11 to the data line D11.

The first to third switches SW11 to SW13 are simultaneously turned on or off by the first control signal CS11, and the fourth switch SW14 is turned on or off by the second control signal CS12. In this case, the first control signal CS11 is a waveform in which pulses are applied at regular intervals, and the second control signal CS12 is a reverse phase waveform of the first control signal CS11. Therefore, the first to third switches SW11 to SW13 and the fourth switch SW14 are alternately turned on or off.

The first to third switches SW11 to SW13 may be configured as transistors that are simultaneously turned on or turned off by receiving a first control signal CS11 to a gate electrode. The fourth switch SW14 may be configured as a transistor that is turned on or turned off by receiving a second control signal CS12 to the gate electrode. In this case, the first to fourth switches SW11 to SW14 may be configured as an N-type MOS transistor or a P-type MOS transistor.

In addition, the first to third switches SW11 to SW13 receive a first control signal CS11 and an inverted signal of the first control signal CS11 to a gate electrode and are applied to a common electrode. Can be composed of a pair of N-type and type transistors for transmitting or blocking to a common connected drain electrode, and the second switch signal CS12 and the second control signal CS12 are connected to the gate electrode through the fourth switch SW14. A pair of N-type and P-type transistors may be configured to receive an inverted signal of a reference) and transmit or block a signal applied to a common connected source electrode to a common connected drain electrode. The pair of N-type and type transistors configured as described above is commonly referred to as a transmission gate.

The first comparator COMP11 and the second comparator COMP11 and COMP12 may be configured as an inverter, a voltage amplifier, or the like.

A resistor may be further provided between the fourth switch SW14 and the data line D11 to prevent noise from occurring in the output signal OUT, and precharges the data line D11. Alternatively, a switch for resetting may be further provided.

The current switching unit 120 discharges current from the data line D11 through an eleventh switch SW21 that is turned on or off according to the control signal C_OUT of the second comparator COMP12. One current source 120A; The second current source 120B charges a current in the data line D11 through a twelfth switch SW31 that is turned on or off according to the control signal C_OUT of the second comparator COM12.

6 is a waveform diagram illustrating a simulation of a circuit configuration of an analog buffer according to the first embodiment of the present invention. Referring to this, driving of the analog buffer according to the first embodiment of the present invention will be described in detail as follows. same.

First, in the initialization period in which the first control signal CS11 is applied to the comparator 110 at high potential, the first switch SW11 is turned on so that the input signal IN to be charged in the data line D11 of the display panel is first generated. The first capacitor C11 is charged and the second switch SW12 is turned on to initialize the input terminal and the output terminal of the first comparator COMP11.

In addition, as the second switch SW12 is turned on, the input signal IN is charged to the second capacitor C12, and the third switch SW13 is turned on so that the input terminal and the output terminal of the second comparator COMP12 are turned on. Initialize

In the meantime, the second control signal CS12 is applied at a low potential in the initialization section in which the first control signal CS11 is applied at a high potential, so that the fourth switch SW14 is cut off, and the data line D11 is further provided. Can be reset by a switch that is

Therefore, in the initialization period, the first capacitor C11 is charged with a voltage value obtained by subtracting the threshold voltage Vth of the first comparator COM11 from the voltage of the input signal IN. At this time, as the input terminal and the output terminal of the second comparator COMP12 configured as the inverter are initialized by the third switch SW13, the control signal C_OUT of the second comparator COM12 is output as a voltage value of an intermediate level. The first current source 120A and the second current source 120B are not driven.

In addition, the first to third switches SW11 to SW13 are cut off and the fourth switch S14 is turned on in the signal application section where the second control signal CS12 is applied at high potential. The input signal IN stored in C11 is applied to the data line D11 as an output signal OUT through the fourth switch S14.

The first comparator COMP11 and the second comparator COMP12 of the comparator 110 compare the difference between the input signal IN and the output signal OUT, and thus the level of the input signal IN is equal to the output signal. If the level is greater than the level of OUT, the level of the control signal C_OUT output from the second comparator COM12 is increased. On the contrary, if the level of the input signal IN is smaller than the level of the output signal OUT. The level of the control signal C_OUT output from the second comparison unit COMP12 is lowered.

When the level of the control signal C_OUT output from the second comparator COMP12 rises, the second current source 120B is driven to charge a current in the data line D11, and conversely, the second comparator. When the level of the control signal C_OUT output from COMP12 decreases, the first current source 120A is driven to discharge current from the data line D11.

The current is charged in the data line D11 by the second current source 110B or the current is discharged from the data line D11 by the first current source 110A, so that the level of the input signal IN and the output signal OUT is reduced. When this is the same, the control signal C_OUT output from the second comparator COMP12 is output as a voltage value of an intermediate level to block driving of the second current source 120B and the first current source 120A.

The analog buffer according to the first embodiment of the present invention driven as described above compares the level of the input signal to be charged to the data line with the output signal to be charged to the data line and charges the current to the data line through the current switch. By discharging the current from the data line, the level of the input signal and the output signal are the same, and then the current switching unit is shut off, thereby preventing the leakage current in the circuit stand-by mode except for charging and discharging of the data line. Will be.

In addition, since the output terminal of the comparator is not connected to the data line, the analog buffer according to the first embodiment of the present invention has a leakage current by designing the comparator to a minimum size even when the load of the data line is high in a high resolution and large area liquid crystal display. Can be minimized.

On the other hand, in the analog buffer according to the first embodiment of the present invention, when an overshoot occurs in which the level of the output signal charged to the data line exceeds the level of the desired data signal, the current switching unit is determined according to the comparison result. Because the drive is done in real time, the level of the output signal charged to the data line can be maintained stably and accurately.

7 is an exemplary view showing a circuit configuration of an analog buffer according to a second embodiment of the present invention.

Referring to FIG. 7, the comparison unit 110 of FIG. 4 receives a first comparison of receiving an input signal IN to be charged in the data line D11 through the first switch SW11 and the first capacitor C11. Part (COMP11); A second switch (SW12) connected between an input terminal and an output terminal of the first comparator (COMP11) to initialize the input terminal and the output terminal; A second comparator COMP12 receiving the output signal of the first comparator COMP11 through a second capacitor C12 and outputting a control signal C_OUT; A third switch (SW13) connected between an input terminal and an output terminal of the second comparator (COMP12) to initialize the input terminal and the output terminal; A third capacitor C13 connected between the input terminal of the first comparator COMP11 and the data line D11; The fourth switch SW14 electrically connects or disconnects the input terminal of the first comparator COMP11 and the data line D11.

The first to third switches SW11 to SW13 are simultaneously turned on or off by the first control signal CS11, and the fourth switch SW14 is turned on or off by the second control signal CS12. In this case, the first control signal CS11 is a waveform in which pulses are applied at regular intervals, and the second control signal CS12 is a reverse phase waveform of the first control signal CS11. Therefore, the first to third switches SW11 to SW13 and the fourth switch SW14 are alternately turned on or off.

The first to fourth switches SW11 to SW14 may be configured as the above-described en-type or transistor type morph transistors, or may be configured as transmission gates.

The first comparator COMP11 and the second comparator COMP11 and COMP12 may be configured as an inverter, a voltage amplifier, or the like.

A resistor may be further provided between the fourth switch SW14 and the data line D11 to prevent noise from being generated in the output signal OUT, and pre-charge or reset the data line D11. A switch may be further provided.

In addition, the current switching unit 120 of FIG. 4 receives current from the data line D11 through the eleventh switch SW21 which is turned on or off according to the control signal C_OUT of the second comparison unit COMP12. A first current source 120A for discharging; The second current source 120B charges a current in the data line D11 through a twelfth switch SW31 that is turned on or off according to the control signal C_OUT of the second comparator COM12.

As shown in FIG. 6, the first current source 120A and the second current source 120B may have a current mirror type circuit, and the eleventh switch SW21 and the twelfth switch SW31 may be shaped morph transistors. And N-type MOS transistors can be applied.

8 is a waveform diagram simulating a circuit configuration of an analog buffer according to a second embodiment of the present invention. Referring to this, the driving of the analog buffer according to the second embodiment of the present invention will be described in detail as follows.

First, in the initialization period in which the first control signal CS11 is applied to the comparator 110 at high potential, the first switch SW11 is turned on so that the input signal IN to be charged in the data line D11 of the display panel is first generated. The first capacitor C11 is charged and the second switch SW12 is turned on to initialize the input terminal and the output terminal of the first comparator COMP11.

In addition, as the second switch SW12 is turned on, the input signal IN is charged to the second capacitor C12, and the third switch SW13 is turned on so that the input terminal and the output terminal of the second comparator COMP12 are turned on. Initialize

In the meantime, the second control signal CS12 is applied at a low potential in the initialization section in which the first control signal CS11 is applied at a high potential, so that the fourth switch SW14 is cut off, and the data line D11 is further provided. Can be reset by a switch that is

Therefore, in the initialization period, the first capacitor C11 is charged with a voltage value obtained by subtracting the threshold voltage Vth of the first comparator COM11 from the voltage of the input signal IN. At this time, as the input terminal and the output terminal of the second comparator COMP12 configured as the inverter are initialized by the third switch SW13, the control signal C_OUT of the second comparator COM12 is output as a voltage value of an intermediate level. The first current source 120A and the second current source 120B are not driven.

In addition, the first to third switches SW11 to SW13 are cut off and the fourth switch S14 is turned on in the signal application section in which the second control signal CS12 is applied at high potential. ) Is electrically connected to an input terminal of the first comparison unit COMP11. In this case, the data line D11 and the first comparator COMP11 are electrically connected to each other through the third capacitor C13, so that the output signal OUT of the data line D11 is connected to the first capacitor C11 and the first capacitor C11. It can be adjusted by the capacitance ratio of the three capacitors (C13).

The first comparator COMP11 and the second comparator COMP12 of the comparator 110 compare the difference between the input signal IN and the output signal OUT, and thus the level of the input signal IN is equal to the output signal. If the level is greater than the level of OUT, the level of the control signal C_OUT output from the second comparator COM12 is increased. On the contrary, if the level of the input signal IN is smaller than the level of the output signal OUT. The level of the control signal C_OUT output from the second comparison unit COMP12 is lowered.

When the level of the control signal C_OUT output from the second comparator COMP12 rises, the second current source 120B is driven to charge a current in the data line D11, and conversely, the second comparator. When the level of the control signal C_OUT output from COMP12 decreases, the first current source 120A is driven to discharge current from the data line D11.

As described above, the current is charged in the data line D11 by the second current source 110B, or the current is discharged from the data line D11 by the first current source 110A to output the input signal IN and the output signal OUT. ) Level is the same, the control signal C_OUT output from the second comparator COMP12 outputs a voltage value of an intermediate level to block driving of the second current source 120B and the first current source 120A. .

The analog buffer according to the second embodiment of the present invention driven as described above compares the level of the input signal to be charged to the data line with the output signal to be charged to the data line and charges the current to the data line through the current switch. By discharging the current from the data line, the level of the input signal and the output signal are the same, and then the driving of the current switching unit is cut off, thereby preventing the leakage current in the circuit standby mode except for charging and discharging the data line.

In addition, in the analog buffer according to the second embodiment of the present invention, since the output terminal of the comparator is not connected to the data line, the comparator is designed to have a minimum size even when the load of the data line is high in a high resolution and large area liquid crystal display device. Can be minimized.

The analog buffer according to the second embodiment of the present invention controls the driving of the current switching unit by comparing the level of the input signal to be charged to the data line with the output signal charged to the data line. No pre-charge is required.

On the other hand, in the analog buffer according to the second embodiment of the present invention, when an overshoot occurs in which the level of the output signal charged to the data line exceeds the level of the desired data signal, the current switching unit is determined according to the comparison result of the comparator. Because the drive is done in real time, the level of the output signal charged to the data line can be maintained stably and accurately.

FIG. 9 is an example of the first current source 120A and the second current source 120B of the current switching unit 120 shown in FIGS. 5 and 7, and a circuit in the form of a current mirror is applied. The first current source 120A, the second current source 120B, the eleventh switch SW21 and the twelfth switch to which the shaped morph transistor and the en-type morph transistor are applied as the eleventh switch SW21 and the twelfth switch SW31. An example view showing the circuit configuration of SW31.

Referring to FIG. 9, the first current source 120A has a ground potential VSS through the eleventh type morph transistor PM21 whose drain electrode is electrically controlled by the control signal C_OUT of the second comparator COM12. A twelfth pit transistor (PM22) connected to the gate electrode, a gate electrode connected to the drain electrode, and a source electrode connected to the power supply voltage VDD; A thirteenth type morph transistor PM23 having a drain electrode connected to the ground potential VSS, a gate electrode connected to a gate electrode of the twelfth type morph transistor PM22, and a source electrode connected to the data line D11. It is composed of

In the second current source 120B, a source electrode is connected to the power supply voltage VDD, a gate electrode is connected to the drain electrode, and the drain electrode is controlled by the control signal C_OUT of the second comparison unit COMP12. A twenty-first type morph transistor PM31 connected to a ground potential VSS through a twenty-first en-type morph transistor NM31 controlled to be conductive; A twenty-second type MOS transistor PM32 having a source electrode connected to the power supply voltage VDD, a gate electrode connected to a gate electrode of the twenty-first type MOS transistor PM31, and a drain electrode connected to the data line D11. It is composed of

The first current source 120A and the second current source 120B configured as described above are selectively driven according to the control signal C_OUT level of the second comparator COMP12 to draw current from the data line D11. Discharge or charge current to the data line D11.

That is, when the eleventh type MOS transistor PM21 is turned on by the control signal C_OUT of the second comparator COM12, the power supply voltage of the first current source 120A is turned on. Current according to the turn-on state of the eleventh-type morph transistor PM21 through a first path leading to the VDD, the twelfth-type morph transistor PM22, the eleventh-type morph transistor PM21, and the ground potential VSS. In this case, the current value flowing through the first path flows equally to the second path leading to the data line D11, the thirteenth-type morph transistor PM23, and the ground potential VSS according to the principle of the current mirror. One current source 120A discharges current from the data line D11. At this time, the second current source 120B is not driven because the twenty-first N-type MOS transistor PM31 is turned off.

When the twenty-first N-type MOS transistor NM31 is turned on by the control signal C_OUT of the second comparator COM12, the power voltage VDD and the second voltage of the second current source 120A are turned on. A current flows according to the turn-on state of the 21 th type N-type transistor NM31 through a third path leading to the 21-type morph transistor PM31, the 21st-type MOS transistor NM31, and the ground potential VSS. The current value flowing through the three paths is equally flowed in the fourth path leading to the power supply voltage VDD, the 22nd type morph transistor PM32, and the data line D11 according to the principle of the current mirror, and thus the second current source 120A. Charges a current in the data line D11. At this time, since the eleventh type morph transistor PM21 is turned off, the first current source 120A is not driven.

Meanwhile, the analog buffer according to the present invention may be provided in a gate driver or a data driver embedded in a liquid crystal display integrated with a driving circuit. In particular, the analog buffer may be provided in an output terminal of a data driver for applying an image signal to a data line of a liquid crystal display. Can be.

In addition, the analog buffer according to the present invention is not only a liquid crystal display but also a plasma display device (PDP), a field emission display (FED), or a cathode ray tube (CRT). The display device may be provided in a signal line driver of various flat panel display devices such as an electroluminescence display (ELD), and may be provided in an output terminal of a signal line driver that applies an image signal to a signal line of a flat panel display.

As described above, the analog buffer and the driving method thereof according to the present invention compare the level of the input signal to be charged to the data line and the output signal to be charged to the data line to charge current in the data line through the current switch or from the data line. By discharging the current, the level of the input signal and the output signal are the same, and then the driving of the current switching unit is cut off, thereby preventing the leakage current in the circuit standby mode except for charging and discharging the data line, thereby reducing power consumption. It can work.

In addition, since the output terminal of the comparator is not connected to the data line, even when the load of the data line is high in a high resolution and large area liquid crystal display, the comparator can be designed to a minimum size to minimize leakage current, thereby reducing power consumption. There is an effect that can be minimized.

When the level of the output signal charged to the data line exceeds the level of the desired data signal, the current switching unit is driven in real time according to the comparison result of the comparator. Since the level of the output signal can be maintained stably and accurately, the desired color can be accurately expressed on the display panel, thereby improving image quality.

In particular, in the second embodiment of the present invention, the analog buffer and the driving method thereof are used because the comparator controls the driving of the current switching unit by simply comparing the level of the input signal to be charged to the data line and the output signal to be charged to the data line. Since pre-charging for driving is not required, driving is simplified and power consumption can be reduced.

1 is an exemplary view showing a schematic configuration of a drive circuit-integrated liquid crystal display device.

Figure 2 is an exemplary view showing a conventional analog buffer.

FIG. 3 is a waveform diagram of first and second control signals and output signals in FIG. 2; FIG.

Figure 4 is an exemplary view showing a block configuration of an analog buffer according to the present invention.

5 is an exemplary view showing a circuit configuration of an analog buffer according to the first embodiment of the present invention in FIG.

FIG. 6 is a waveform diagram simulating a circuit configuration of an analog buffer according to the first embodiment of the present invention shown in FIG.

FIG. 7 is an exemplary view showing a circuit configuration of an analog buffer according to the second embodiment of the present invention in FIG.

FIG. 8 is a waveform diagram simulating the circuit configuration of the analog buffer according to the second embodiment of the present invention shown in FIG.

FIG. 9 is an exemplary view showing a circuit configuration of a first current source, a second current source, an eleventh switch, and a twelfth switch in FIGS. 5 and 7;

*** Explanation of symbols for main parts of drawing ***

110: comparison unit 120: current switching unit

IN: input signal OUT: output signal

C_OUT: control signal D11: data line

Claims (34)

A comparator for comparing the input signal to be charged in the signal line of the display panel with the output signal charged to the signal line of the display panel and outputting a control signal; And a current switching unit for discharging a current from a signal line of the display panel or charging a current in a signal line of the display panel by a control signal of the comparator. The analog buffer of claim 1, wherein the analog buffer is provided in a data driver embedded in a liquid crystal display integrated with a driving circuit. The analog buffer of claim 1, wherein the signal line is a data line of a liquid crystal display. The display apparatus of claim 1, wherein the comparison unit comprises: a first comparison unit configured to receive an input signal to be charged in the signal line through a first switch and a first capacitor; A second switch connected between the input terminal and the output terminal of the first comparator to initialize the input terminal and the output terminal; A second comparator for receiving the output signal of the first comparator through a second capacitor and outputting a control signal; A third switch connected between an input terminal and an output terminal of the second comparing unit to initialize the input terminal and the output terminal; And a fourth switch configured to apply an input signal charged in the first capacitor to a signal line. The analog buffer of claim 4, wherein the first to fourth switches are formed of an N-type MOS transistor or a P-type MOS transistor. The analog buffer of claim 4, wherein the first to fourth switches are configured as a transmission gate. The analog buffer of claim 4, wherein the first and second comparators comprise one of an inverter and a voltage amplifier. The analog buffer of claim 4, further comprising a resistor between the fourth switch and the signal line. 5. The analog buffer of claim 4, further comprising a switch for precharging or resetting the signal line between the fourth switch and the signal line. The display apparatus of claim 1, wherein the comparator comprises: a first comparator configured to receive an input signal to be charged in a signal line through a first switch and a first capacitor; A second switch connected between the input terminal and the output terminal of the first comparator to initialize the input terminal and the output terminal; A second comparator for receiving the output signal of the first comparator through a second capacitor and outputting a control signal; A third switch connected between an input terminal and an output terminal of the second comparing unit to initialize the input terminal and the output terminal; A third capacitor connected between an input terminal of the first comparator and a signal line; And a fourth switch for electrically connecting or disconnecting an input terminal of the first comparator and a signal line. The analog buffer of claim 10, wherein the first to fourth switches are configured of an N-type MOS transistor or a P-type MOS transistor. The analog buffer of claim 10, wherein the first to fourth switches are configured as a transmission gate. The analog buffer of claim 10, wherein the first and second comparators comprise one of an inverter and a voltage amplifier. The analog buffer of claim 10, further comprising a resistor between the fourth switch and the signal line. 11. The analog buffer of claim 10, further comprising a switch for precharging or resetting the signal line between the fourth switch and the signal line. The electronic device of claim 1, wherein the current switching unit comprises: a first current source configured to discharge current from the signal line through an eleventh switch that is turned on or off according to a control signal of the comparator; And a second current source configured to charge a current in the data line through a twelfth switch that is turned on or off according to the control signal of the comparator. 17. The analog buffer of claim 16 wherein the first current source and the second current source comprise a current mirror. 17. The power supply of claim 16, wherein the first current source is connected to a ground potential through an eleventh type morph transistor whose drain electrode is electrically controlled by a control signal of the comparator, the gate electrode is connected to the drain electrode, and the source electrode is a power source. A twelfth shaped morph transistor connected to a voltage; And a drain electrode connected to the ground potential, a gate electrode connected to the gate electrode of the twelfth-type morph transistor, and a source electrode connected to the signal line, the thirteenth-type morph transistor. 17. The second current source of claim 16, wherein the source electrode is connected to a power supply voltage, the gate electrode is connected to a drain electrode, and the drain electrode is grounded through a twenty-first N-type MOS transistor in which conduction is controlled by a control signal of the comparator. A twenty-first type morph transistor connected to the potential; And a source electrode connected to the power supply voltage, a gate electrode connected to the gate electrode of the twenty-first type morph transistor, and a drain electrode connected to the signal line. A first comparing unit receiving an input signal to be charged in the signal line through the first switch and the first capacitor; A second switch connected between the input terminal and the output terminal of the first comparator to initialize the input terminal and the output terminal; A second comparator for receiving the output signal of the first comparator through a second capacitor and outputting a control signal; A third switch connected between an input terminal and an output terminal of the second comparing unit to initialize the input terminal and the output terminal; A first current source configured to discharge current from the signal line through an eleventh switch which is turned on or off in accordance with a control signal of the second comparator; A second current source for charging current in the signal line through a twelfth switch which is turned on or off according to a control signal of the second comparing unit; And a fourth switch configured to apply an input signal charged in the first capacitor to a signal line. 21. The analog buffer of claim 20, wherein the first to fourth switches are configured as a transmission gate. 21. The analog buffer of claim 20, wherein the first and second comparators comprise one of an inverter and a voltage amplifier. 21. The analog buffer of claim 20, further comprising a resistor between the fourth switch and the signal line. 21. The analog buffer of claim 20, further comprising a switch for precharging or resetting the signal line between the fourth switch and the signal line. 21. The analog buffer of claim 20 wherein the first current source and the second current source comprise a current mirror. A first comparing unit receiving an input signal to be charged in the signal line through the first switch and the first capacitor; A second switch connected between the input terminal and the output terminal of the first comparator to initialize the input terminal and the output terminal; A second comparator for receiving the output signal of the first comparator through a second capacitor and outputting a control signal; A third switch connected between an input terminal and an output terminal of the second comparing unit to initialize the input terminal and the output terminal; A first current source configured to discharge current from the signal line through an eleventh switch which is turned on or off in accordance with a control signal of the second comparator; A second current source for charging current in the signal line through a twelfth switch which is turned on or off according to a control signal of the second comparing unit; A third capacitor connected between an input terminal of the first comparator and a signal line; And a fourth switch for electrically connecting or disconnecting an input terminal of the first comparator and a signal line. 27. The analog buffer of claim 26, wherein the first to fourth switches are configured as a transmission gate. 27. The analog buffer of claim 26, wherein the first and second comparators comprise one of an inverter and a voltage amplifier. 27. The analog buffer of claim 26, further comprising a resistor between the fourth switch and the signal line. 27. The analog buffer of claim 26, further comprising a switch for precharging or resetting the signal line between the fourth switch and the signal line. 27. The analog buffer of claim 26 wherein the first current source and the second current source comprise a current mirror. A first step of comparing an input signal to be charged in the signal line of the display panel with an output signal charged in the signal line of the display panel; Discharging a current from a signal line of the display panel or charging a current in a signal line of the display panel according to the comparison result of the first step; A third step of compensating for a phenomenon in which the level of the output signal exceeds a desired level; And a fourth step of interrupting charging or discharging of the current. Initializing the input and output terminals of the comparator; Comparing an input signal to be charged in the signal line of the display panel with an output signal charged in the signal line of the display panel; Changing the control signal level of the comparator when the level of the input signal is higher than the level of the output signal to charge a current in the signal line; And discharging a current from the signal line by changing a control signal level of the comparator when the level of the input signal is lower than the level of the output signal. 34. The method of claim 33, further comprising: compensating for a phenomenon in which the level of the output signal exceeds a desired level; And blocking the current charging or discharging.