KR20050070784A - Method for trans-reflection type liquid crystal display device - Google Patents

Abstract

The present invention relates to a method for manufacturing a transflective liquid crystal display device using a low mask technology, comprising: forming first and second semiconductor layers on an insulating substrate; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming a gate electrode and a storage electrode on the gate insulating film; Implanting n-type impurities into the first semiconductor layer using the gate electrode as a mask to form source / drain regions of the n-type TFT; Forming an interlayer insulating film on the entire surface including the gate electrode; Forming a transmission electrode on the interlayer insulating film; Forming a protective film on the entire surface including the transmissive electrode; Forming an uneven pattern on the passivation layer where the n-type TFT region and the transmission electrode are located; Implanting p-type impurities into the second semiconductor layer using the gate electrode as a mask to form source / drain regions of the p-type TFT; Forming an organic insulating film along a surface of the uneven pattern; Forming a contact hole and an open area to which the source / drain area and the transmission electrode are respectively exposed; And simultaneously forming a source / drain electrode connected to the source / drain region through the contact hole and a reflective electrode connected to the transmissive electrode through the open region.

Description

Method for manufacturing a transflective liquid crystal display device {Method for Trans-reflection Type Liquid Crystal Display Device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device (LCD), and more particularly, to a method of manufacturing a CMOS-TFT array substrate using low mask technology.

Liquid crystal display devices have a high contrast ratio, are suitable for gray scale display and moving image display, and have low power consumption.

The liquid crystal display device forms various patterns such as a driving device or a wiring on a substrate to perform an operation, and photolithography is a common technique used to form a pattern.

The method includes coating a photoresist, which is a material that is photosensitive with ultraviolet rays, to a substrate on which a pattern is to be formed, exposing the pattern formed on the photomask onto the photoresist, and developing the photoresist. After etching, a series of complex processes of stripping the photoresist occur.

Therefore, researches on technologies for increasing productivity and securing process margin by minimizing the number of photolithography processes have been actively conducted.

On the other hand, the liquid crystal display device includes a thin film transistor (TFT) for selectively applying a signal to the pixel electrode of each pixel, and storage for maintaining a state of charge until each pixel is subsequently addressed. A TFT array substrate, a color filter substrate having a color filter layer for realizing color, a liquid crystal layer encapsulated between the two substrates, and a driving circuit for driving the TFT array substrate, the image being displayed by various external signals. Is displayed.

In this case, in the case of the transflective liquid crystal display device, each pixel is divided into a transmissive part and a reflecting part, and a transmissive electrode is formed in the transmissive part, and a reflective electrode is formed in the reflecting part, thereby applying a constant voltage to the liquid crystal.

The transmissive part displays an image by injecting light from the backlight incident through the lower substrate into the liquid crystal layer, and the reflecting part reflects external light incident through the upper substrate when the external natural light is bright to display an image. There is.

The driving circuit is formed on a separate PCB substrate and connected to the TFT substrate by TCP. Recently, however, a method of forming the driving circuit on the TFT array substrate without forming a separate PCB has been proposed.

The thin film transistor may include a pixel driving thin film transistor for driving each pixel in an active region, and a pad unit for applying a signal to a gate line and a data line by operating the pixel driving thin film transistor. It is divided into thin film transistor for driving circuit in the area.

In this case, the pixel driving thin film transistor is an n-type TFT capable of high-speed operation, and the thin film transistor for driving circuit is a p-type TFT having excellent power consumption along with the n-type TFT. A thin film transistor is implemented.

Hereinafter, a manufacturing method of a conventional transflective liquid crystal display device having a CMOS thin film transistor will be described with reference to the accompanying drawings.

First, as shown in FIG. 1A, a buffer layer 52 is formed on an insulating substrate 11, and a polycrystalline silicon layer is formed on the buffer layer 52. Then, a first photoresist (not shown) is deposited on the polycrystalline silicon layer, and the first, second and third semiconductor layers 54 (54; 54a, 54b, 54c) are used as a photoetching technique using a first mask. To form.

The polycrystalline silicon layer may be formed by directly depositing polycrystalline silicon, or by depositing amorphous silicon and then crystallizing the polycrystalline silicon.

The former method is LPCVD (Low Pressure Chemical Vapor Deposition) to be deposited at high temperature above 550 ℃ and plasma chemical vapor deposition using SiF4 / SiH4 / H2 mixed gas below 400 ℃. (PECVD method: Plasma Enhanced Chemical Vapor Deposition), etc. The latter method is a solid phase crystallization method (SPC method: Solid Phase Crystallization) which crystallizes by heat treatment at high temperature for a long time, and an excimer which is crystallized by applying an excimer laser while heating to about 250 ° C. Laser annealing (ELA), metal induced crystallization (CVD) that induces crystallization by depositing a metal on an amorphous silicon layer.

The semiconductor layer 54 is patterned into three kinds of island shapes, among which the first and third semiconductor layers 54a and 54c are n-type thin film transistors (TFTs) and p-type thin films, respectively, through post-processing. The transistor TFT is formed, and storage is formed in the second semiconductor layer 54c through a post process.

Next, as shown in FIG. 1B, after the second photoresist 31 is coated on the entire surface of the insulating substrate 11, the first semiconductor layer 54a of the n-type TFT region and the exposure and development processes using the second mask are formed. The second photoresist 31 is patterned to cover the third semiconductor layer 54c of the p-type TFT region.

Thereafter, storage doping is performed on the entire surface of the substrate to form a storage doping layer for the second semiconductor layer 54b of the storage area.

Subsequently, as shown in FIG. 1C, the second photoresist 31 pattern is removed, and an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is generally plasma-enhanced on the entire surface of the insulating substrate 11. The gate insulating layer 13 is formed by depositing by a plasma enhanced chemical vapor deposition (PECVD) method.

In addition, as an example of the low resistance metal layer on the gate insulating layer 13, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) ), Molybdenum-tungsten (MoW), and the like, and a third photoresist (not shown) are deposited thereon, and then on each of the semiconductor layers 54a, 54b, and 54c by photolithography using a third mask. The first and second gates 12 and 22 and the storage electrode 19 are formed on the substrate.

At this time, the first and second gates 12 and 22 are formed in a predetermined region so as to overlap the first and second channel layers 14 and 24 in the n-type TFT region and the p-type TFT region to be formed later. The storage electrode 19 is formed to overlap the second semiconductor layer 54b in the storage area.

Next, the semiconductor layers 54a and 54c are doped with low concentrations of n-type impurity ions using the first and second gate electrodes 12 and 22 as masks, so that the first and second gate electrodes 12 and 22 are doped. Lightly Doped Drain (LDD) doping layers 88 are formed in the semiconductor layers 54a and 54c on both sides. At this time, the first and second channel layers 14 and 24 become regions of the first and second semiconductor layers 54a and 54c which are not doped with n-type impurities.

As such, the reason for forming the LDD doped layer by doping a portion of the semiconductor layer at low concentration is to reduce the electric field applied to the junction due to the resistance in the region so as to reduce the off current and minimize the decrease of the on current. For sake.

Thereafter, as shown in FIG. 1D, after applying the fourth photoresist 33 to the entire surface including the first gate electrode 12, the first gate electrode 12 is exposed and developed using a fourth mask. A portion of the first semiconductor layer 54a of both n-type TFT regions is patterned to be exposed. As a result, the p-type TFT region and the storage region are blocked to prevent ion implantation into the region.

Then, the first source / drain regions 15a and 15b are formed in the n-type TFT region by doping a high concentration of n-type impurity ions with phosphorus (P) or the like on the entire surface of the insulating substrate 11. Next, the first source / drain regions 15a and 15b are activated.

Next, after stripping the fourth photoresist 33, after applying the fifth photoresist 35 to the entire surface including the first and second gate electrodes 12 and 22, as shown in FIG. 1E. The patterning is performed such that the p-type TFT region is exposed by an exposure and etching process using a fifth mask. As a result, the n-type TFT region and the storage region are blocked to prevent ion implantation into the region.

Thereafter, high concentrations of p-type impurity ions are doped with boron (B) or the like on the entire surface of the insulating substrate 11 to form second source / drain regions 25a and 25b in the p-type TFT region. Next, the second source / drain regions 25a and 25b are activated.

Thereafter, the fifth photoresist 35 is stripped and an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the first gate electrode 12 by PECVD as shown in FIG. 1F. The interlayer insulating film 23 is formed.

In addition, a sixth photoresist (not shown) is deposited, and a predetermined portion of the first and second source / drain regions 15a, 15b, 25a, and 25b is exposed by photolithography using a sixth mask. The gate insulating layer 13 and the interlayer insulating layer 23 are selectively removed to form the first contact hole 71.

Stripping the sixth photoresist and connecting the first and second source / drain regions 15a, 15b, 25a, and 25b through the first contact hole 71 as shown in FIG. 1g. Two source / drain electrodes 15c, 15d, 25c, and 25d are formed to complete a CMOS thin film transistor having an n-type TFT and a p-type TFT.

That is, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), and titanium on the entire surface including the interlayer insulating layer 23 so as to be filled in the first contact hole 71. (Ti), tantalum (Ta), molybdenum-tungsten (MoW), and the like, a low-resistance metal layer and a seventh photoresist (not shown) are sequentially deposited and patterned by an exposure and development process using a seventh mask to form the first, Two source / drain electrodes 15c, 15d, 25c, and 25d are formed.

Thus, an n-type TFT composed of the first gate electrode 12, the first source / drain electrodes 15c and 15d, and the first channel layer 14 and formed for each pixel and driving the respective pixels, A p-type TFT composed of the second gate electrode 22, the second source / drain electrodes 25c and 25d, and formed on the driving circuit part and applying a signal to each gate wiring and data wiring; The second semiconductor layer 54b, the gate insulating layer 13, and the storage electrode 19 constitute storage for each pixel.

After stripping the seventh photoresist and applying photoacrylic resin to the entire surface including the first source / drain electrodes 15c and 15d as shown in FIG. 1H, exposure and development using an eighth mask are performed. In the process, a plurality of photoacrylic resin patterns at regular intervals are formed, and the photoacrylic resin pattern is reflowed to form a spherical first uneven pattern 90.

Therefore, a plurality of first uneven patterns 90 are formed in a spherical shape at predetermined intervals.

Next, as shown in FIG. 1I, an inorganic insulating material such as silicon nitride or silicon oxide is deposited on the entire surface including the first uneven pattern 90, or an organic insulating material such as benzocyclobutene (BCB) or an acrylic material is coated to form a protective film. (16) is formed.

In this case, since the material for the protective film is deposited or coated along the first uneven pattern 90, the second uneven pattern 92 is formed on the passivation layer 16.

Subsequently, as shown in FIG. 1J, the passivation layer 16 and the interlayer insulating layer 23 are etched to expose the first drain electrode 15d and the storage electrode 19 by a photoetching technique using a ninth mask. The contact hole 81 is formed.

Subsequently, as shown in FIG. 1K, aluminum, aluminum alloy, titanium, and the like are deposited on the entire surface including the protective film 16, for example, and then patterned as a photoetch technique using a tenth mask to form a reflective electrode ( 17a).

Since the reflective electrode 17a is formed along the surface of the second uneven pattern 92, it has reflective unevenness. In the reflection irregularities, when the external natural light is used as the light source, the reflection angle of the external natural light is locally changed to secure a considerable amount of reflected light.

Lastly, as shown in FIG. 1L, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is deposited on the entire surface including the reflective electrode 17a, and then patterned and transmitted as a photoetch technique using an eleventh mask. The electrode 17b is formed.

In this case, the reflective electrode 17a is formed on the reflective portion of each pixel, and the transparent electrode 17b is formed on the transparent portion of each pixel, and the transparent electrode 17b is disposed on a predetermined portion of the reflective electrode 17a. This contact allows voltage to be applied.

The TFT array substrate thus formed is usually formed using a total of 11 masks.

Thus, although not shown, a CMOS-TFT array substrate including an n-type TFT and a p-type TFT is bonded by a sealant with an opposing substrate on which a color filter layer is formed and a spacer interposed therebetween. Then, the liquid crystal is injected between the two substrates to form a liquid crystal layer, and the liquid crystal inlet is sealed to complete the liquid crystal display device.

The CMOS according to the prior art has a low integration and a complicated process, but research to simplify the process is active due to the advantage of low power consumption. One form of such research is low mask technology.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a CMOS-TFT array substrate and a method of manufacturing the same, which reduce process cost and process time by reducing the number of times of use of a mask.

Method of manufacturing a transflective liquid crystal display device of the present invention for achieving the above object comprises the steps of forming a first, a second semiconductor layer on an insulating substrate; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming a gate electrode and a storage electrode on the gate insulating film; Implanting n-type impurities into the first semiconductor layer using the gate electrode as a mask to form source / drain regions of the n-type TFT; Forming an interlayer insulating film on the entire surface including the gate electrode; Forming a transmission electrode on the interlayer insulating film; Forming a protective film on the entire surface including the transmissive electrode; Forming an uneven pattern on the passivation layer where the n-type TFT region and the transmission electrode are located; Implanting p-type impurities into the second semiconductor layer using the gate electrode as a mask to form source / drain regions of the p-type TFT; Forming an organic insulating film along a surface of the uneven pattern; Forming a contact hole and an open area to which the source / drain area and the transmission electrode are respectively exposed; And simultaneously forming a source / drain electrode connected to the source / drain region through the contact hole and a reflective electrode connected to the transmissive electrode through the open region.

The semi-transmissive liquid crystal display device including the CMOS-TFT according to the present invention greatly reduces the manufacturing cost and the processing time by greatly reducing the number of masks used in the conventional eleven times to six times.

Instead of forming a photoresist with a mask for the P doping process, the number of times of mask use can be reduced by using an uneven pattern.

The lower electrode of the storage capacitor is formed at the same time as the gate electrode, and the upper electrode of the storage capacitor is useful as a transmissive electrode, thereby reducing the number of times the mask is used.

In addition, the number of times of using the mask can be further reduced by forming the source / drain electrodes and the reflective electrodes at the same time.

On the other hand, the array substrate on which the various thin film transistors are formed is divided into an active region and a driving circuit region, wherein the active region defines a data line for transmitting an image signal and vertically crosses the data line to define each pixel, and transmit a scan signal. A thin film transistor for pixel driving including a first gate electrode, a first source / drain electrode, and a first channel layer formed at an intersection point of the gate wiring, the gate wiring and the data wiring, and the thin film transistor for pixel driving. A reflective electrode connected to the plurality of reflective unevennesses, a transmissive electrode connected to the pixel driving thin film transistor by the reflecting electrode, and formed at a predetermined portion of each pixel to form a storage electrode and the transmissive electrode. The capacitor is formed.

And a thin film for a driving circuit configured to include a second gate electrode, a second source / drain electrode, and a second channel layer in the driving circuit region to apply a voltage to each pixel through a data wiring and a gate wiring extending from the active region. The transistor is formed.

In this case, the pixel driving thin film transistor is an n-type TFT capable of high-speed operation, and the thin film transistor for driving circuit is a p-type TFT having excellent power consumption to form a CMOS-TFT.

Hereinafter, a translucent liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and examples.

2A to 2J are process cross-sectional views and II-II 'line plan views for explaining the manufacturing process of the transflective liquid crystal display device according to the present invention.

2A through 2J are divided into an active region in which an n-type TFT is formed and a driving circuit portion region in which a p-type TFT is formed, and a plan view of the active region is shown.

First, as shown in FIG. 2A, amorphous silicon (a-Si: H) is deposited on the insulating substrate 211 by a plasma chemical vapor deposition method using a mixed gas of SiH 4 and H 2, followed by a laser or the like. Rapid application of heat melts and solidifies the amorphous silicon into polycrystalline silicon.

Next, as a photolithography technique using a first photoresist and a first mask, two types of islands are patterned to form first and second semiconductor layers 254 (254a and 254b).

In this case, the first semiconductor layer 254a is positioned in the region where the n-type thin film transistor TFT is to be formed, and the second semiconductor layer 254b is positioned in the region where the p-type thin film transistor TFT is to be formed. Let's do it.

Although not shown, a buffer layer (not shown) may be further formed on the entire surface of the insulating substrate 211 by chemical vapor deposition or the like before the semiconductor layer 254 is formed.

The buffer layer may be formed of an insulating material such as silicon oxide (SiOx), which prevents foreign matter from penetrating into the semiconductor layer 254 in a subsequent process and protects the insulating substrate 211 from high temperature during the crystallization process of the amorphous silicon layer. It also serves to improve the contact characteristics of the semiconductor layer 254 to the insulating substrate 211.

Next, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface including the semiconductor layer 254 by a plasma enhanced chemical vapor deposition method to form a gate insulating layer 213.

 Thereafter, as shown in FIG. 2B, a low resistance metal layer is formed on the gate insulating layer 213, for example, copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), or titanium. (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like are deposited, and a second photoresist 231 is applied thereon.

Thereafter, the second photoresist 231 is patterned by an exposure and development process using a second mask, and then the low resistance metal layer is etched to form first and second gate electrodes 212 and 222 and a storage electrode 219. do.

In this case, the first and second gate electrodes 212 and 222 are simultaneously formed with the gate wire 222a that transmits the scan signal.

Subsequently, as shown in FIG. 2C, the second photoresist 231 is ashed to reduce the thickness and width of the second photoresist 231 pattern compared to the gate electrode. A high concentration of n-type impurities are implanted into the first and second semiconductor layers 254a and 254b using the reduced second photoresist 231 and the first and second gate electrodes 212 and 222 as masks.

That is, by doping phosphorus (P) ions or arsenic (As) ions, the n-type and p-type TFT regions are first and second source / drain regions 215a, 215b, 225a, and 225b which are n-type doped layers. To form. Then, the first source / drain regions 215a and 215b are activated.

At this time, the first and second semiconductor layers 254a and 254b into which the n-type ions are not implanted become the first and second channel layers 214 and 224.

On the other hand, the n-type doped layer formed by ion implantation into the p-type TFT is changed into a p-type doped layer when the p-type impurity ion implantation is performed later.

Next, as shown in FIG. 2D, the first and second gate electrodes 212 and 222 are etched from the sidewall by using the reduced second photoresist 231 as a mask. As such, the LDD doped layer 288 is formed in a later step by the region etched by the etch-back technique.

Subsequently, a low concentration of n-type impurity ions is doped into the first and second semiconductor layers 254a and 254b using the first and second gate electrodes 212 and 222 slightly etched on both sidewalls as a mask.

An LDD doped layer 288, which is an n-doped layer, is formed inside the first and second source / drain regions 215a, 215b, 225a, and 225b, which are n + doped layers adjacent to the first and second gate electrodes 212,222. This reduces the off current by reducing the electric field across the junction.

Then, as illustrated in FIG. 2E, the second photoresist 231 is stripped and an insulating material such as silicon oxide or silicon nitride is deposited on the entire surface of the substrate including the first gate electrode 212. The interlayer insulating film 223 is formed by vapor deposition.

Subsequently, ITO or IZO, which is a transparent conductive material, is deposited on the entire surface including the interlayer insulating layer 223, and then patterned by photo etching using a fourth mask to form a transmissive electrode 217b.

In this case, the transmission electrode 217b overlapping the storage electrode 219 forms a storage capacitor together with the storage electrode 219 and the interlayer insulating layer 223 interposed therebetween. Therefore, no additional process for forming the storage capacitor is necessary.

Subsequently, as shown in FIG. 2F, after the protective film 216 is deposited on the entire surface including the transmissive electrode 217b, a thick photoacrylic resin is applied thereon, and then the uneven pattern is used as a photoetching technique using a fourth mask. 290 is formed.

The uneven pattern is formed on the n-type TFT region and is not formed on the p-type TFT region for p + doping.

The uneven pattern 290 is formed in a plurality of hemispherical or semi-elliptic form at predetermined intervals. At this time, in order to control the curvature of the concave-convex pattern 290, the photoacrylic resin pattern may be ashed for a predetermined time to reflow.

Thereafter, p + ions such as boron (B) ions or BF2 ions are counter-doped to the entire surface of the insulating substrate 211 to change the second source / drain regions 225a and 225b of the p-type TFT region to p-type. . Then, the second source / drain regions 225a and 225b are activated.

The above counter doping is a type opposite to the impurity used in the LDD ion implantation to increase the substrate concentration of the LDD region by doping at a predetermined angle. As such, the reason why the counter doping is additionally performed in the LDD ion implantation is to solve the punch-through phenomenon.

The punch-through phenomenon is a problem caused by a short channel effect. In the short channel effect, as the degree of integration of a device increases, the size of the device becomes smaller and the internal electric field becomes larger, resulting in stable for a long time. It is difficult to operate the device.

In this way, the number of times of mask use can be reduced once by using the uneven pattern without forming the mask with a photoresist for the p + doping process.

Next, as shown in FIG. 2G, an organic insulating material such as BCB or an acrylic resin having a low dielectric constant is coated on the entire surface including the uneven pattern 290 to form an organic insulating layer 316 along the surface of the uneven pattern 290. To form.

The organic insulating layer 316 protects the uneven pattern 290 and controls the curvature of the uneven pattern 290.

Subsequently, as shown in FIG. 2H, the gate insulating film 213, the interlayer insulating film 223, the protective film 216, and the organic insulating film 316 are collectively etched as a photo etching technique using the fifth mask. The first contact hole 271 is formed to expose the first and second source / drain regions 215a, 215b, 225a, and 225b of the p-type TFT, and at the same time, the protective film 216 and the organic insulating film 316 are formed. A portion of the transparent electrode 217b is removed to form a transparent portion open area 281 so that most of the transparent electrode 217b is exposed.

At this time, the positions of the transmissive portion and the reflecting portion are different by the steps of the passivation layer 216 and the organic insulating layer 316. Since the passivation portion 216 and the organic insulating layer 316 have the same level as that of the liquid crystal layer, the transmissive portion is the reflecting portion. It is located further down by the step of the liquid crystal layer. Therefore, the light incident on the reflecting portion and the light incident on the transmitting portion reach the screen surface at the same time.

That is, the light incident from the outside to the reflecting unit passes through the liquid crystal layer twice to reach the screen surface, and the light incident from the backlight passes through the liquid crystal layer after passing through the passivation layer and the organic insulating layer having the step of the liquid crystal layer. To reach the screen surface, thus reaching at the same time.

Meanwhile, in order to etch the gate insulating film 213, the interlayer insulating film 223, and the protective film 216, dry etching is generally performed. In the dry etching process, the gas is injected into the etching chamber in a high vacuum state and then placed into a plasma state. It is used to etch the insulating film in such a way as to deform and etch a predetermined region of the layer to be etched so that the cation or radical can be used to etch the insulating layer, and the precision of the pattern is relatively excellent.

The dry etching technique is a method of plasma etching, PE (Reactive Ion Etching), Magnetic Enhanced Enhanced Reactive Ion Etching (MERIE), Electron Cyclotron Resonance (ECR), Transformer Coupled Plasma (TCP), etc. Among them, the liquid crystal display device manufacturing process mainly uses the PE, RIE mode.

Lastly, as shown in FIG. 2I, a metal layer having high reflectivity and low resistance is deposited on the entire surface including the organic insulating layer 316 and patterned by photolithography using a sixth mask to form first and second source / drain electrodes. 215c, 215d, 225c, and 225d and the reflective electrode 217a are formed at the same time.

The reflective electrode 217a is connected to the transmissive electrode 217b through the transmissive part open area 281, and is formed along the surface of the uneven pattern 290 to have a plurality of hemispherical reflective unevennesses. The reflection irregularities widen the viewing angle by locally changing the reflection angle of the external natural light as a light source, thereby securing a considerable amount of reflected light.

The metal layer is made of copper (Cu), aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum-tungsten (MoW) and the like. .

At this time, when the first source / drain electrodes 215c and 215d are formed, the data line 215e crossing the gate line 212a is simultaneously formed. The gate lines 212a and the data lines 215e that cross each other define each pixel area.

In addition, the first and second source / drain electrodes 215c, 215d, 225c, and 225d are connected to the first and second source / drain regions 215a, 215b, 225a, and 225b, and the first source electrode 215a is integrally formed with the data line 215e, and the first drain electrode 215b is integrally formed with the reflective electrode 217a.

In this way, the number of times of mask use can be reduced by forming the source / drain electrodes and the reflective electrodes at the same time.

Thus, an n-type TFT composed of the first gate electrode 212, the first source / drain electrodes 215c and 215d, and the first channel layer 214 and formed for each pixel and driving the pixels, A p-type TFT including the second gate electrode 222, the second source / drain electrodes 225c and 225d, and the second channel layer 224 and formed in a driving circuit part and applying a signal to each gate wiring and data wiring. The CMOS thin film transistor is completed.

The CMOS-TFT array substrate thus formed usually uses an array of seven masks to form an array substrate including an n-type TFT and a p-type TFT.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The method of manufacturing the transflective liquid crystal display device of the present invention as described above has the following effects.

First, by using a gate etch back technique, it is possible to perform both a high concentration of n-type impurity ion doping, a low concentration of n-type impurity ion doping, and a counter doping step by using a single mask.

Second, since the lower electrode of the storage capacitor is formed at the same time as the gate electrode, and the upper electrode of the storage capacitor uses the transmissive electrode, the number of times of using the mask can be reduced once.

Third, the number of times of mask use can be reduced by forming the source / drain electrodes and the reflective electrodes at the same time.

Fourth, instead of forming the mask with a photoresist for the p-doping process, the number of times of use of the mask can be reduced once by using an uneven pattern.

Fifth, the transflective liquid crystal display device according to the present invention can reduce manufacturing cost, process time, and is effective for mass production by reducing the number of masks used in the past 11 times to 6 times.

Sixthly, the cell gap difference between the reflecting portion and the transmitting portion is appropriately made. That is, by providing the protective film steps of the reflecting portion and the transmitting portion by the distance passing through the liquid crystal layer once, the light incident on the reflecting portion and the light incident on the transmitting portion reach the screen surface at the same time.

Seventh, an organic insulating film for curvature control is further formed on the protective film on which the uneven pattern is formed, and by performing a separate process of patterning the protective film and the organic insulating film, the surface step unevenness of the organic insulating film due to the batch etching of the protective film and the organic insulating film is performed. Will improve the problem.

1A to 1L are process cross-sectional views of a transflective liquid crystal display device according to the prior art.

2A to 2I are process cross-sectional views and II-II line plan views for explaining the manufacturing process of the transflective liquid crystal display device according to the present invention.

* Explanation of symbols on the main parts of the drawings

211: insulating substrate 212: gate electrode

214: channel layer 215a, 215b: source / drain area

215c and 215d: source / drain electrodes 217a: reflective electrode

217b: transmission electrode 219: storage electrode

231: first photoresist

254: semiconductor layer 271: first contact hole

281: transmissive part open area 288: LDD doped layer

290: uneven pattern

Claims (12)

Forming first and second semiconductor layers on the insulating substrate; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming a gate electrode and a storage electrode on the gate insulating film; Implanting n-type impurities into the first semiconductor layer using the gate electrode as a mask to form source / drain regions of the n-type TFT; Forming an interlayer insulating film on the entire surface including the gate electrode; Forming a transmission electrode on the interlayer insulating film; Forming a protective film on the entire surface including the transmissive electrode; Forming an uneven pattern on the passivation layer where the n-type TFT region and the transmission electrode are located; Implanting p-type impurities into the second semiconductor layer using the uneven pattern as a mask to form source / drain regions of a p-type TFT; Forming an organic insulating film along a surface of the uneven pattern; Forming a contact hole and an open area to which the source / drain area and the transmission electrode are respectively exposed; And simultaneously forming a source / drain electrode connected to the source / drain region through the contact hole and a reflective electrode connected to the transmissive electrode through the open region. Manufacturing method. The method of claim 1, wherein the source / drain electrodes and the reflective electrodes are formed on the organic insulating layer. The method of claim 1, Bonding an opposing substrate to the insulating substrate; A method of manufacturing a transflective liquid crystal display device, characterized by further comprising forming a liquid crystal layer between the two substrates. The method of claim 1, wherein the forming of the uneven pattern may include: Forming the protective film; Applying photo acrylic on the protective film; And forming a concave-convex pattern by patterning the photoacrylic. The method of manufacturing a transflective liquid crystal display device according to claim 1, wherein the laminated film of the protective film, the uneven pattern and the organic insulating film is formed to have a thickness of the liquid crystal layer cell gap. The method of claim 1, wherein the forming of the contact hole and the open area to which the source / drain area and the transmissive electrode are exposed, respectively, Applying and patterning photoresist on the organic insulating film; Forming a contact hole by collectively etching the organic insulating film, the protective film, the interlayer insulating film, and the gate insulating film exposed between the patterned photoresist, and forming an open region by collectively etching the organic insulating film and the protective film. A method of manufacturing a transflective liquid crystal display device. The method of claim 1, wherein the source / drain regions are each formed of an n + doped layer or a p + doped layer, respectively. The method of claim 7, wherein the forming of the first source / drain region, which is the n + doped layer, and the second source / drain region, which is the p + doped layer, comprises: Forming an n + doped layer in the first source / drain region; Forming an LDD layer inside the n + doped layer, And forming a p + doped layer in the second source / drain region after masking the n + doped layer. The method of claim 1, wherein the transmissive electrode is formed to overlap the storage electrode. The method of claim 1, wherein the reflective electrode is integrated with the first drain electrode. The method of claim 1, wherein the passivation layer has a transmissive part open area in the transmissive part. The method of claim 1, wherein a buffer layer is further provided between the substrate and the first and second semiconductor layers.