KR20050120873A - Driving circuit and method of inverter for liquid crystal display device and liquid crystal display device - Google Patents

Abstract

Disclosure of Invention An object of the present invention is to provide an inverter for a liquid crystal display device, which can solve a problem in which a power loss occurs because the switching signals input to the p-type transistor and the n-type transistor of the inverter for the liquid crystal display device have the same phase. A driving circuit, a driving method, and a liquid crystal display device are provided.

The present invention is a driving circuit for driving an inverter for a liquid crystal display device in which an n-type transistor and a p-type transistor are arranged in a full bridge form, and in a low state by delaying a source signal in which a high state and a low state are alternately repeated. A signal delay unit configured to generate a delayed signal delayed by the T1 time to the high state and delayed by the T2 time to the low state from the high state; OR calculating means for ORing the delay signal and the source signal to generate a first switching signal input to the p-type transistor; An AND driving means for performing an AND operation on the delay signal and the source signal to generate a second switching signal input to the n-type transistor is provided.

According to the present invention, the p-type transistor and the n-type transistor are alternately turned on at a time difference with each other. Accordingly, the p-type transistor and the n-type transistor are simultaneously driven on at the same time as in the prior art, thereby overloading the entire switching circuit. There is an effect that can improve the power loss caused by the chute current.

Description

Inverter driving circuit and driving method for liquid crystal display device and liquid crystal display device {Driving circuit and method of inverter for liquid crystal display device and liquid crystal display device}

The present invention relates to a liquid crystal display device, and more particularly, to a driving circuit and a driving method for driving an inverter for a liquid crystal display device for supplying power to a lamp of the liquid crystal display device.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. Recently, liquid crystal display (LCD), plasma display panel (PDP), electro luminescent display (ELD), and VFD (vacuum) Various flat panel displays such as fluorescent displays are used.

Among flat panel displays, liquid crystal displays are widely used because they can be driven with low power and have excellent image quality.

The liquid crystal display device includes two substrates facing each other and a liquid crystal interposed between the two substrates. Two substrates of a liquid crystal display device correspond to an array substrate on which a thin film transistor (TFT) is formed and a color filter substrate on which a color filter is formed.

Such a liquid crystal display device is a non-light emitting display device and requires a separate light source. Therefore, a lamp is used as a light source to supply light to the liquid crystal display.

The lamp is an electroluminescent lamp (EL), cold cathode fluorescence lamp (CCFL) is used, such a lamp is powered by an AC power source.

The inverter is connected to the lamp to supply AC power to the lamp. The inverter converts the input DC power into AC power and supplies it to the lamp.

1 is a view showing a conventional inverter for a liquid crystal display device.

As shown, the inverter 160 includes a switching circuit 161 and a transformer 162.

In the switching circuit 161, the n-type transistors NT1 and NT2 and the p-type transistors PT1 and PT2 are disposed in a full bridge form. That is, the first p-type transistor PT1 and the first n-type transistor NT1 are connected in series and the second n-type transistor NT2 connected in parallel with the first p-type transistor PT1. A second p-type transistor PT2 connected in parallel with the first n-type transistor NT1 is connected in series.

Each of the first and second p-type transistors PT1 and PT2 and the first and second n-type transistors NT1 and NT2 has a diode D _P1 , D _P2 , D _N1 , D _N2 and a capacitor in parallel as a buffer circuit. (C _P1 , C _P2 , C _N1 , C _N2 ) are connected to prevent the transistors PT1, PT2, NT1, NT2 from being overloaded.

The switching circuit 161 switches the DC voltage V _DC input from the power input unit 170 through the transistors PT1, PT2, NT1, and NT2, so that the first p-type transistor PT1 and the first n-type transistor are switched. contact a voltage V _a and the n- type 2 transistor (NT2) and a p- type 2 transistor (PT2), the difference voltage V _AB between the voltage V _B at the point B of the transformer 162 of the in the (NT1) Will be delivered to

The transformer 162 converts the differential voltage V _AB into an alternating voltage V _AC by mutual induction of the core, the wound primary coil, and the secondary coil. The converted AC voltage V _AC is supplied to the lamp 150 to drive the lamp 150.

The transistors PT1, PT2, NT1, NT2 of the switching circuit 161 generating the differential voltage V _AB input to the transformer 162 are turned on / off by the switching signals SW1, SW2 input from the outside. OFF) is driven.

2 is a diagram showing waveforms of switching signals input to a switching circuit of an inverter for a liquid crystal display.

The switching signals SW1 and SW2 are input to the gate terminals of the p-type transistors (see PT1 and PT2 in FIG. 1) and the n-type transistors (see NT1 and NT2 in FIG. 1), respectively, to provide a p-type transistor and an n-type transistor. The transistor is turned on / off.

The switching signals SW1 and SW2 include a first switching signal SW1 input to the p-type transistor and a second switching signal SW2 input to the n-type transistor.

The first and second switching signals SW1 and SW2 have the same phase. The p-type transistor is turned off in the high state of the first switching signal, and the p-type transistor is turned on in the low state of the first switching signal. The n-type transistor is driven on in the high state of the second switching signal, and the n-type transistor is driven off in the low state of the second switching signal.

When the first and second switching signals SW1 and SW2 are input to the switching circuit (see 161 in FIG. 1), the p-type transistor and the n-type transistor are repeatedly turned on and off without overlapping each other. Therefore, the first and second switching signals SW1 and SW2 correspond to ideal waveforms.

However, the first and second switching signals SW1 and SW2 are theoretical waveforms, and the boundary time point tb is changed from the first and second switching signals SW1 and SW2 to a high state and a low state when input to an actual switching circuit. In this case, the p-type transistor and the n-type transistor can be driven on simultaneously.

When the p-type transistor and the n-type transistor are simultaneously driven on, the entire switching circuit is shorted and the entire circuit is overloaded. In addition, a shoot current phenomenon occurs in which the current Id flowing in the transistor instantly rises, resulting in a relationship such as {P (power) = Vds (voltage between the source and drain terminals) * Id}. As a result, power loss occurs.

SUMMARY OF THE INVENTION An object of the present invention for solving the above-described problems is that the switching signals input to the p-type transistor and the n-type transistor of the inverter for a liquid crystal display have the same phase with each other, thereby causing a power loss. The present invention provides an inverter driving circuit, a driving method, and a liquid crystal display device for improving a liquid crystal display device.

In order to achieve the above object, the present invention provides a driving circuit for driving an inverter for a liquid crystal display device in which an n-type transistor and a p-type transistor are arranged in a full bridge shape, wherein a high state and a low state are alternately performed. A signal delay unit for delaying the repeated source signal to generate a delayed signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state; OR calculating means for ORing the delay signal and the source signal to generate a first switching signal input to the p-type transistor; An AND driving means for performing an AND operation on the delay signal and the source signal to generate a second switching signal input to the n-type transistor is provided.

The signal delay unit may include a first signal delay unit for generating a first delay signal input to the OR calculation unit, and a second signal delay unit for generating a second delay signal input to the AND calculation unit. .

The signal delay unit may use an RC delay circuit using a resistor and a capacitor.

The OR calculating means may use an OR gate, and the AND calculating means may use an AND gate.

In another aspect, the present invention is a driving method for driving an inverter for a liquid crystal display device in which an n-type transistor and a p-type transistor are arranged in a full bridge form, and delaying a source signal in which a high state and a low state are alternately repeated. Generating a delayed signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state; ORing the delay signal and the source signal to generate a first switching signal input to the p-type transistor; And an AND operation of the delay signal and the source signal to generate a second switching signal input to the n-type transistor.

The generating of the delay signal may include generating a first delay signal used for the OR operation, and generating a second delay signal used for the AND operation.

The generating of the delay signal may include delaying the source signal using an RC delay circuit using a resistor and a capacitor.

The OR operation may be performed using an OR gate, and the AND operation may be performed using an AND gate.

In another aspect, the present invention, the data driver for outputting a data signal; A gate driver for outputting a gate signal; A liquid crystal panel which receives the data signal and the gate signal and displays an image; A lamp for supplying light to the liquid crystal panel; an inverter including a switching circuit in which an n-type transistor and a p-type transistor are arranged in a full bridge form to switch a DC voltage, and a transformer for converting the DC voltage output from the switching circuit into an AC voltage and supplying the lamp to the lamp; ; A signal delay unit for delaying a source signal in which a high state and a low state are alternately repeated, generating a delay signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state; OR calculation means for generating the first switching signal inputted to the p-type transistor by ORing the source signal, and second switching signal inputted to the n-type transistor by ANDing the delay signal and the source signal. It provides a liquid crystal display device comprising an inverter drive circuit including an AND operation means for generating a.

The apparatus may further include a source signal generator for generating the source signal, and a signal controller for controlling operations of the gate driver and the data driver.

The present invention changes the phase of a switching signal input to each of a p-type transistor and an n-type transistor of an inverter for a liquid crystal display. Therefore, the p-type transistor and the n-type transistor are not driven on at the same point in time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<First Embodiment>

3 is a diagram illustrating a liquid crystal display device including a driving circuit of an inverter for a liquid crystal display device according to a first embodiment of the present invention. 4 is a view showing an inverter for a liquid crystal display according to a first embodiment of the present invention, and FIG. 5 is a view showing a switching signal generation unit according to the first embodiment of the present invention.

As shown in FIG. 3, the LCD 200 according to an exemplary embodiment of the present invention includes a liquid crystal panel 210, a gate driver and a data driver 220 and 230, a signal controller 240, and a lamp ( 250, an inverter 260, a power input unit 270, a switching signal generator 280, and a source signal generator 290.

The liquid crystal panel 210 is a display panel that displays an image and includes two substrates (not shown) facing each other and a liquid crystal layer (not shown) between the two substrates. The liquid crystal panel 210 is positioned at a portion where the gate lines and the data lines GL and DL and the gate lines GL and the data lines DL intersect to define the pixels P arranged in a matrix form. The thin film transistor T and the liquid crystal capacitor C _LC connected to the thin film transistor T are positioned. The thin film transistor T is driven on / off according to the gate signal transmitted through the gate line GL, and the data signal is transferred through the data line DL when the thin film transistor T is turned on. The capacitor C _LC is charged to display an image.

The gate driver 220 sequentially outputs the gate signal to the gate line GL, and the data driver 230 outputs the data signal to the data line DL.

The signal controller 240 outputs a data signal to the data driver 230 according to timing, and outputs various control signals to the gate driver and the data drivers 220 and 230 to gate drivers and data drivers 220 and 230. ) To control the operation.

The lamp 250 receives power from the inverter 260 to supply light to the liquid crystal panel 210.

The inverter 260 converts the DC voltage V _DC input from the power input unit 270 to supply the _AC voltage V _AC to the lamp 250.

As shown in FIG. 4, the inverter 260 includes a switching circuit 261 and a transformer 262.

In the switching circuit 261, the n-type transistors NT1 and NT2 and the p-type transistors PT1 and PT2 are disposed in a full bridge form. That is, the first p-type transistor PT1 and the first n-type transistor NT1 are connected in series and the second n-type transistor NT2 connected in parallel with the first p-type transistor PT1. A second p-type transistor PT2 connected in parallel with the first n-type transistor NT1 is connected in series.

Each of the first and second p-type transistors PT1 and PT2 and the first and second n-type transistors NT1 and NT2 is a diode D _P1 , D _P2 , D _N1 , D _N2 arranged in parallel as a buffer circuit. And capacitors C _P1 , C _P2 , C _N1 and C _N2 are connected to prevent the transistors PT1, PT2, NT1, NT2 from being overloaded.

The switching circuit 261 switches the DC voltage V _DC input from the power input unit 270 through the transistors PT1, PT2, NT1, and NT2, so that the first p-type transistor PT1 and the first n-type transistor are switched. contact a voltage V _a and the second n- type transistor (NT2) and a second difference voltage V _AB between the voltage V _B at the contact point B of the p- type transistor (PT2), the transformer 262 at the (NT1) Will be delivered to

The transformer 262 converts the differential voltage V _AB into an AC voltage V _AC according to the mutual induction of the core, the wound primary coil, and the secondary coil. The converted AC voltage V _AC is supplied to the lamp 250 to drive the lamp 250.

Transistors PT1, PT2, NT1, NT2 of the switching circuit 261 generating the differential voltage V _AB input to the transformer 262 are output from the switching signal generator 280 (see 280 of FIG. 3). It is driven on / off by SW2).

As shown in FIG. 5, the switching signal generator 280 converts the source signal S input from the source signal generator (see 290 of FIG. 3) to convert the first and second switching signals SW1 and SW2. Will print.

The switching signal generator 280 includes a first switching signal generator 281 for generating a first switching signal SW1 input to a p-type transistor (see PT1 and PT2 in FIG. 4), and an n-type transistor ( And a second switching signal generator 282 for generating a second switching signal SW2 input to NT1 and NT2 of FIG. 4.

As shown in FIG. 3, the source signal generator 290 generates a source signal S of a square wave. The source signal generator 290 may be located in the signal controller 240.

6 and 7 illustrate first and second switching signal generation units according to the first embodiment of the present invention, respectively. 8 is a diagram illustrating waveforms of signals input and output to the first and second switching signal generation units according to the first embodiment of the present invention.

As illustrated in FIG. 6, the first switching signal generation unit 281 includes a first signal delay unit 283 and an OR calculation unit 285.

The first signal delay unit 283 delays the input source signal S by using an RC delay circuit using the resistors Rc and Rv and the capacitor C. The resistors Rc and Rv are configured by connecting a fixed resistor Rc having a fixed resistance value and a variable resistor Rv in parallel, and one electrode of the capacitor C has a fixed resistor Rc and a variable resistor Rv. ) And the other electrode is grounded. Here, the fixed resistor Rc may be connected in series with the diode D. The OR calculation unit 285 performs an OR operation on the input signal and outputs the OR signal. An OR gate may be used.

As shown in FIG. 7, the second switching signal generation unit 282 includes a second signal delay unit 284 and an AND operation unit 286.

In the first embodiment of the present invention, the second signal delay unit 284 has the same configuration as that of the first signal delay unit (see 283 in FIG. 6).

The second signal delay unit 284, like the first signal delay unit, delays the input source signal S using an RC delay circuit using the resistors Rc and Rv and the capacitor C. do.

The resistors Rc and Rv are composed of a fixed resistor Rc having a fixed resistance value and a variable resistor Rv connected in parallel, and one electrode of the capacitor C is a fixed resistor Rc and a variable resistor Rv. ) And the other electrode is grounded. Here, the fixed resistor Rc may be connected in series with a diode. The AND operation unit 286 performs an AND operation on the input signal and outputs the AND gate. An AND gate may be used.

As shown in FIG. 8, when the source signal S, which is a square wave in which the high state and the low state are alternately repeated, is input to the first switching signal generation unit (see 281 in FIG. 6), the first signal delay unit ( Referring to 283 of FIG. 6), the source signal S is delayed by the time constant τ of the RC delay according to the resistor (see Rc and Rv of FIG. 6) and the capacitor (see C of FIG. 6). ) Will be printed. That is, according to the time constant τ of the resistor and the capacitor, the first delay signal SDP is delayed and rises from the low state to the high state by the time Tr at the rising time tr of the source signal S. At the falling time (tf: falling time) of the signal S, the signal S is delayed and lowered from the high state to the low state by the time Tf. Here, Tr and Tf correspond to the same time.

The OR calculating means (see 285 of FIG. 6) OR-operates the input source signal S and the first delay signal SDP to output the first switching signal SW1. Since the first delay signal SDP is delayed by the Tf time at the falling time tf of the source signal S, the low delay state becomes a low state. Thus, the high state of the first switching signal SW1 is low when the first delay signal SDP is low. The first delayed signal SDP is maintained until the first delay signal SDP is reached from the high state to the low state at the time when the state rises to the high state. That is, the high state of the first switching signal SW1 is maintained for a time between the end of the low state of the first delay signal SDP and the start of the next low state.

The low state of the first switching signal SW1 is maintained for the low state time of the first delay signal SDP.

On the other hand, when the source signal S is input to the second switching signal generation unit (see 282 in FIG. 7), the second signal delay unit (see 284 in FIG. 7) may include a resistor (see Rc and Rv in FIG. 7) and a capacitor. The source signal S is delayed by the time constant? Of the RC delay according to (see FIG. 7C), and the second delay signal SDN having the same phase as the first delay signal SDP is output. That is, according to the time constant τ of the resistor and the capacitor, the second delay signal SDN is delayed and increased by the time of Tr from the low state to the high state at the rising time tr of the source signal S, and increases. At the time of fall tf, the voltage falls from the high state to the low state by a delay time of Tf.

The AND calculating means (see 286 of FIG. 7) performs an AND operation on the input source signal S and the second delay signal SDN to output the second switching signal SW2. Since the second delay signal SDN is delayed by the time Tr at the rising point tr of the source signal S and becomes high, and is delayed by the time Tf at the falling time tf of the source signal S, the second delay signal SDN is lowered. The high state of the switching signal SW2 is maintained for the high state time of the second delay signal SDN.

The low state of the second switching signal SW2 is from the time when the second delay signal SDN falls from the high state to the low state until the time when the second delay signal SDN rises from the low state to the next high state. maintain. That is, the low state of the second switching signal SW2 is maintained for the time between the end of the high state of the second delay signal SDN and the start of the next high state.

The first and second switching signals SW1 and SW2 generated as described above are input to the switching circuit 261 of FIG. 4.

The first switching signal SW1 is input to the gate terminal of the p-type transistor (see PT1 and PT2 in FIG. 4), and the second switching signal SW2 is connected to the n-type transistor (see NT1 and NT2 in FIG. 4). It is input to the gate terminal to drive the p-type transistor and the n-type transistor on / off.

The p-type transistor is driven off in the high state of the first switching signal SW1 and the p-type transistor is driven in the low state of the first switching signal SW1. The n-type transistor is driven on in the high state of the second switching signal SW2, and the n-type transistor is driven off in the low state of the second switching signal SW2.

The low state of the first switching signal SW1 and the high state of the second switching signal SW2 for driving on the p-type transistor and the n-type transistor, respectively, have a time difference, i.e., a delay time Tr, Tf. And alternately placed. Therefore, the p-type transistor and the n-type transistor are driven on alternately with a time difference of the delay times Tr and Tf.

In the first embodiment of the present invention, although the first and second signal delay units having the same resistance and capacitor and the same time constant are used, signal delay units having different configurations and time constants may be used in case of signal delay. have.

Second Embodiment

In the second embodiment of the present invention, the switching signal generation unit includes a signal delay unit, an OR operation unit, and an AND operation unit. In the second embodiment, the circuit is simply fabricated by integrating one signal delay unit positioned in each of the first and second switching signal generation units in the first embodiment.

In the second embodiment of the present invention, description of the same or corresponding matters as the first embodiment will be omitted.

9 is a diagram illustrating a switching signal generator according to a second embodiment of the present invention.

As illustrated, the switching signal generation unit 380 includes a signal delay unit 387, an OR operation unit 385, and an AND operation unit 386.

The signal delay unit 387 has the same configuration as the signal delay unit (see 283 in FIG. 6 and 284 in FIG. 7) of FIG. 6 or 7 in the first embodiment. The signal delay unit 387 delays the input source signal S and outputs the delayed signal SD having the same phase to the OR calculation unit 385 and the AND calculation unit 386.

The OR calculating means 385 ORs the delay signal SD and the source signal S to output the first switching signal SW1. The AND calculating means 386 performs an AND operation on the delay signal SD and the source signal S to output the second switching signal SW2.

The first and second switching signals SW1 and SW2 have the signal waveforms of FIG. 8 of the first embodiment. Therefore, the p-type transistor and the n-type transistor are alternately driven on with a time difference by the delay time.

According to the present invention, the p-type transistor and the n-type transistor are alternately turned on with a time difference of a delay time Tr and Tf, and thus the p-type transistor and the n-type transistor are simultaneously driven on. Overloading the entire switching circuit and power loss caused by the chute current can be improved.

Embodiment of the present invention as described above is an example of the present invention, various modifications are possible. When such modifications are included in the spirit of the present invention, it is obvious to those skilled in the art that they fall within the scope of the present invention. The scope of the invention will be apparent from the claims.

According to the present invention, the p-type transistor and the n-type transistor are alternately turned on with a time difference by the delay time, and as a result, the p-type transistor and the n-type transistor are simultaneously driven on simultaneously to the whole switching circuit. Overload and power loss caused by the chute current can be improved.

1 is a view showing a conventional inverter for a liquid crystal display device.

2 is a diagram showing waveforms of switching signals input to a switching circuit of an inverter for a liquid crystal display device.

3 is a view showing a liquid crystal display device including a driving circuit of an inverter for a liquid crystal display device according to a first embodiment of the present invention.

4 is a view showing an inverter for a liquid crystal display device according to a first embodiment of the present invention.

5 is a diagram illustrating a switching signal generator according to a first embodiment of the present invention.

6 and 7 are diagrams illustrating first and second switching signal generation units according to the first embodiment of the present invention, respectively.

8 is a diagram illustrating waveforms of signals input and output to the first and second switching signal generation units according to the first embodiment of the present invention.

9 is a view showing a switching signal generation unit according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

281 and 282: first and second switching signal generator

283, 284: first and second signal delay unit

285, 286: OR, AND calculation means

S: Source signal

SDP, SDN: 1st, 2nd delay signal

SW1, SW2: first and second switching signals

Claims (10)

A driving circuit for driving an inverter for a liquid crystal display device in which an n-type transistor and a p-type transistor are arranged in a full bridge shape, A signal delay unit for delaying a source signal in which the high state and the low state are alternately repeated to generate a delay signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state; OR calculating means for ORing the delay signal and the source signal to generate a first switching signal input to the p-type transistor; AND operation means for generating an AND operation on the delayed signal and the source signal to generate a second switching signal input to the n-type transistor. Inverter drive circuit for a liquid crystal display device comprising a. The method of claim 1, The signal delay unit includes a first signal delay unit for generating a first delay signal input to the OR calculation unit, and a second signal delay unit for generating a second delay signal input to the AND calculation unit. Inverter driving circuit. The method of claim 1, The signal delay unit is an inverter driving circuit for a liquid crystal display using an RC delay circuit using a resistor and a capacitor. The method of claim 1, And said OR calculating means uses an OR gate and said AND calculating means uses an AND gate. A driving method for driving an inverter for a liquid crystal display device in which an n-type transistor and a p-type transistor are arranged in a full bridge form, Generating a delay signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state by delaying a source signal in which the high state and the low state are alternately repeated; ORing the delay signal and the source signal to generate a first switching signal input to the p-type transistor; ANDing the delay signal and the source signal to generate a second switching signal input to the n-type transistor Inverter driving method for a liquid crystal display device comprising a. The method of claim 5, The generating of the delay signal may include generating a first delay signal used in the OR operation, and generating a second delay signal used in the AND operation. The method of claim 5, The generating of the delay signal may include delaying the source signal using an RC delay circuit using a resistor and a capacitor. The method of claim 5, And the OR operation is performed using an OR gate, and the AND operation is performed using an AND gate. A data driver for outputting a data signal; A gate driver for outputting a gate signal; A liquid crystal panel which receives the data signal and the gate signal and displays an image; A lamp for supplying light to the liquid crystal panel; an inverter including a switching circuit in which an n-type transistor and a p-type transistor are arranged in a full bridge form to switch a DC voltage, and a transformer for converting the DC voltage output from the switching circuit into an AC voltage and supplying the lamp to the lamp; ; A signal delay unit for delaying a source signal in which a high state and a low state are alternately repeated, generating a delay signal delayed by a T1 time from a low state to a high state and delayed by a T2 time from a high state to a low state; OR calculation means for generating the first switching signal inputted to the p-type transistor by ORing the source signal, and second switching signal inputted to the n-type transistor by ANDing the delay signal and the source signal. Inverter drive circuit comprising an AND operation means for generating a Liquid crystal display comprising a. The method of claim 9, And a signal controller for controlling the operation of the gate driver and the data driver.