KR20050122688A - Scan driving apparatus and method of light emitting display using the same - Google Patents

Abstract

The present invention relates to a light emitting display device capable of reducing a kickback voltage.

According to an exemplary embodiment of the present invention, a light emitting display device includes scan lines, data lines formed in a direction crossing the scan lines, a pixel positioned at an intersection of the scan lines and the data lines, and the pixel to be selected. And a scan driver for sequentially supplying a selection signal having a stepped wave shape to the scan lines.

By such a configuration, the kickback voltage of the pixel can be minimized in the present invention, thereby improving image quality.

Description

SCAN DRIVING APPARATUS AND METHOD OF LIGHT EMITTING DISPLAY USING THE SAME}

The present invention relates to a scan driver, a light emitting display device using the same, and a driving method thereof, and more particularly, to a scan driver capable of reducing kickback voltage, a light emitting display device using the same, and a method of driving the same.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption.

1 is a circuit diagram illustrating a pixel of a conventional light emitting display device.

Referring to FIG. 1, when the selection signal is applied to the scan line S, the pixel 10 of the conventional light emitting display generates light corresponding to the data signal supplied to the data line D. FIG.

As shown in FIG. 2, the selection signal SS is sequentially supplied to the scan line S from the first scan line S1 to the nth scan line Sn. The data signals are supplied to the data lines D to be synchronized with the selection signal SS.

Each pixel 10 includes an organic light emitting element OLED and a pixel circuit 12 connected to the data line D and the scan line S to emit light of the organic light emitting element OLED.

To this end, each pixel 10 includes an organic light emitting element OLED and a pixel circuit 12 connected to a data line D, a scan line S, and an anode electrode of the organic light emitting element OLED.

The anode electrode of the organic light emitting element OLED is connected to the pixel circuit 12, and the cathode electrode is connected to the second power source VSS. The organic light emitting diode OLED includes an emission layer, an electron transport layer, and a hole transport layer formed between the anode electrode and the cathode electrode. The organic light emitting diode OLED may further include an electron injection layer and a hole injection layer. When a voltage is applied between the anode electrode and the cathode electrode of the OLED, the electrons generated from the cathode move to the emission layer via the electron injection layer and the electron transport layer, and the electrons generated from the anode electrode are hole injected. It moves to the light emitting layer via the layer and the hole transport layer. Then, light is generated by recombination of electrons supplied from the electron transport layer and holes supplied from the hole transport layer in the light emitting layer.

The pixel circuit 12 includes a driving thin film transistor ("TFT") DT connected between the first power supply VDD and the organic light emitting diode OLED, the driving TFT DT, and data. The switching element SW connected between the line D and the scanning line S and the storage capacitor Cst connected between the gate electrode and the source electrode of the driving TFT DT are provided. In FIG. 1, each of the TFTs DT and SW is a P-type metal oxide semiconductor field effect transistor (MOSFET).

The gate electrode of the switching element SW is connected to the scan line S, and the source electrode is connected to the data line D. The drain electrode of the switching element SW is connected to the first terminal of the storage capacitor Cst. The switching device SW is turned on when the selection signal is supplied from the scan line S to supply the data signal supplied from the data line D to the storage capacitor Cst. At this time, the storage capacitor Cst is charged with a voltage corresponding to the data signal.

The gate electrode of the driving TFT DT is connected to the first terminal of the storage capacitor Cst, and the source electrode is connected to the second terminal of the storage capacitor Cst and the first power source VDD. The drain electrode of the driving TFT DT is connected to the anode electrode of the organic light emitting element OLED. The driving TFT DT controls the amount of current flowing from the second power supply VDD to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. In this case, the organic light emitting diode OLED generates light having a luminance corresponding to the amount of current supplied from the driving TFT DT.

However, such a conventional light emitting display device has a problem in that image quality is degraded due to a kickback phenomenon. In detail, the parasitic capacitor Cgd is equivalently formed between the gate electrode and the drain electrode of the switching element. Here, the voltage of the storage capacitor Cst is changed when the switching device SW is turned from the turn-on state to the turn-off state by the parasitic capacitor Cgd. The kickback voltage is one of the causes of the change. Can be mentioned. The kickback voltage is generated by redistributing the charge of the parasitic capacitor Cgd by changing the voltage across the parasitic capacitor Cgd when the potential of the selection signal is switched from the turn-on to the turn-off voltage.

The kickback voltage generated when the switching device SW is turned from the turn-on state to the turn-off state directly affects the voltage charged in the storage capacitor Cst. In other words, the kickback voltage fluctuates the storage voltage of the storage capacitor Cst, thereby causing a problem in that an image of a desired gray scale cannot be displayed.

Accordingly, an object of the present invention is to provide a scan driver capable of reducing a kickback voltage, a light emitting display device using the same, and a driving method thereof.

In order to achieve the above object, a light emitting display device according to an exemplary embodiment of the present invention may include scan lines, data lines formed in a direction intersecting the scan lines, and pixels positioned at intersections of the scan lines and the data lines. And a scan driver for sequentially supplying a stepped wave selection signal to the scan lines so that the pixel can be selected.

The scan driver includes a shift register for generating an output signal sequentially shifted according to a clock signal, and a negative logic gate (NAND) for generating a square wave signal by performing a logical operation on the output signal and an enable signal supplied from the outside. And a stepped wave generation unit connected to each of the negative AND gates to generate a stepped wave signal using the square wave signal.

Each pixel may include a switching device turned on by the selection signal, a driving transistor supplying a current corresponding to a data signal to the light emitting device when the switching device is turned on, and a voltage corresponding to the data signal. With a storage capacitor.

Each pixel includes a driving transistor for supplying a current corresponding to a data signal to the light emitting device, and a first switching unit including a compensation capacitor controlled by a first selection signal and compensating for a threshold voltage of the driving transistor. A storage capacitor configured to store a voltage corresponding to the data signal, a second switching unit configured to transfer the data signal to the storage capacitor in response to a second selection signal, and a light emission control line parallel to the scan line; And a switching element controlled by a light emitting signal supplied and controlling a timing of supply of a current supplied from the driving transistor to the light emitting element.

The scan driver supplies the light emission signal in the form of a staircase wave.

According to an embodiment of the present invention, a scan driver performs a logic operation on shift registers for generating an output signal sequentially shifted according to a clock signal and an enable signal supplied from the outside, and generates a square wave signal. And a stepped wave generation unit connected to each of the AND gates and the negative AND gates to generate a stepped wave signal using the square wave signal.

Each of the stepped wave generators includes a first switching device having a source electrode connected to a third power supply, a drain terminal connected to a first node, which is an output terminal of the negative AND gate, and a gate terminal connected to a control signal input terminal. Wow; And a second switching device having a source electrode connected to a fourth power supply, a drain terminal connected to the first node, and a gate terminal connected to the control signal input terminal.

The square wave signal is a signal that is lowered from the absolute second voltage to the absolute first voltage to maintain the absolute first voltage for a first period, and rises to the absolute second voltage after the first period.

The first and second switching elements are turned on for at least a part of a first period in which the square wave signal is supplied.

The first and second switching elements are turned on for a second period including a time point at which the square wave signal falls and a third period including a time point at which the square wave signal rises.

The third power supply is a pulse signal that is dropped to a reference voltage which is an intermediate voltage between the absolute first voltage and the absolute second voltage at a predetermined voltage during the second period and the third period.

The fourth power source is a DC voltage having a potential of the reference voltage.

The reference voltage is set to 0V.

The first node is set to the voltage value of the reference voltage during the second period and the third period, and the potential of the first node during the remaining period of the first period except the first period and the third period is It is set to the voltage value of the absolute first voltage.

And a buffer connected to the first node of each of the stepped wave generators to supply the stepped wave signal to the scan lines.

A method of driving a light emitting display device according to an exemplary embodiment of the present invention includes a first step of sequentially supplying a selection signal to select a pixel, and a second step of supplying a data signal to the pixels selected by the selection signal. And the selection signal is supplied in the form of a staircase wave.

The selection signal rises and falls in the stepped wave shape.

The method may further include supplying a light emission control signal to control the timing at which light is generated in the pixel.

The emission control signal is supplied in the form of a staircase wave.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIG. 3 to FIG. 9B to which a person skilled in the art may easily implement the present invention.

3 illustrates a light emitting display device according to an embodiment of the present invention.

Referring to FIG. 3, a light emitting display device according to an exemplary embodiment of the present invention includes an image display unit 100 including pixels 110 formed at an intersection area of scan lines S1 to Sn and data lines D1 to Dm. And a scan driver 120 for driving the scan lines S1 to Sn and a data driver 130 for driving the data lines D1 to Dm.

Each of the pixels 110 is selected by the selection signal SS applied to the scan line S, and displays an image corresponding to the data signal supplied to the data line D. FIG. Here, each pixel is formed in the structure as shown in FIG.

The data driver 130 supplies a data signal from the controller to the pixel 110 through the data lines D1 to Dm in response to data control signals supplied from a controller (not shown). In this case, the data driver 130 supplies data signals of one horizontal line to the data lines D1 to Dm every one horizontal period.

The scan driver 120 generates a selection signal for driving the scan lines S1 to Sn in response to the scan control signals supplied from the controller, that is, the start pulse and the clock signal, to sequentially scan lines S1 to Sn. Supply. Here, the scan driver 120 of the present invention supplies the selection signal SS in the form of a step wave as shown in FIG. 4. In other words, the scan driver 120 may rise in the form of a staircase wave when the selection signal SS falls and fall in the form of a staircase wave when the selection signal SS falls.

In this embodiment of the present invention, the scan driver 120 and / or the data driver 130 may be mounted in the form of a chip in a tape carrier package (TCP) electrically connected to the image display unit 100. Can be. In addition, the scan driver 120 and / or the data driver 130 may be mounted in the form of a chip in a flexible printed circuit (FPC) or a film that is electrically connected to the image display unit 100. . On the other hand, the scan driver 120 and / or the data driver 130 may be directly mounted on the substrate of the image display unit 100 as well as formed directly on the substrate.

The scan driver 120 transfers the shift register block 122 including the plurality of shift registers 122a through 122n, and the output and enable signal ENB of each stage of the shift registers 122a through 122n as shown in FIG. 5. A negative logic gate block 124 comprising a plurality of NAND gates 124a through 124n for logical combination, and a stepped waveform positioned to be connected to each of the negative logic gates 124a through 124n. A step wave generator block 126 including step wave generators 126a to 126n for generating, and buffers 128a to 128n positioned to be connected to each of the step wave generators 126a to 126n. Buffer block 128.

The shift registers 122a to 122n supply the start signal SP or the output signal of its upper shift register to the lower shift register. Here, the upper and lower represent the order according to the flow of the signal.

The negative logical gates 124a through 124n are provided at the output terminals of the shift registers 122a through 122n to logically operate the output signal of the shift registers 122a through 122n and the enable signal ENB. Here, the negative logical gates 124a to 124n sequentially generate a square wave signal.

The stepped wave generators 126a to 126n are installed at the output terminals of the negative logic gates 124a to 124n to convert the square wave signal inputted to the stepped wave signal. The buffers 128a to 128n supply the stepped wave signals supplied from the negative logic gate block 128 to the scan lines S1 to Sn. Here, the stepped wave signal output from the buffer block 128 is sequentially supplied to the scan lines S1 to Sn as shown in FIG. 4.

Meanwhile, each of the stepped wave generators 126a to 126n is configured as shown in FIG. 6 to convert the square wave signal into a stepped wave signal. Referring to FIG. 6, each of the stepped wave generators 126a to 126n includes first and second switching elements T1 and T2 disposed between the third power source VP and the fourth power source VP. . The first and second switching elements T1 and T2 are turned on and off in response to the control signal Vt supplied from the controller. The source electrode of the first switching element T1 is connected to the third power source VP, the drain electrode is connected to the first node N1, which is the output terminal of the negative logic gate, and the gate electrode is connected to the control signal input terminal. Connected. The source electrode of the second switching element T2 is connected to the fourth power supply VD, the drain electrode is connected to the first node N1, and the gate electrode is connected to the control signal input terminal.

The operation of the stepped wave generators 126a to 126n will be described in detail using the driving waveform of FIG. 7. Here, the operation process will be described using the stepped wave generator 128a connected to the first scan line S1 for convenience of description.

The square wave signal input from the first negative logic gate 124a is divided into a first period T10, a second period T11, and a third period T12. The first period T10 is the first half period of the square wave signal, the second period T11 is the middle half period of the square wave signal, and the third period T12 is the second half period of the square wave signal. Here, the second period T11 is set wider than the first period T10 and the third period T12.

The control signal Vt corresponding to the turn-on voltage is supplied during the first period T10 and the third period T12, and the control signal Vt corresponding to the turn-off voltage is supplied during the other periods. The third power source Vp is a pulse signal that falls from the predetermined potential to the reference voltage V2 when the control signal Vt corresponding to the turn-on voltage is supplied. The fourth power source VD is a direct current power source having a voltage value of the reference voltage V2.

In the first period T10, the control signal Vt corresponding to the turn-on voltage is input to the first and second switching elements T1 and T2. When the control signal Vt is input, the first and second switching elements T1 and T2 are turned on. When the first and second switching devices T1 and T2 are turned on, the potential of the first node N1 is increased from the absolute first voltage V1 to the reference voltage V2.

In the second period T11, the first and second switching elements T1 and T2 are turned off. When the first and second switching devices T1 and T2 are turned off, the potential of the first node N1 is lowered to the absolute first voltage V1.

In the third period T12, the first and second switching devices T1 and T2 are turned on to increase the potential of the first node N1 from the absolute first voltage V1 to the reference voltage V2. After the third period T12, the potential of the first node N1 is increased from the reference voltage V2 to the absolute second voltage V3.

In fact, in the present invention, the stepped wave generator 126a generates the stepped wave signal using the square wave signal while passing through the first to third periods T10 to T12. The stepped wave signal generated by the stepped wave generator 126a is supplied to the scan line S1 via the buffer 128a.

Meanwhile, in the exemplary embodiment of the present invention, the reference voltage V2 is set to an intermediate voltage value between the absolute first voltage V1 and the absolute third voltage V3. The reference voltage V2 may be set to a voltage of 0V.

As described above, when the selection signal SS is supplied in a stepped wave form, the kickback voltage proportional to the voltage difference between the selection signals SS may be reduced. In detail, the kickback voltage generated by the parasitic capacitors equivalently formed in the switching device SW is generated in proportion to the peak to peak voltage of the selection signal SS.

Here, in the exemplary embodiment of the present invention, since the selection signal SS is increased in the form of a step wave, the kickback voltage is generated in proportion to the voltage difference between the absolute first voltage V1 and the reference voltage V2. In other words, in the related art, the kickback voltage is generated in proportion to the voltage difference between the absolute first voltage V1 and the absolute second voltage V3. However, in the exemplary embodiment of the present invention, the absolute first voltage V1 and the reference voltage ( Since the voltage is generated in proportion to the voltage difference of V2), the kickback voltage can be reduced as compared with the conventional art.

On the other hand, the selection signal rising and falling in the form of a staircase wave is applicable to various types of pixels. For example, in the exemplary embodiment of the present invention, the present invention can be applied to the pixel 210 of the type shown in FIG. 8.

8 is a diagram illustrating a light emitting display device according to another embodiment of the present invention.

Referring to FIG. 8, a light emitting display device according to an exemplary embodiment of the present invention may include pixels 210 formed at intersections of scan lines S1 to Sn, data lines D1 to Dm, and emission control lines E1 to En. ), An image display unit 200 including (), a scan driver 220 for driving the scan lines S1 to Sn, and a data driver 230 for driving the data lines D1 to Dm.

The scan driver 220 generates a selection signal for driving the scan lines S1 to Sn in response to scan control signals from a controller (not shown), that is, a start pulse and a clock signal, to the scan lines S1 to Sn. Supply sequentially. In addition, the scan driver 220 generates emission control signals and sequentially supplies the emission control signals to the emission control lines E1 to En. Here, the scan driver 220 supplies a stepped wave signal that is sequentially raised and lowered by the selection signal SS supplied to the scan lines S1 to Sn, as shown in FIG. 9A. That is, the scan driver 220 includes a step wave generator block 126 as shown in FIG. 5. In addition, as illustrated in FIG. 9B, the scan driver 220 may supply not only the selection signal SS but also the emission control signal EMI as a step wave signal.

The data driver 230 supplies a data signal from the controller to the pixel 210 through the data lines D1 to Dm in response to data control signals supplied from the controller. In this case, the data driver 230 supplies data signals of one horizontal line to the data lines D1 to Dm every one horizontal period.

In this embodiment of the present invention, the scan driver 220 and / or the data driver 230 may be mounted in the form of a chip in a tape carrier package (TCP) electrically connected to the image display unit 200. Can be. Also, the scan driver 220 and / or the data driver 230 may be mounted in the form of a chip in a flexible printed circuit (FPC) or a film that is electrically connected to the image display unit 200. . On the other hand, the scan driver 220 and / or the data driver 230 may be directly mounted on the substrate of the image display unit 200 as well as formed directly on the substrate.

Each of the pixels 210 positioned in the intersection region of the scan lines S1 to Sn and the data lines D1 to Dm is selected when the selection signal SS is applied to the scan line S, and is selected from the data line D. Generates light corresponding to the supplied data signal.

To this end, each pixel 210 includes a pixel circuit 212 connected to a data line D, a scan line S, an emission control line E, and a first power source VDD, a pixel circuit 212, An organic light emitting diode OLED is connected between the second power sources VSS. The second power supply VSS connected to the cathode electrode of the organic light emitting diode OLED is set to a voltage lower than the first power supply VDD, for example, a ground voltage.

The organic light emitting diode OLED generates light corresponding to a current supplied from the pixel circuit 212. To this end, the organic light emitting diode OLED includes a light emitting layer, an electron transporting layer, and a hole transporting layer formed between the anode electrode and the cathode electrode. In addition, the organic light emitting diode OLED may further include an electron injection layer and a hole injection layer. In the organic light emitting diode OLED, when a voltage is applied between the anode electrode and the cathode electrode, electrons generated from the cathode electrode move to the light emitting layer through the electron injection layer and the electron transport layer, and holes generated from the anode electrode are transferred to the hole injection layer. And move toward the light emitting layer through the hole transport layer. Accordingly, in the light emitting layer, light is generated when the electrons and holes supplied from the electron transporting layer and the hole transporting layer collide and recombine.

The pixel circuit 212 includes a driving TFT DT connected between the first power supply VDD and the organic light emitting diode OLED, an nth (n is a natural number) emission control line En, and an organic light emitting diode OLED. And a fourth switching element SW4 connected to the driving TFT DT, a first switching element SW1 connected to the nth scan line Sn and a data line D, a first switching element SW1, The first node N1 between the second switching element SW2 connected to the first power source VDD and the n-1 th scan line Sn-1, and the driving TFT DT and the fourth switching element SW4. And a third switching device SW3 connected to the n-1 scan line Sn-1 and the gate electrode of the driving TFT DT, and a second node connected to the first and second switching devices SW1 and SW2. A storage capacitor Cst connected between the N2 and the first power supply VDD, and a compensation capacitor Cvth connected between the second node N2 and the driving TFT DT.

In FIG. 8, the driving TFT DT and the first to fourth switching devices SW1 to SW4 are illustrated as P-type metal oxide semiconductor field effect transistors (MOSFETs). It is not limited.

The gate electrode of the first switching element SW1 is connected to the nth scan line Sn, and the source electrode is connected to the data line D. The drain electrode of the first switching element SW1 is connected to the second node N2. The first switching device SW1 supplies the data signal from the data line D to the second node N2 in response to the selection signal supplied to the nth scan line Sn.

The gate electrode of the second switching element SW2 is connected to the n-th scan line Sn-1, and the source electrode is connected to the first power source VDD. The drain electrode of the second switching element SW2 is connected to the second node N2. The second switching device SW2 supplies the voltage from the first power supply VDD to the second node N2 in response to the selection signal supplied to the n-th scan line Sn-1.

The gate electrode of the third switching element SW3 is connected to the n-th scan line Sn-1, and the source electrode is connected to the driving TFT DT. The drain electrode of the third switching element SW3 is connected to the first node N1. The third switching device SW3 connects the gate electrode of the driving TFT DT to the first node N1 in response to the selection signal supplied to the n-1 th scan line Sn-1.

The storage capacitor Cst stores a voltage corresponding to the data signal supplied to the second node N2 when the selection signal is supplied to the nth scan line Sn, and maintains the stored voltage for one frame.

The compensation capacitor Cvth stores a voltage corresponding to the threshold voltage Vth of the driving TFT DT when the selection signal is supplied to the n−1 th scan line Sn−1. Here, the voltage stored in the compensation capacitor Cvth is used as a compensation voltage for compensating the threshold voltage Vth of the driving TFT DT.

The gate electrode of the driving TFT DT is connected to the source electrode of the third switching element SW3 and the compensation capacitor Cvth, and the source electrode is connected to the first power source VDD. The drain electrode of the driving TFT DT is connected to the fourth switching element SW4. The driving TFT DT adjusts the current supplied from the first power supply VDD to the first node N1 according to the voltage supplied to its gate electrode.

The gate electrode of the fourth switching element SW4 is connected to the emission control line En, and the source electrode is connected to the first node N1. The drain electrode of the fourth switching element SW4 is connected to the anode electrode of the organic light emitting element OLED. The fourth switching device SW4 controls the timing of supply of the current supplied from the driving TFT DT to the OLED in response to the emission control signal supplied to the emission control line En.

The operation of the pixel 100 will be described in detail with reference to FIG. 9A. In the following description, it will be assumed that n is '2'. First, a stepped wave select signal SS is supplied to the n-1 th scan line Sn-1 and a turn-off voltage Voff is supplied to the n th scan line Sn during the T1 period. The light emission control signal EMI is supplied to the nth light emission control line En during the T1 period. When the stepped wave select signal SS is supplied to the n-1 th scan line Sn-1, the second and third switching elements SW2 and SW3 are turned on. When the emission control signal EMI is supplied to the nth emission control line En, the fourth switching device SW4 is turned off.

When the second and third switching elements SW2 and SW3 are turned on in the T1 period, the driving TFT DT performs a diode function, and the gate-source voltage of the driving TFT DT is represented by its threshold voltage. Until Vth). Accordingly, a compensation voltage corresponding to the threshold voltage Vth of the driving TFT DT is stored in the compensation capacitor Cvth.

During the T2 period, a stepped wave select signal SS is supplied to the n-th scan line Sn-1 and a turn-off voltage Voff is supplied to the n-th scan line Sn. The emission control signal EMI is supplied to the nth emission control line En during the T2 period. When the stepped wave select signal SS is supplied to the nth scan line Sn, the first switching device SW1 is turned on. When the emission control signal EMI is supplied to the nth emission control line En, the fourth switching device SW4 is turned off.

When the first switching device SW1 is turned on during the T2 period, the data signal supplied to the data line D is supplied to the second node N2 via the first switching device SW1. When the data signal is supplied to the second node N2, the voltage corresponding to the data signal is charged in the storage capacitor Cst. Here, the gate electrode of the driving TFT DT is supplied with the voltage Vdata-VDD charged in the storage capacitor CSt and the compensation voltage stored in the compensation capacitor Cvth. Then, the driving TFT DT controls the current supplied from the first power source VDD to the fourth switching element SW4 in response to the voltage supplied to the gate electrode.

After the T2 period, the turn-on voltage Von is supplied to the emission control line E. Then, the fourth switching device SW4 is turned on so that the current supplied from the driving TFT DT is supplied to the organic light emitting diode OLED, thereby generating light corresponding to the current in the organic light emitting diode OLED. do.

In the present invention as described above, the kickback voltage may be reduced because the selection signal SS having a staircase wave is supplied to the scan lines S. FIG. In detail, the kickback voltage generated by parasitic capacitors equivalently formed in the switching elements SW is generated in proportion to the peak to peak voltage of the selection signal SS.

Since the selection signal SS is increased in the form of a staircase wave, the kickback voltage is generated in proportion to the voltage difference between the absolute first voltage V1 and the reference voltage V2. In other words, in the related art, the kickback voltage is generated in proportion to the voltage difference between the absolute first voltage V1 and the absolute second voltage V3. However, in the exemplary embodiment of the present invention, the absolute first voltage V1 and the reference voltage ( Since the voltage is generated in proportion to the voltage difference of V2), the kickback voltage can be reduced as compared with the conventional art. That is, in the embodiment of the present invention, the voltage variation of the second node N2 may be minimized, and thus the image quality may be improved. In addition, in the present invention, as shown in FIG. 9B, the emission control signal EMI may also be raised and lowered in the form of a stair wave, thereby minimizing the kickback voltage generated at the first node N1, thereby further improving image quality. .

The above detailed description and drawings are merely exemplary of the present invention, which are used only for the purpose of illustrating the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Accordingly, those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical protection scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

As described above, according to the light emitting display device and the driving method thereof according to the exemplary embodiment of the present invention, the kickback voltage of the pixel can be minimized by supplying the selection signal and / or the light emission control signal as the stair wave signal, thereby improving image quality. Can be improved.

1 is a circuit diagram illustrating a pixel of a conventional light emitting display device.

FIG. 2 is a waveform diagram for driving the pixel circuit shown in FIG.

3 is a view showing a light emitting display device according to an embodiment of the present invention;

FIG. 4 is a waveform diagram illustrating a selection signal supplied from the scan driver shown in FIG. 3.

FIG. 5 is a view showing details of the scan driver shown in FIG. 3; FIG.

FIG. 6 is a circuit diagram illustrating a stepped wave generator shown in FIG. 5. FIG.

7 is a waveform diagram illustrating a process of generating a stair wave signal in the stair wave generator shown in FIG. 6;

8 illustrates a light emitting display device according to another embodiment of the present invention.

9A and 9B are waveform diagrams showing driving waveforms supplied from the scan driver shown in FIG.

<Explanation of symbols for the main parts of the drawings>

10,110,210: Pixel 12,212: Pixel Circuit

100: image display unit 120,220: scan driver

130,230: data driver 122: shift register block

122a, 122b, 122c, 122n: Shift register

124: negative logical gate block

124a, 124b, 124c, 124n: negative logical gate

126: step wave generator block 126a, 126b, 126c, 126n: step wave generator

128: buffer block 128a, 128b, 128c, 128d: buffer

Claims (19)

Scan lines, Data lines formed in a direction crossing the scan lines; A pixel positioned at an intersection of the scan lines and the data lines; And a scan driver for sequentially supplying a stepped wave selection signal to the scan lines so that the pixel can be selected. The method of claim 1, The scan driver Shift registers for generating an output signal sequentially shifted according to a clock signal; Negative AND gates (NAND) for generating a square wave signal by performing a logical operation on the output signal and an enable signal supplied from the outside; And a stepped wave generator connected to each of the negative AND gates and configured to generate a stepped wave signal using the square wave signal. The method of claim 1, Each pixel is A switching device turned on by the selection signal; A driving transistor for supplying a current corresponding to the data signal to the light emitting device when the switching device is turned on; And a storage capacitor configured to store a voltage corresponding to the data signal. The method of claim 1, Each pixel is A driving transistor for supplying a current corresponding to the data signal to the light emitting device; A first switching unit controlled by a first selection signal and including a compensation capacitor for compensating the threshold voltage of the driving transistor; A storage capacitor storing a voltage corresponding to the data signal; A second switching unit transferring the data signal to the storage capacitor in response to a second selection signal; And a switching element controlled by a light emission signal supplied to a light emission control line formed in parallel with the scan line and controlling a supply timing of a current supplied from the driving transistor to the light emitting element. The method of claim 4, wherein And the scan driver is configured to supply the light emission signal in a stepped wave shape. Shift registers for generating an output signal sequentially shifted according to a clock signal; Negative AND gates (NAND) for generating a square wave signal by performing a logical operation on the output signal and an enable signal supplied from the outside; And a stepped wave generator connected to each of the negative AND gates and configured to generate a stepped wave signal using the square wave signal. The method of claim 6, Each of the step wave generators A first switching element having a source electrode connected to a third power supply, a drain terminal connected to a first node which is an output terminal of the negative AND gate, and a gate terminal connected to a control signal input terminal; And a second switching element having a source electrode connected to a fourth power supply, a drain terminal connected to the first node, and a gate terminal connected to the control signal input terminal. The method of claim 7, wherein The square wave signal is a signal which is lowered from the absolute second voltage to the absolute first voltage to maintain the absolute first voltage for a first period, and rises to the absolute second voltage after the first period. Drive part. The method of claim 8, And the first and second switching elements are turned on for at least part of a first period during which the square wave signal is supplied. The method of claim 9, And the first and second switching elements are turned on for a second period including a time point at which the square wave signal falls and a third period including a time point at which the square wave signal rises. The method of claim 10, And the third power supply is a pulse signal that falls from a predetermined voltage to a reference voltage which is an intermediate voltage between the absolute first voltage and the absolute second voltage at a predetermined voltage during the second period and the third period. The method of claim 11, And the fourth power supply is a direct current voltage having a potential of the reference voltage. The method of claim 11, And the reference voltage is set to 0V. The method of claim 12, The first node is set to the voltage value of the reference voltage during the second period and the third period, and the potential of the first node during the remaining period of the first period except the first period and the third period is A scan driver which is set to the voltage value of the absolute first voltage. The method of claim 7, wherein And a buffer connected to the first node of each of the stepped wave generators to supply the stepped wave signal to the scan lines. A first step of sequentially supplying a selection signal so that a pixel can be selected; And supplying a data signal to the pixels selected by the selection signal. And the selection signal is supplied in the form of a staircase wave. The method of claim 16, And the selection signal rises and falls in the stepped wave shape. The method of claim 16, And supplying an emission control signal to control the timing of light generation from the pixel. The method of claim 18, And the light emission control signal is provided in a stepped wave shape.