KR20060053507A - Thin film transistor array panel and method of manufacturing the same - Google Patents

Abstract

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, comprising: arranging an island-like semiconductor film including a plurality of nano bars including a linear semiconductor made of single crystal silicon and an insulator surrounding the semiconductor, on the insulating substrate; Forming a gate electrode overlapping with the gate electrode; implanting impurities into the semiconductor at a high concentration using the gate electrode as an ion implantation mask to form source and drain regions on both sides of the gate electrode; and covering the gate electrode and the semiconductor film. Forming an interlayer insulating film, and etching the interlayer insulating film and the insulator to form source and drain electrodes connected to the source and drain regions, respectively.

Thin Film Transistor, Nano, Monocrystalline, Complementary

Description

Method for manufacturing thin film transistor array panel and thin film transistor array panel {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME}

1A is a block diagram of a display device according to an exemplary embodiment of the present invention.

1B is an equivalent circuit diagram of one pixel of a liquid crystal display, which is an example of a display device according to an exemplary embodiment of the present invention.

2A is a layout view illustrating a pixel portion of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2B is a plan view specifically illustrating a semiconductor film of a thin film transistor in the thin film transistor array panel of FIG. 2A.

FIG. 3 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 2A taken along the line III-III ′.

4 is a layout view schematically illustrating a complementary thin film transistor positioned in a driving unit of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor illustrated in FIG. 4 taken along the line VV ′.

6A and 6B are layout views in an intermediate step of manufacturing the thin film transistor array panel shown in FIGS. 2 to 5 according to the embodiment of the present invention.

6C is a cross-sectional view taken along lines VIc-VIc 'and VIc'-VIc ″ of FIGS. 6A and 6B, respectively.

7A and 7B are layout views of a thin film transistor array panel in the next step of FIGS. 6A and 6B, respectively.

FIG. 7C is a cross-sectional view taken along the lines VIIc-VIIc ′ and VIIc′-VIIc ″ of FIGS. 7A and 7B, respectively.

FIG. 8 is a cross-sectional view taken along line VIIb-VIIc 'and VIIc'-VIIc "of FIGS. 7A and 7B as a cross-sectional view of the thin film transistor array panel in the next step of FIG. 7C.

9A and 9B are layout views at the next stage of FIG. 8.

9C is a cross-sectional view taken along the lines IXc-IXc 'and IXc'-IXc "of FIGS. 9A and 9B, respectively.

10A and 10B are layout views at the next stage of FIGS. 9A and 9B.

10C is a cross-sectional view taken along the lines Xc-Xc 'and Xc'-Xc "of FIGS. 10A and 10B, respectively.

11A and 11B are layout views at the next stage of FIGS. 10A and 10B.

FIG. 11C is a cross-sectional view taken along the lines XIc-XIc 'and XIc'-XIc "of FIGS. 11A and 11B, respectively.

12A and 12B are layout views at the next stage of FIGS. 11A and 11B.

12C is a cross-sectional view taken along the lines XIIc-XIIc 'and XIIc'-XIIc "of FIGS. 12A and 12B, respectively.

※ Explanation of symbols on main parts of drawing ※                 

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

137: sustain electrode 140: gate insulating film

153: source region 154: channel region

155: drain region 171: data line

173 Source electrode 175 Drain electrode

190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel, a method for manufacturing the same, and a method for manufacturing a thin film transistor array panel using the same, and more particularly, to a method for manufacturing a polycrystalline silicon thin film transistor.

In general, a thin film transistor (TFT) is used as a switching element for driving each pixel independently in a flat panel display device such as a liquid crystal display or an organic electroluminescent emitting display. The thin film transistor array panel including the thin film transistor includes a scan signal line (or gate line) for transmitting a scan signal to the thin film transistor and a data line for transmitting a data signal, in addition to the thin film transistor and the pixel electrode connected thereto.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode connected to the pixel electrode, and a semiconductor positioned on the gate electrode between the source electrode and the drain electrode. The data signal from the data line is transferred to the pixel electrode in accordance with the scan signal from the. In this case, the semiconductor of the thin film transistor is made of crystalline silicon (crystallized-silicon) or amorphous silicon (amorphous silicon).

In general, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and thus is mainly used in display devices using glass having a low melting point as a substrate. However, due to the low field effect mobility, amorphous silicon requires application of crystalline silicon having high field effect mobility, high frequency operating characteristics, and electrical characteristics of low leakage current. It is preferable to form a chip in glass by forming a driving integrated circuit together with the thin film transistor on the substrate.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same, which may improve driving ability of a thin film transistor.

In the thin film transistor array panel and the method for manufacturing the same according to the present invention for achieving the above object, a plurality of linear semiconductors of nano-rods including single crystal silicon are arranged and used as a semiconductor of the thin film transistor.

More specifically, the thin film transistor array panel according to the exemplary embodiment of the present invention may be formed of a single crystal silicon, and may include a linear region including a channel region and a source region and a drain region disposed at both sides of the channel region and heavily doped with impurities. An island-like semiconductor film in which a plurality of nanorods including a semiconductor of the semiconductor and an insulator surrounding the semiconductor are arranged in parallel with each other, a gate electrode overlapping and crossing the linear semiconductor on the insulator, and covering the gate electrode, An interlayer insulating film having first and second contact holes exposing the source region and the drain region together with the insulator, and formed on the interlayer insulating film, wherein the source and drain regions are formed through the first and second contact holes. And source and drain electrodes that are respectively connected to It is.

The display device may further include a gate line connected to the gate electrode, a data line crossing the gate line, a data line connected to the source electrode, and a pixel electrode connected to the drain electrode.

The thin film transistor array panel is preferably used for a liquid crystal display or an organic light emitting display.

Preferably, the source region and the drain region are doped with an N-type or P-type impurity, and the island-type semiconductor film may include the first and the source regions and the drain region doped with N-type and P-type impurities. A second linear semiconductor, said gate electrode comprising first and second control electrodes, said source electrode comprising first and second input electrodes, and said drain electrode having first and second output electrodes It may include. The second input electrode and the first control electrode may be connected to each other.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, comprising: disposing an island-like semiconductor film including a plurality of nano bars including a linear semiconductor made of single crystal silicon and an insulator surrounding the semiconductor, on an insulating substrate; Forming a gate electrode overlapping the semiconductor on the insulator, and implanting impurities into the semiconductor at a high concentration using the gate electrode as an ion implantation mask to form source and drain regions on both sides of the gate electrode Forming an interlayer insulating layer covering the gate electrode and the semiconductor layer; etching the interlayer insulating layer and the insulator to form source and drain electrodes connected to the source and drain regions, respectively. .

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

A thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1A and 1B.

FIG. 1A is a block diagram of a display device according to an exemplary embodiment of the present invention, and FIG. 1B is an equivalent circuit diagram of one pixel of a liquid crystal display, which is an example of the display device according to an exemplary embodiment.

As shown in FIG. 1A, a display device according to an exemplary embodiment of the present invention includes a display panel unit 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. And a connected gray level signal generator 800 and a signal controller 600 for controlling the gray level signal generator 800.

Referring to FIG. 1A, the display panel unit 300 is connected to a plurality of display panel lines G1-after, D1-Dm when viewed in an equivalent circuit, arranged in a substantially matrix form, and the display area. and a plurality of pixels PX constituting a display area DA. Referring to FIG. 1B, the display panel 300 of the liquid crystal display includes lower and upper display panels 100 and 200 and a liquid crystal layer 3 therebetween. In the case of an organic light emitting display, the display panel 300 may include only one display panel.                     

The display signal lines G ₁ -G _n and D ₁ -D _m transmit a data signal and a plurality of gate lines G ₁ -G _n that transmit a gate signal (also called a “scan signal”). It includes a data line (D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes at least one switching element (not shown) such as a thin film transistor and at least one capacitor (not shown).

Referring to FIG. 1B, each pixel PX of the liquid crystal display includes a switching element Q connected to the display signal lines G ₁ -G _n and D ₁ -D _m and a liquid crystal capacitor C connected thereto. _LC ) and a storage capacitor (C _ST ). The display signal lines G ₁ -G _n and D ₁ -D _m are disposed on the lower display panel 100, and the storage capacitor C _ST may be omitted as necessary.

The switching element Q, such as a crystalline silicon thin film transistor, is provided in the lower panel 100 and is connected to a control terminal and a data line D ₁ -D _m connected to the gate lines G ₁ -G _n , respectively. It is a three-terminal device that has an input terminal and an output terminal connected to a liquid crystal capacitor (C _LC ) and a storage capacitor (C _ST ).

The liquid crystal capacitor C _LC has two terminals, the pixel electrode 190 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 190 and 270. It functions as a dielectric. The pixel electrode 190 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 1B, the common electrode 270 may be provided in the lower panel 100. In this case, both electrodes 190 and 270 may be formed in a linear or bar shape.

The storage capacitor C _ST is a capacitor that assists the liquid crystal capacitor C _LC . A separate signal line (not shown) and a pixel electrode 190 of the lower panel 100 overlap each other, and the separate signal line is provided. A predetermined voltage such as the common voltage Vcom is applied to the. However, the storage capacitor C _ST may be formed such that the pixel electrode 190 overlaps the front end gate line directly above the insulator.

In order to implement color display, each pixel PX uniquely displays one of a plurality of primary colors (spatial division) or alternately displays a plurality of primary colors (time division) so that the spatial and temporal sum of the primary colors can be achieved. Indicates the desired color. Examples of primary colors include red, green and blue. FIG. 1B illustrates an example of spatial division in which each pixel PX includes a color filter 230 representing one color of primary colors in a corresponding region of the upper panel 200 facing the pixel electrode 190. . Alternatively, the color filter 230 may be formed above or below the pixel electrode 190 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the two display panels 100 and 200 of the display panel unit 300.                     

Each pixel PX of the organic light emitting display device includes a switching transistor (not shown) connected to the display signal lines G ₁ -G _n and D ₁ -D _m , and a driving transistor connected thereto (not shown). And a storage capacitor (not shown), and a light emitting diode (not shown). The light emitting diode includes a pixel electrode (not shown), a common electrode (not shown), and a light emitting member (not shown) therebetween.

Referring back to FIG. 1A, the gray signal generator 800 generates a plurality of gray signals related to the transmittance of the pixel PX. The gray level signal generator 800 for the liquid crystal display generates two gray level voltages each having a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 is connected to the gate lines G ₁ -G _n of the display panel 300 to receive a gate signal having two values equal to the gate on voltage Von and the gate off voltage Voff, respectively. G ₁ -G _n ). The gate driver 400 is integrated in the display panel 300 and includes a plurality of driving circuits (not shown). Each driving circuit constituting the gate driver 400 is connected to one gate line G ₁ -G _n and includes a plurality of N-type, P-type, and complementary thin film transistors. However, the gate driver 400 may be mounted on the display panel 300 in the form of an integrated circuit (IC) chip or on a flexible printed circuit (FPC) film. In the latter case, a flexible printed circuit film is attached onto the display panel unit 300.

The data driver 500 is connected to the data lines D ₁ -D _m of the display panel 300 and selects a gray voltage from the gray signal generator 800 to select the gray voltage as the data voltage D ₁ -D _m. ) Is applied. The data driver 500 may also be a flexible printed circuit (FPC) integrated into the display panel unit 300, mounted on the display panel unit 300 in the form of one or more integrated circuit chips, or attached to the display panel unit 300. ) Can be mounted on the film.

The driving units 400 and 500 or the flexible printed circuit film on which they are mounted are positioned in a peripheral area positioned outside the display area DA in the display panel 300.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like, and may be mounted on a printed circuit board (PCB).

Next, an example of the lower panel for the liquid crystal display device, that is, the thin film transistor array panel illustrated in FIGS. 1A and 1B will be described in detail with reference to FIGS. 2A to 5. Here, it is assumed that the thin film transistor of the pixel PX is an N type and the thin film transistor of the gate driver 400 or the data driver 500 is a complementary type including a P type and an N type.

FIG. 2A is a layout view illustrating a pixel portion of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2B is an enlarged plan view illustrating a semiconductor part of the thin film transistor in the thin film transistor array panel of FIG. 2A, and FIG. 3 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 2A taken along the line III-III ′. 4 is a layout view schematically illustrating a thin film transistor for a gate driver of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line V-V ′ of the thin film transistor illustrated in FIG. 4.

A blocking film 111 made of silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is formed on the transparent insulating substrate 110. The blocking film 111 may have a multilayer structure.

On the blocking film 111, a plurality of nanorods including linear semiconductors 151a, 151b and 151c made of single crystal silicon and insulators 141a, 141b and 141c surrounding the linear semiconductors 151a, 151b and 151c. Island-like semiconductor films 150a, 150b, 150c including wires are formed. FIG. 2B illustrates only the semiconductor film 150a of the pixel portion disposed in the thin film transistor in detail. The semiconductor film 150a includes a plurality of semiconductors 151a parallel to each other and an insulator 141a surrounding the semiconductor 151a. ) And a plurality of nano bars including (), and the semiconductor films 150b and 150c of the driving unit have the same structure.

The linear semiconductors 151a, 151b, and 151c of the semiconductor films 150a, 150b, and 150c each include an impurity region containing conductive impurities and an intrinsic region containing little conductive impurities. The impurity region includes a heavily doped region having a high impurity concentration and a lightly doped region having a low impurity concentration.

The intrinsic region of the pixel portion linear semiconductor 151a includes a channel region 154a and a storage region 157, and the high concentration impurity regions are separated from each other about the channel region 154a. A source region 153a, a drain region 155a, and other regions 158, wherein the low concentration impurity regions 152, 156 are formed of intrinsic regions 154a, 157 and high concentration impurity regions ( 153a, 155a, and 158, the width of which is narrow. In particular, the low concentration impurity region 152 located between the source region 153a and the channel region 154a and between the drain region 155a and the channel region 154a is referred to as a lightly doped drain region (LDD region). do.

Intrinsic regions of each of the driver linear semiconductors 151b and 151c include channel regions 154b and 154c, respectively, and high concentration impurity regions include source regions 153b and 153c and drain regions 155b and 155c. Here, one of the driver linear semiconductors 151b is a semiconductor of the N-type thin film transistor and is a low concentration impurity region disposed between the source region 153b and the channel region 154b and between the drain region 155b and the channel region 154b. 152, and the other 151c is a semiconductor of the P-type thin film transistor.

Examples of the conductive impurity include P-type impurities such as boron (B) and gallium (Ga) and N-type impurities such as phosphorus (P) and arsenic (As). The lightly doped regions 152 and 156 may prevent leakage current or punch through from occurring in the thin film transistor and may be replaced with an offset region free of impurities.                     

A plurality of gate lines 121, a plurality of storage electrode lines 131, and a plurality of first lines extending in a horizontal direction are disposed on the island-like semiconductor films 150a, 150b, 150c and the blocking film 111. And second control electrodes 124b and 124c are formed.

The gate line 121 transmits a gate signal and includes a gate electrode 124a that protrudes downward and overlaps the channel region 154a of the pixel portion linear semiconductor 151a. The gate electrode 124a may also overlap the lightly doped region 152. One end of the gate line 121 is directly connected to the gate driving circuit.

The first and second control electrodes 124b and 124c overlap the channel regions 154b and 154c of the driver semiconductors 151b and 151c and are connected to other signal lines (not shown) to which a control signal is applied.

The storage electrode line 131 receives a predetermined voltage such as a common voltage applied to a common electrode (not shown), and extends up and down to overlap the storage region 157 of the semiconductor 151a. 137).

The insulators 141a, 141b, and 141c of the island-like semiconductor films 150a, 150b, and 150c overlapping the gate electrode 124a and the first and second control electrodes 124b and 124c are gate insulating films of the thin film transistor.

The gate line 121, the sustain electrode line 131, and the first and second control electrodes 124b and 124c may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, It may be made of copper-based metals such as copper (Cu) or copper alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), titanium (Ti), and tungsten (W). . However, the gate line 121, the storage electrode line 131, and the first and second control electrodes 124b and 124c may have a multilayer structure including two conductive films (not shown) having different physical properties. One of these conductive films is a metal having a low resistivity, for example, to reduce signal delay or voltage drop of the gate line 121, the storage electrode line 131, and the first and second control electrodes 124b and 124c. For example, it may be made of an aluminum-based metal, a silver-based metal, or a copper-based metal. The other conductive layer may be formed of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, throm, tantalum, or titanium. A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

Side surfaces of the gate line 121, the storage electrode line 131, and the first and second control electrodes 124b are inclined with respect to the surface of the substrate 110 so that the upper thin film can be smoothly connected.

An interlayer insulating film 160 is formed on the gate line 121, the storage electrode line 131, the first and second control electrodes 124b, and the island-like semiconductor films 150a, 150b, and 150c. . The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and photosensitivity, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by plasma chemical vapor deposition, or It may be formed of an inorganic material such as silicon nitride.

The insulators 141a, 141b, and 141c of the interlayer insulating layer 160 and the island-like semiconductor films 150a, 150b, and 150c respectively expose the source regions 153a, 153b, and 153c and the drain regions 155a, 155b, and 155c, respectively. Contact holes 163, 166, 165, 167, 168, and 169 are formed.

The data line 171, the plurality of drain electrodes 175a, the plurality of first and second input electrodes 173b and 173c, and the plurality of first and second data lines 171 are disposed on the interlayer insulating layer 160. Second output electrodes 175b and 175c are formed.

The data line 171 transmitting the data signal mainly includes a source electrode 173a extending in the vertical direction to intersect the gate line 121 and connected to the source region 153a through the contact hole 163. One end of the data line 171 may have a large area in order to connect to another layer or an external driving circuit. Line 171 may be directly connected to the data driving circuit.

The drain electrode 175a is separated from the source electrode 173a and is connected to the drain region 155a through the contact hole 165. The drain electrode 175a may extend to the storage region 157.

The first and second input electrodes 173b and 173c and the first and second output electrodes 175b and 175c are separated from each other with respect to the control electrode 124b and through the contact holes 166, 167, 168 and 169. The driving units may be connected to the source regions 153b and 153c and the drain regions 155b and 155c of the linear semiconductors 151b and 151c and may be connected to other signal lines (not shown). In the complementary thin film transistor, the first output electrode 175b of the N-type thin film transistor and the second input electrode 173c of the P-type thin film transistor are connected to each other.                     

The data line 171, the drain electrode 175a, the first and second input electrodes 173b and 173c, and the first and second output electrodes 175b and 175c may be formed of a refractory metal such as molybdenum, chromium, tantalum, or titanium. refratory metal) or an alloy thereof. However, they may also have a multilayer structure including a conductive film having a low resistance and a conductive film having good contact characteristics, such as the gate line 121. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Sides of the data line 171, the drain electrode 175a, the first and second input electrodes 173b and 173c, and the first and second output electrodes 175b and 175c are also inclined with respect to the surface of the substrate 110. desirable.

A passivation layer on the data line 171, the drain electrode 175a, the first and second input electrodes 173b and 173c, and the first and second output electrodes 175b and 175c and the interlayer insulating layer 160 ( 180 is formed. The passivation layer 180 may be made of the same material as the interlayer insulating layer 160 and may have a plurality of contact holes 185 exposing the drain electrode 175a. The passivation layer 180 may be omitted in the driver.

A pixel electrode 190 made of a transparent conductive material such as indium zinc oxide (IZO) or indium tin oxide (ITO) or an opaque reflective conductive material such as aluminum or silver is formed on the passivation layer 180.

The pixel electrode 190 is connected to the drain electrode 175a connected to the drain region 155a through the contact hole 185 to receive a data voltage from the drain region 155a and the drain electrode 175a.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 to which the common voltage is applied to determine the direction of the liquid crystal molecules of the liquid crystal layer 3 between the two electrodes 190 and 270, or An electric current is made to flow through a light emitting layer (not shown) between electrodes, and light is emitted.

Referring to FIG. 1B, the pixel electrode 190 and the common electrode 270 form a liquid crystal capacitor C _LC to maintain an applied voltage even after the thin film transistor Q is turned off, and the storage capacitor C _ST is a pixel. A portion of the electrode 190 and the drain electrode 175a and the storage electrode line 131 including the storage region 157 and the storage electrode 137 are made to overlap.

When the passivation layer 180 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may be overlapped with the data line 171 and the gate line 121 to improve the aperture ratio.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1A through 5 will be described in detail with reference to FIGS. 1A through 5 in addition to FIGS. 6A through 12C.

6A and 6B are layout views at an intermediate stage of manufacturing the thin film transistor array panel shown in FIGS. 2 to 5 according to an embodiment of the present invention, and FIG. 6C is VIc-VIc ′ and VIc of FIGS. 6A and 6B, respectively. 7A and 7B are layout views of the thin film transistor array panel in the next steps of FIGS. 6A and 6B, respectively, and FIG. 7C is VIIc-VIIc of FIGS. 7A and 7B, respectively. 8 is a cross-sectional view taken along the line VIIc'-VIIc ", and FIG. 8 is a cross-sectional view taken along the lines VIIc-VIIc 'and VIIc'-VIIc" of FIGS. 7A and 7B as a cross-sectional view of the thin film transistor array panel in the next step of FIG. 7C. 9A and 9B are layout views in the next step of FIG. 8, FIG. 9C is a cross-sectional view taken along the lines IXc-IXc ′ and IXc′-IXc ″ of FIGS. 9A and 9B, respectively. FIGS. 10A and 10B 9A and 9B are layout views of the next step, and FIG. 10C is cut along the lines Xc-Xc ', Xc'-Xc "of FIGS. 10A and 10B, respectively. 11A and 11B are layout views at the next stage of FIGS. 10A and 10B, and FIG. 11C is a cross-sectional view taken along lines XIc-XIc ′ and XIc′-XIc ″ of FIGS. 11A and 11B, respectively. 12A and 12B are layout views at the next stage of FIGS. 11A and 11B, and FIG. 12C is a cross-sectional view taken along the lines XIIc-XIIc 'and XIIc'-XIIc "in FIGS. 12A and 12B, respectively. And "B" represent the pixel portion and the driver portion.

First, as shown in FIGS. 6A to 6C, the blocking film 111 is formed on the transparent insulating substrate 110, and then arranged in parallel with each other, and the linear semiconductors 151a, 151b, and 151c are formed of single crystal silicon. The island-like semiconductor films 150a, 150b, and 150c including a plurality of nanowires including the insulators 141a, 141b, and 141c surrounding the linear semiconductors 151a, 151b, and 151c are disposed.

Subsequently, as shown in FIGS. 7A to 7B, the gate metal layer is stacked on the blocking layer 111 by sputtering, and then patterned by a photolithography process using a mask to form an N-type thin film of the pixel portion A and the driving portion B. The metal member 125 and the second control electrode 124c covering the island-like semiconductor film 150b of the transistor are formed.

The P-type impurity ions are implanted at a high concentration using the second control electrode 124c as a mask to form the P-type source region 153c and the drain region 155c in the linear semiconductor 150c.

Subsequently, a mask metal film is successively stacked on the substrate 110 on which the metal member 125 and the second control electrode 124c are formed. The mask metal film is formed of a gate metal film and a metal having a high etching selectivity, and is formed of a high heat resistant and high chemical material. For example, when the gate metal film is formed of aluminum, the mask metal film may be formed of chromium.

Next, as shown in FIGS. 8A to 8B, the mask metal layer and the metal member 125 are patterned by a photolithography process using a mask to form the mask metal member 121 ′ in the pixel portion A and the driving portion B. FIG. , 131 ′, 124b ′ and a plurality of gate lines 121 disposed below and including the gate electrode 124a, a plurality of storage electrode lines 131 including the storage electrode 137, and a first control electrode ( 124b). At this time, the metal member 135 covering the second control electrode 124c and the island-like semiconductor film 150c of the driving unit B is also formed.

At this time, if the etching time is sufficiently long so that the metal member 125 is overetched than the mask metal members 121 ', 131', and 124b ', the gate line 121, the gate electrode 124a, and the storage electrode 137 are formed. And the width of the storage electrode line 131 is narrower than that of the mask metal members 121 ', 131', and 124b '.

Subsequently, when N-type impurity ions are implanted at a high concentration using the photosensitive film or mask metal members 121 ', 131', and 124b 'as ion implantation masks, the semiconductors 151a and 151b of the pixel portion A and the driving portion B are formed. A plurality of high concentration impurity regions including N-type source regions 153a and 153b, drain regions 155a and 155b, and other regions 158 are formed in the substrate. Ion implantation can be performed after removing a photosensitive film.

Next, as shown in FIGS. 9A and 9B, the photoresist film and the mask metal members 121 ′, 131 ′, and 124 b ′ are removed, and then the gate electrodes 124 a and the first electrodes of the pixel portion A and the driver B are removed. N-type impurity ions are lightly doped into the linear semiconductors 151a and 151b using the control electrode 124b as an ion implantation mask to form a plurality of low concentration impurity regions 152 and 156. In this way, the areas under the gate electrode 124a and the first control electrode 124b respectively positioned between the source regions 153a and 153b and the drain regions 155a and 155b become the channel regions 154a and 154b. The area under the electrode line 131 becomes the holding area 157.

The low concentration impurity regions 152 and 156 may be disposed on sidewalls of the gate line 121, the storage electrode line 131, and the first control electrode 124b in addition to the mask metal members 121 ′, 131 ′, and 124b ′ described above. It can be formed by creating a spacer or the like.

10A through 10C, the interlayer insulating layer 160 is stacked on the entire surface of the substrate 110, and the photo is etched together with the insulators 141a, 141b, and 141c of the island-like semiconductors 150a, 150b, and 150c. And a plurality of contact holes 163, 165, 166, 167, 168, and 169 exposing the drain regions 153a, 155a, 153b, 155b, 153c, and 155c, respectively.

Next, as shown in FIGS. 11A and 11B, a metal film for data is stacked and patterned on the interlayer insulating layer 160 and connected to the source region 153a and the drain region 155a through the contact holes 163 and 165, respectively. A plurality of data lines 171 and a plurality of drain electrodes 175a having a source electrode 173a are formed and connected to the source region 153b and the drain region 155b through the contact holes 166 and 167, respectively. The first input electrode 173b and the first output electrode 175b, and the second input electrode 173c connected to the source region 153c and the drain region 155c through the contact holes 168 and 169, respectively. ) And the second output electrode 175c.

12A to 12C, the passivation layer 180 is stacked and photo-etched to form a plurality of contact holes 185 exposing the drain electrode 175a of the pixel portion A. Referring to FIG.

2A and 3, the plurality of pixel electrodes 190 connected to the drain electrode 175a through the contact hole 185 using a transparent conductive material such as IZO, ITO, or the like on the passivation layer 180. Form.

The method of manufacturing the thin film transistor array panel according to the present exemplary embodiment may be similarly applied to a process of manufacturing an organic light emitting display device by adding a process of forming an organic light emitting layer afterwards, in which case the arrangement of the thin film transistors in the pixel unit or the driving unit is performed. The structure can be changed.

As described above, the driving capability of the thin film transistor can be improved by implementing the thin film transistor using the nano bar, and through this, the thin film transistor as well as the thin film transistor of the driving part can be formed. It can be formed directly on top. In addition, the photolithography process and the crystallization process may be omitted when forming the semiconductor, thereby simplifying the manufacturing process and minimizing the manufacturing cost.                     

Although the above has been described in detail with respect to preferred embodiments of the present invention, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

Claims (8)

A nanorod comprising a single crystal silicon, a linear semiconductor including a source region and a drain region disposed in both the channel region and the channel region and heavily doped with impurities, and a nanorod including an insulator surrounding the semiconductor. Island-like semiconductor films arranged in parallel in large numbers, A gate electrode overlapping and crossing the linear semiconductor on the insulator, An interlayer insulating film covering the gate electrode and having first and second contact holes to expose the source region and the drain region together with the insulator; A source electrode and a drain electrode formed on the interlayer insulating layer and connected to the source region and the drain region through the first and second contact holes, respectively. Thin film transistor array panel comprising a. In claim 1, A gate line connected to the gate electrode, A data line crossing the gate line and connected to the source electrode; A pixel electrode connected to the drain electrode Thin film transistor display panel further comprising. In claim 2, The thin film transistor array panel is used for a liquid crystal display device or an organic light emitting display device. In claim 1, And the source region and the drain region are doped with an N-type or P-type impurity. In claim 1, The island-like semiconductor film includes first and second linear semiconductors in which the source region and the drain region are doped with N-type and P-type impurities, and the gate electrode includes first and second control electrodes. And the source electrode includes first and second input electrodes, and the drain electrode includes first and second output electrodes. In claim 5, The thin film transistor array panel is connected to the second input electrode and the first control electrode. Arranging an island-like semiconductor film including a plurality of nanorods including a linear semiconductor made of single crystal silicon and an insulator surrounding the semiconductor, on an insulating substrate; Forming a gate electrode overlapping the semiconductor on the insulator, Implanting impurities into the semiconductor at a high concentration using the gate electrode as an ion implantation mask to form source and drain regions on both sides of the gate electrode; Forming an interlayer insulating film covering the gate electrode and the semiconductor film; Etching the interlayer insulating layer and the insulator to form a source electrode and a drain electrode respectively connected to the source region and the drain region; Method of manufacturing a thin film transistor array panel comprising a. In claim 7, Forming a gate line connected to the gate electrode; Forming a data line connected to the source electrode; Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array panel further comprising.

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