KR20070003254A - Schottky-barrier transistor fabrication using tensile silicon technology. - Google Patents

Abstract

The present invention relates to a method for fabricating a field effect transistor, and more particularly, to a method for fabricating a field effect transistor having a Schottky-barrier source and a drain applied to a transistor using a metal silicide in a source / drain region. .

A method of fabricating a Schottky-barrier transistor using a tensile silicon technology according to the present invention is a method of manufacturing a Schottky barrier transistor semiconductor, wherein an insulating spacer is formed on a silicon germanium strain semiconductor substrate on a side surface of a gate insulating film, a gate electrode, and a gate electrode. Forming a source / drain region by implanting impurities into the semiconductor substrate using the ion implantation mask using the gate pattern and the spacer; Depositing a metal film on the entire surface of the substrate; Heat treating the entire surface of the substrate to form metal silicide; And forming a silicide and selectively removing the remaining metal film.

Description

Schottky-barrier transistor fabrication using tensile silicon technology. {METHOD FOR MANUFACTURING SCHOTKKY--BARRIER TRANSISTOR WITH THE STRAINED SILICON TECHNOLOGY}

FIG. 1 illustrates a fabrication procedure of a Schottky-barrier transistor using a tensile silicon technology to include a silicide gate and a source / drain on a silicon germanium modified semiconductor substrate according to an embodiment of the present invention.

FIG. 2 illustrates a fabrication process of a Schottky-barrier transistor using a tensile silicon technique for depositing a silicon nitride capping layer on a front surface of a transistor substrate including a silicide gate and a source / drain according to another embodiment of the present invention. will be.

FIG. 3 illustrates a fabrication procedure of a Schottky-barrier transistor using a tensile silicon technique for selectively epitaxially growing a source / drain region with silicon germanium according to another embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

1: embedded silicon layer 2: gate insulating film

3: gate 4: spacer

5: source 6: drain

7: metal layer 8: silicide gate

9: silicide source 10: silicide drain

11: silicon nitride capping layer

The present invention relates to a field effect transistor fabrication method and structure thereof, and more particularly to a field effect transistor fabrication method having a Schottky-barrier source and drain, and a field effect transistor fabricated by the fabrication method.

At present, in order to lower the price and increase the performance of semiconductor devices, the size of semiconductor devices has been continuously reduced in accordance with Moore's Law to enable high integration of semiconductor ICs.

However, as the channel length of the device shrinks below 100 nm, the electrical resistance of the gate electrode increases due to the narrow width of the gate electrode.

As a result, the transmission speed of the electrical signal applied to the gate electrode of the transistor becomes slow due to the RC delay time.

In addition, an increase in sheet resistance due to the shallow junction depth of the source / drain regions results in a decrease in the driving current of the transistor.

To solve this problem, a Schottky barrier transistor with Schottky barrier (metal) source / drain technology has been proposed.

However, the Schottky barrier (metal) transistor is difficult to reduce the Schottky junction resistance (junction resistance between the metal source / drain and the silicon channel) to increase the driving current of the transistor.

In order to solve this problem, a Schottky barrier (metal silicide) transistor in which metal silicide is applied to a source / drain is widely used.

For example, erbium silicide is used for N-type transistors and platinum silicide is used for P-type transistors.

Metal salicide technology selectively forms a metal silicide film in the gate and source / drain regions, thereby dramatically lowering the resistance of the gate and source / drain regions to meet the low power / high speed of future devices.

Schottky junction resistance in Schottky barrier transistors is known to be reduced by controlling the metal work function.

However, in the Schottky barrier transistor using the metal silicide, the reduction of the Schottky junction resistance due to the reduction of the Schottky barrier height through the control of the metal work function is limited by the Fermi level pinning effect.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a Schottky-barrier transistor which reduces the Schottky junction resistance between the silicide source / drain and the silicon channel, reduces the RC-delay time and increases the driving current, and a method of manufacturing the same. It is.

The Schottky-barrier transistor using a tensile silicon technology according to the present invention and a manufacturing method thereof according to the present invention for solving the above problems, in the method of manufacturing a Schottky barrier transistor semiconductor, (a) a gate insulating film, Forming an insulating spacer on the side of the gate electrode and the gate electrode, and implanting impurities into the semiconductor substrate using the gate pattern and the spacer with an ion implantation mask to form a source / drain region; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; And (d) selectively removing the remaining metal film after forming the silicide.

Here, the gate insulating film is preferably a high-k metal oxide having a dielectric constant greater than 4.0.

Here, the gate is preferably a highly doped polycrystalline polysilicon or metal.

Here, the spacer is preferably an oxide film.

Here, the source / drain is preferably made of any one of cobalt silicide, nickel silicide or titanium silicide.

In addition, in the method of manufacturing a Schottky barrier transistor semiconductor according to the present invention, (a) an insulating spacer is formed on a side surface of a gate insulating film, a gate electrode, and a gate electrode on a semiconductor substrate, and the gate pattern and the spacer are formed as an ion implantation mask. Implanting impurities into the semiconductor substrate to form source / drain regions; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; And (d) forming silicide and selectively removing the remaining metal film; And (e) selectively epitaxially growing the source / drain regions with silicon germanium to exert a tensile force.

Here, the semiconductor substrate is preferably any one of silicon, silicon germanium, or insulating layer buried silicon (SOI).

Here, the gate insulating film is preferably a high-k metal oxide having a dielectric constant greater than 4.0.

Here, the gate is preferably a highly doped polycrystalline polysilicon or metal.

Here, the spacer is preferably an oxide film.

Here, the source / drain is preferably made of any one of cobalt silicide, nickel silicide or titanium silicide.

In addition, in the method of manufacturing a Schottky barrier transistor semiconductor according to the present invention, (a) an insulating spacer is formed on a side surface of a gate insulating film, a gate electrode, and a gate electrode on the semiconductor substrate, and the gate pattern and the spacer are ion implanted masks. Implanting impurities into the semiconductor substrate to form source / drain regions; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; (d) forming silicide and selectively removing the remaining metal film; And (e) forming a silicon nitride (SiN) cap layer.

Here, the semiconductor substrate is preferably any one of silicon, silicon germanium, or insulating layer buried silicon (SOI).

Here, the gate insulating film is preferably a high-k metal oxide having a dielectric constant greater than 4.0.

Here, the gate is preferably a highly doped polycrystalline polysilicon or metal.

Here, the spacer is preferably an oxide film.

Here, the source / drain is preferably made of any one of cobalt silicide, nickel silicide or titanium silicide.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 illustrates a fabrication procedure of a Schottky-barrier transistor using a tensile silicon technology to include a silicide gate and a source / drain on a silicon germanium modified semiconductor substrate according to an embodiment of the present invention.

As shown, the Schottky-barrier transistor forms a silicon substrate 101, a gate insulating film 102, a poly silicon gate 103, a spacer 104, a source 105, and a drain 106 (100A). .

Here, the silicon 101 substrate is a silicon germanium strained semiconductor substrate, and an isolation region (not shown) is formed in a predetermined region of the silicon 101 to form an active region, and in the active region, the gate oxide film 102 and the poly silicon gate are formed. 103 is formed.

Here, the gate insulating film 102 is a high-k metal oxide having a dielectric constant greater than 4.0, and the gate 103 is a heavily doped polycrystalline polysilicon or metal.

Here, the polysilicon gate 103 is heavily doped with N-type impurities for the NMOS transistor, or heavily doped with P-type impurities for the PMOS transistor.

Here, spacers 104 are formed on the sidewalls of the gate insulating layer 102 and the polysilicon gate 103.

Here, the spacer 104 may be composed of an oxide film.

Here, the source 105 and drain 106 regions are heavily doped with N-type impurities for the NMOS transistors or heavily doped with P-type impurities for the PMOS transistors.

Next, the metal film 107 is deposited (100B).

Here, the metal film 107 is formed of any one of nickel, cobalt, and titanium.

Next, heat treatment is performed at a low temperature of 400 to 550 ° C. (100C).

Here, the metal film 107 in contact with the silicon surface reacts with silicon to form silicide, and the metal film 107 in contact with the oxide film surface (spacer region) does not react with the oxide film.

That is, the metal film 107 in contact with the polysilicon gate 103 and the source 105 / drain 106 reacts and is consumed, and the metal film 107 in contact with the spacer 104 does not react and is not consumed. Do not.

Here, the source 109 / drain 110 is any one of cobalt silicide, nickel silicide or titanium silicide.

As a result, the metal atoms of the metal film 107 react with the silicon atoms of the polysilicon gate 103, the source 105 / drain 106 to form the gate surface 108 and the thin source 109 and the drain 110. A metal silicide film is formed in the region.

Next, silicide is formed and the remaining metal film 107 is selectively removed (100D).

By this manufacturing method, the Schottky-barrier transistor reduces the Schottky barrier height between the silicide source / drain and the silicon channel, thereby lowering the Schottky junction resistance between the silicide source / drain and the silicon channel.

FIG. 2 illustrates a fabrication process of a Schottky-barrier transistor using a tensile silicon technique for depositing a silicon nitride capping layer on a front surface of a transistor substrate including a silicide gate and a source / drain according to another embodiment of the present invention. will be.

As shown, the Schottky-barrier transistor forms silicon 201, gate oxide 202, polysilicon gate 203, spacer 204, source 205, and drain 206 (200A).

Here, the silicon 201 is buried silicon, and an isolation region (not shown) is formed in a predetermined region of the silicon 201 to form an active region, and the gate oxide film 202 and the polysilicon gate 203 are formed in the active region. Is formed.

Here, the gate insulating film 202 is a high-k metal oxide having a dielectric constant higher than 4.0, and the gate 203 is a heavily doped polycrystalline polysilicon or metal.

Here, the polysilicon gate 203 is heavily doped with N-type impurities for the NMOS transistor, or heavily doped with P-type impurities for the PMOS transistor.

Here, a spacer 204 is formed on sidewalls of the gate oxide film 202 and the polysilicon gate 203.

Here, the source 205 and drain 206 regions are heavily doped with N-type impurities for the NMOS transistors or heavily doped with P-type impurities for the PMOS transistors.

Next, a metal film 207 is deposited (200B).

Here, the metal film 207 is formed of any one of nickel, cobalt, and titanium.

That is, the metal silicide technique is applied to the semiconductor substrate on which the above-described source 205 / drain 206 process is completed.

Next, heat treatment is performed at a low temperature of 400 to 550 ° C. (200C).

Here, the metal film 207 in contact with the silicon surface reacts with silicon to form silicide, and the metal film 207 in contact with the surface of the oxide film (spacer region) does not react with the oxide film.

That is, the metal film 207 in contact with the polysilicon gate 208 and the source 205 / drain 206 reacts and is consumed, and the metal film 207 in contact with the spacer 204 does not react and is not consumed. Do not.

Here, the source 209 / drain 210 is any one of cobalt silicide, nickel silicide or titanium silicide.

As a result, the metal atoms of the metal film 207 react with the silicon atoms of the poly silicon gate 203, the source 205 / drain 206 to form the gate surface 208 and the thin source 209 and the drain 210. A metal silicide film is formed in the region.

Next, silicide is formed and the remaining metal film 207 is selectively removed (200D).

Next, silicon nitride (SiN) 211 is deposited (200E).

By this manufacturing method, the Schottky-barrier transistor reduces the Schottky barrier height between the silicide source / drain and the silicon channel, thereby lowering the Schottky junction resistance between the silicide source / drain and the silicon channel.

FIG. 3 illustrates a fabrication procedure of a Schottky-barrier transistor using a tensile silicon technique for selectively epitaxially growing a source / drain region with silicon germanium according to another embodiment of the present invention.

As shown, the Schottky-barrier transistor forms 300 A in silicon 301, gate insulating film 302, poly silicon gate 303, spacer 304, source 305, and drain 306.

Here, the silicon 301 is buried silicon, and an isolation region (not shown) is formed in a predetermined region of the silicon 301 to form an active region, and the gate oxide layer 302 and the polysilicon gate 303 are formed in the active region. Is formed.

Here, the gate insulating film 302 is a metal oxide having a dielectric constant higher than 4.0 (high-k), and the gate 303 is a heavily doped polycrystalline polysilicon or metal.

Here, the polysilicon gate 303 is heavily doped with N-type impurities for the NMOS transistor, or heavily doped with P-type impurities for the PMOS transistor.

Here, a spacer 304 is formed on sidewalls of the gate insulating film 302 and the polysilicon gate 303.

Here, the spacer 304 may be composed of an oxide film.

Here, the source 305 and drain 306 regions are heavily doped with N-type impurities for the NMOS transistors or heavily doped with P-type impurities for the PMOS transistors.

Next, a metal film 307 is deposited (300B).

Here, the metal film 307 is formed of any one of nickel, cobalt, and titanium.

Next, heat treatment is performed at a low temperature of 400 ° C to 550 ° C (300C).

Here, the metal film 307 in contact with the silicon surface reacts with silicon to form silicide, and the metal film 307 in contact with the surface of the oxide film (spacer region) does not react with the oxide film.

That is, the metal film 307 in contact with the polysilicon gate 303 and the source 305 / drain 306 reacts and is consumed, and the metal film 307 in contact with the spacer 304 does not react and is not consumed. Do not.

As a result, the metal atoms of the metal film 307 react with the silicon atoms of the polysilicon gate 303, the source 305 / drain 306 to form the gate surface 308 and the thin source 309 and drain 310. A metal silicide film is formed in the region.

Here, the source 309 / drain 310 is any one of cobalt silicide, nickel silicide or titanium silicide.

Next, silicide is formed and the remaining metal film 307 is selectively removed (300D).

Next, the source 309 / drain 310 region is selectively epitaxially grown with silicon germanium (300E).

By this manufacturing method, the Schottky-barrier transistor reduces the Schottky barrier height between the silicide source / drain and the silicon channel, thereby lowering the Schottky junction resistance between the silicide source / drain and the silicon channel.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

According to the above-described configuration of the present invention, there is provided a Schottky-barrier transistor with a reduced Schottky junction resistance between the silicide source / drain and the silicon channel, and a method of manufacturing the same, thereby reducing the RC-delay time in the Schottky-barrier transistor and driving current. Has the effect of increasing.

Claims (17)

In the method of manufacturing a Schottky barrier transistor semiconductor, (a) forming an insulating spacer on a side surface of the gate insulating film, the gate electrode, and the gate electrode on the silicon germanium modified semiconductor substrate, and implanting impurities into the semiconductor substrate using an ion implantation mask to form a source / drain region; step; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; And (d) forming silicide and selectively removing the remaining metal film; Schottky-barrier transistor manufacturing method using a tensile silicon technology, comprising. The method of claim 1, And the gate insulating film is a high-k metal oxide having a dielectric constant greater than 4.0. The method of claim 1, Wherein said gate is a heavily doped polycrystalline polysilicon or metal. The method of claim 1, And the spacer is an oxide film. The method of claim 1, Wherein the source / drain is one of cobalt silicide, nickel silicide, or titanium silicide. In the method of manufacturing a Schottky barrier transistor semiconductor, (a) forming an insulating spacer on the side of the gate insulating film, the gate electrode, and the gate electrode on the semiconductor substrate, and implanting impurities into the semiconductor substrate using the gate pattern and the spacer with an ion implantation mask to form a source / drain region; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; And (d) forming silicide and selectively removing the remaining metal film; And (e) selectively epitaxially growing the source / drain regions with silicon germanium to exert a tensile force; Schottky-barrier transistor manufacturing method using a tensile silicon technology, including. The method of claim 6, Wherein said semiconductor substrate is one of silicon, silicon germanium, or insulating layer buried silicon (SOI). The method of claim 6, And the gate insulating film is a high-k metal oxide having a dielectric constant greater than 4.0. The method of claim 6, Wherein said gate is a heavily doped polycrystalline polysilicon or metal. The method of claim 6, And the spacer is an oxide film. The method of claim 6, Wherein the source / drain is one of cobalt silicide, nickel silicide, or titanium silicide. In the method of manufacturing a Schottky barrier transistor semiconductor, (a) forming an insulating spacer on the side surface of the gate insulating film, the gate electrode, and the gate electrode on the semiconductor substrate, and implanting impurities into the semiconductor substrate using the gate pattern and the spacer with an ion implantation mask to form source / drain regions; (b) depositing a metal film on the entire surface of the substrate; (c) heat treating the entire surface of the substrate to form metal silicide; (d) forming silicide and selectively removing the remaining metal film; And (e) forming a silicon nitride (SiN) cap layer; Schottky-barrier transistor manufacturing method using a tensile silicon technology, comprising. The method of claim 12, And said semiconductor substrate is one of silicon, silicon germanium, or insulating layer buried silicon (SOI). The method of claim 12, And the gate insulating film is a high-k metal oxide having a dielectric constant greater than 4.0. The method of claim 12, Wherein said gate is a heavily doped polycrystalline polysilicon or metal. The method of claim 12, And the spacer is an oxide film. The method of claim 12, Wherein the source / drain is one of cobalt silicide, nickel silicide, or titanium silicide.

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