KR20070071045A - Metal wiring formation method of semiconductor device and semiconductor device manufacturing method using same - Google Patents

Abstract

The present invention is to provide a method for forming a metal wiring of a semiconductor device and a method for manufacturing a semiconductor device using the same, which can increase the yield by preventing the occurrence of substrate defects in the pixel region when forming the copper wiring in the image sensor. Forming a first interlayer insulating film having a contact plug interposed therebetween; forming a hole for exposing the contact plug by etching a portion of the first interlayer insulating film; and forming an OH group on the surface of the substrate. Performing a first annealing process using hydrogen gas for desorption and a second annealing process using hydrogen radicals to remove defects generated on the surface of the substrate during etching of the first interlayer insulating film. And forming an isolated first metal layer in the trench to be in contact with the contact plug. The present invention provides a method for forming metal wiring of a semiconductor device.

Description

METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

1 to 11 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device and a method of manufacturing a semiconductor device using the same according to an embodiment of the present invention.

-Explanation of symbols for the main parts of the drawings-

10: substrate

11, 19, 25, 28: interlayer insulating film

12: contact plug

14: Hall

16: barrier film

17 seed layer

17a, 23, 26, 29: copper wiring

18, 24, 27: etching stop film

20: pattern hole

30: passivation film

33: bump

The present invention relates to a method of forming a metal wiring of a semiconductor device and a method of manufacturing a semiconductor device using the same, and more particularly, to a method of forming a copper wiring of an image sensor and a method of manufacturing an image sensor using the same.

Recently, many attempts have been made to reduce the interlayer thickness between metal wires in order to reduce noise in manufacturing an image sensor. One of them is to form copper (Cu) wiring using a damascene process. This is because copper maintains excellent wiring characteristics even at a thin thickness because copper has lower electrical conductivity than aluminum (Al).

On the other hand, such a copper wiring has a problem in that the reliability of the wiring deteriorates during the high temperature heat treatment due to the characteristics of copper, so that the high temperature heat treatment is difficult during the subsequent process. Considering this, when a defect occurs in the pixel region where the pixel including the photodiode and the plurality of transistors of the image sensor is to be formed by an etching process or other processes, hydrogen is transferred to a subsequent process. There is a problem that it is difficult to proceed with the high temperature heat treatment used.

In particular, a defect generated in the pixel region refers to a substrate defect in a region where a transistor constituting the pixel is formed. Substrate defects are caused by damage to the substrate surface due to the plasma used in the etching process. In particular, since these substrate defects are not neutral, but also have polarities, they act as traps in signal transmission using transistors, causing device malfunction.

The high temperature heat treatment using hydrogen is performed to recover the image sensor after the final metallization process is completed. However, in the related art, such high temperature heat treatment becomes difficult, resulting in a decrease in yield of the image sensor.

The present invention proposed to solve the problems of the prior art as described above, the method of forming a metal wiring of a semiconductor device that can increase the yield by preventing the occurrence of substrate defects in the pixel area when forming a copper wiring in the image sensor and using the same Its purpose is to provide a method for manufacturing a semiconductor device.

According to an aspect of the present invention, there is provided a method including forming a first interlayer insulating layer having a contact plug interposed therebetween, and etching a portion of the first interlayer insulating layer to expose the contact plug. Forming an oxide, performing a first annealing process using hydrogen gas to desorb OH groups on the surface of the substrate, and defects generated on the surface of the substrate during etching of the first interlayer insulating layer. And a second annealing process using hydrogen radicals to form a first metal layer in the trench to be connected to the contact plug. .

In one aspect of the present invention, after the first metal layer is formed, a second interlayer insulating film having a first pattern hole for exposing the first metal layer is formed on the first interlayer insulating film including the first metal layer. Performing the first and second annealing processes and cooling the entire structure, forming an isolated second metal layer in the first pattern hole, and the second interlayer including the second metal layer. Forming a third interlayer insulating film having a second pattern hole exposing the second metal layer on the insulating film, performing the first and second annealing processes and cooling the entire structure, and the second pattern The method may further include forming an isolated third metal layer in the hole.

In an aspect of the present invention, the method may further include cooling the entire structure of the second annealing process to trap the hydrogen radicals injected into the substrate in the first interlayer insulating film during the second annealing process. Can be.

According to another aspect of the present invention, there is provided a substrate on which a top metal layer is formed using a method of forming the second and third metal layers, and forming a passivation film covering the top metal layer. And forming a hole for exposing the top metal layer by etching a portion of the passivation film, and forming a bump to fill the hole.

Preferably, the bumps are formatted with nickel.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. Also, throughout the specification, the same reference numerals denote the same components.

Example

1 to 11 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device and a method of manufacturing a semiconductor device using the same according to an embodiment of the present invention.

First, as shown in FIG. 1, after forming a lower layer (not shown) on the substrate 10, an interlayer insulating layer 11 (hereinafter, referred to as a first interlayer insulating layer) is deposited to cover the lower layer. Subsequently, a contact plug 12 is formed in the first interlayer insulating film 11 to be electrically connected to the lower layer. Here, the lower layer may include a gate electrode, a source / drain, or the like of the transistor.

In addition, the first interlayer insulating layer 11 is formed of an oxide-based material. For example, the first interlayer insulating film 11 may include a high density plasma (HDP) oxide film, a boron phosphorus silicate glass (BPSG) film, a phosphorus silicate glass (PSG) film, a plasma enhanced tetra ethole ortho silicate (peteos) film, and plasma enhanced PECVD. Single layer film or lamination thereof using any one of Chemical Vapor Deposition (USG) film, USG (Un-doped Silicate Glass) film, FSG (Fluorinated Silicate Glass) film, Carbon Doped Oxide (CDO) film and Organic Silicate Glass (OSG) film It is formed into a laminated film.

Subsequently, an interlayer insulating film 13 (hereinafter referred to as a second interlayer insulating film) is deposited on the first interlayer insulating film 11, and then a mask process and an etching process are performed to form holes having a predetermined depth in the second interlayer insulating film 13. (14) is formed. Here, the hole 14 is for defining a region where the metal wiring is to be formed.

Subsequently, as illustrated in FIGS. 2 and 3, annealing is performed twice in a hydrogen atmosphere to generate defects on the surface of the substrate 10 during an etching process for forming the holes 14. Remove it.

First, as shown in FIG. 2, the first annealing process using hydrogen (Hydrogen, H ₂ ) gas is performed to desorb water, that is, OH groups, present on the surface of the substrate 10. This is because such moisture may cause deterioration of device characteristics in subsequent processes. Here, the first annealing process at 300 ~ 450 ℃ to the flow rate of H ₂ with 10 ~ 500sccm performed 1 ~ 5 minutes. Preferably, it carried out in H ₂ atmosphere at 450 ℃.

The first annealing process not only serves as a degas that desorbs OH groups adsorbed on the substrate 10, but also serves as an antenna of the contact plug 12 during the etching process for forming the holes 14. As a result, the plasma-induced damage generated in the substrate 10 is trapped with hydrogen to neutralize defects.

Subsequently, as shown in FIG. 3, the surface of the substrate 10 is subjected to a second annealing process using hydrogen radicals, thereby forming defects on the surface of the substrate 10 during the etching process for forming the holes 14. Remove it.

Here, the second annealing process is performed by using a remote plasma method. For example, after injecting hydrogen gas and inert gas into the chamber, only RF power is applied to convert hydrogen gas (H ₂ ) into hydrogen radical (H ⁺ ), and thus activated H ⁺ is used. Thus, defects on the surface of the substrate 10 can be reliably removed.

By using H ⁺ as described above, the surface of the contact plug 12 exposed to the bottom of the hole 14 is reduced to improve contact resistance, and the substrate is formed by diffusing the activated H ⁺ into the substrate 10. (10) The defect removal efficiency of the surface can be improved.

In particular, the RF power applied during the second annealing process has a range of 400 to 750 W, and argon (Ar) gas is used as the inert gas. Preferably, the gas ratio of H ₂ and Ar to be injected during the second annealing process is 0 to 0.8: 0.2 to 1. In addition, a 2nd annealing process is implemented within the temperature of 200-400 degreeC.

Subsequently, although not shown in the drawings, the entire structure in which the second annealing process is completed is trapped to trap H ⁺ diffused into the substrate 10 in the second annealing process during the second annealing process. Let's do it. Preferably, the temperature raised during the second annealing process is lowered to a temperature lower than room temperature.

Subsequently, as shown in FIG. 4, the barrier layer 16 and the seed layer 17 are sequentially deposited along the stepped portions of the second interlayer insulating layer 13 including the holes 14 (see FIG. 3). Here, the seed layer 17 is made of copper as a seed of the metallization material to be subsequently deposited.

Subsequently, as illustrated in FIG. 5, copper is deposited on a metal layer (not shown) for metal wiring so that holes 14 (see FIG. 3) are embedded on the seed layer 17. Then, the metal layer and the barrier film 16 are planarized to the upper portion of the second interlayer insulating film 13 to form metal wirings isolated in the holes 14, that is, copper wirings 17a (hereinafter referred to as first copper wirings). do.

Subsequently, as illustrated in FIG. 6, after the etch stop layer 18 is deposited on the second interlayer insulating layer 13 including the first copper wiring 17a, the interlayer insulating layer 18 may be formed on the etch stop layer 18. 19, hereinafter referred to as a third interlayer insulating film).

Subsequently, a pattern hole 20 exposing the first copper interconnection 17a in the third interlayer insulating layer 19 by etching a portion of the third interlayer insulating layer 19 and the etch stop layer 18 by applying a dual damascene technique. ). In this case, the pattern hole 20 has a dual damascene form.

Subsequently, as shown in FIGS. 6 and 7, the annealing process is performed twice in a hydrogen atmosphere to remove defects generated on the surface of the substrate 10 during the etching process for forming the pattern holes 20. Here, the second annealing process is carried out in the same process as the process described above in Figures 2 and 3, the recipe (recipe) is also the same (recipe), the effects thereof are also the same, and further description will be omitted.

Subsequently, although not shown in the figure, the entire structure in which the second annealing process is completed is cooled to trap H ⁺ diffused into the substrate 10 in the second annealing process in the insulating film. Preferably, the temperature raised during the second annealing process is lowered to a temperature lower than room temperature.

Subsequently, although not shown in the drawing, the barrier layer and the seed layer forming process may be performed to further form the barrier layer along the inner surface of the pattern hole 20.

Subsequently, as shown in FIG. 8, copper is deposited with a metal layer (not shown) for metal wiring so that the pattern holes 20 (refer to FIG. 7) are embedded, and then planarizes the copper wirings isolated in the pattern holes 20 ( 23, hereinafter referred to as second copper wiring).

Subsequently, as shown in FIG. 9, the same method as in FIGS. 6 to 8 is applied to form an interlayer insulating film interposed between a plurality of copper wires.

For example, an etch stop film 24 and an interlayer insulating film 25 (hereinafter referred to as a fourth interlayer insulating film) are deposited on the third interlayer insulating film 19 including the second copper wiring 23. Subsequently, a dual damascene type pattern hole (not shown) exposing the second copper interconnection 23 is formed in the fourth interlayer insulating layer 25 by applying the dual damascene technique.

Subsequently, an annealing process is performed twice in a hydrogen atmosphere to remove defects generated on the surface of the substrate 10 during the etching process for forming the pattern holes. Here, the second annealing process is carried out in the same process as described above in Figures 2 and 3, the recipe is also the same, and the effects on the same. However, at this time, the temperature is performed at a temperature lower than that in FIG. 6, for example, 200 ° C. to 400 ° C. during the first annealing step.

Subsequently, although not shown in the figure, the entire structure in which the second annealing process is completed is cooled to trap H ⁺ diffused into the substrate 10 in the second annealing process in the insulating film. Preferably, the temperature raised during the second annealing process is lowered to a temperature lower than room temperature.

Next, a copper wiring 26 (hereinafter referred to as a third copper wiring) is formed in the pattern hole.

Next, an etch stop film 27 and an interlayer insulating film 28 (hereinafter referred to as a fifth interlayer insulating film) are deposited on the fourth interlayer insulating film 25 including the third copper wiring 26. Subsequently, a dual damascene type pattern hole (not shown) for exposing the third copper wiring 26 is formed in the fifth interlayer insulating layer 28 by applying the dual damascene technique.

Subsequently, an annealing process is performed twice in a hydrogen atmosphere to remove defects generated on the surface of the substrate 10 during the etching process for forming the pattern holes.

Subsequently, although not shown in the figure, the entire structure in which the second annealing process is completed is cooled to trap H ⁺ diffused into the substrate 10 in the second annealing process in the insulating film. Preferably, the temperature raised during the second annealing process is lowered to a temperature lower than room temperature.

Next, a copper wiring 29 (hereinafter referred to as a fourth copper wiring) isolated in the pattern hole is formed by the uppermost metal wiring.

Subsequently, the passivation film 30 is deposited on the fifth interlayer insulating film 28 including the fourth copper wiring 29, and then selectively etched to form a hole (not shown) that exposes the fourth copper wiring. .

Next, as shown in FIGS. 9 and 10, two annealing processes are performed in a hydrogen atmosphere to remove defects generated on the surface of the substrate 10 during an etching process for forming holes. Here, the second annealing process is carried out in the same process as described above in Figures 2 and 3, the recipe is also the same, and the effects on the same.

Subsequently, nickel (Ni) is plated with a bump material as shown in FIG. 11 and then reflowed to form a dome-shaped bump 33.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, after forming a hole (or a pattern hole) exposing a metal layer on the substrate, an etching process using plasma for forming the pattern hole is performed by performing an annealing process twice in a hydrogen atmosphere. Defects generated on the surface of the substrate can be eliminated. Therefore, even in the image sensor, the plasma-induced damage can be efficiently removed to increase the yield.

In addition, by forming a bump directly connected to the uppermost metal wiring, it is possible to reduce defects due to the etching process for forming the pad.

In addition, hydrogen radicals can be used to pretreat the substrate surface while removing substrate defects, thereby simplifying the manufacturing process of the semiconductor device.

Claims (14)

Forming a first interlayer insulating film having a contact plug interposed on the substrate; Etching a portion of the first interlayer insulating film to form a hole exposing the contact plug; Performing a first annealing process using hydrogen gas to desorb OH groups present on the surface of the substrate; Performing a second annealing process using hydrogen radicals to remove defects generated on the surface of the substrate when the first interlayer insulating layer is etched; And Forming an isolated first metal layer in the trench to be in contact with the contact plug Metal wiring forming method of a semiconductor device comprising a. The method of claim 1, wherein after performing the second annealing process, And cooling the entire structure in which the second annealing process is completed to trap the hydrogen radicals injected into the substrate in the first interlayer insulating layer during the second annealing process. The method of claim 2, The cooling step is a metal wiring forming method of a semiconductor device for lowering the elevated temperature during the second annealing process to a temperature lower than room temperature. The method according to any one of claims 1 to 3, The first annealing process is a metal wiring forming method of a semiconductor device performed by the flow rate of the hydrogen gas 10 ~ 500sccm. The method of claim 4, wherein The first annealing process is a metal wiring forming method of a semiconductor device performed for 1 to 5 minutes at a temperature of 300 ~ 450 ℃. The method according to any one of claims 1 to 3, The second annealing process is a metal wiring forming method of a semiconductor device using a plasma method. The method of claim 6, The second annealing process, Injecting the hydrogen gas and an inert gas into a chamber; And Converting the hydrogen gas into the hydrogen radical by applying RF power and surface treating the substrate using the hydrogen radical; Metal wiring forming method of a semiconductor device comprising a. The method of claim 7, wherein The RF power is a metal wiring forming method of a semiconductor device to be applied in the range of 400 ~ 750W. The method of claim 7, wherein injecting the hydrogen gas and inert gas into the chamber, The argon (Ar) is used as the inert gas, but the gas ratio is Ar: H ₂ = 0 to 0.8: 0.2 to 1, wherein the metal wiring formation method of a semiconductor device. The method of claim 6, The second annealing process is a metal wiring forming method of a semiconductor device performed at a temperature of 200 ~ 400 ℃. The method according to any one of claims 1 to 3, wherein after forming the first metal layer, Forming a second interlayer insulating layer having a first pattern hole exposing the first metal layer on the first interlayer insulating layer including the first metal layer; Performing the first and second annealing processes and cooling the entire structure; Forming an isolated second metal layer in the first pattern hole; Forming a third interlayer insulating film on which the second pattern hole exposing the second metal layer is formed, on the second interlayer insulating film including the second metal layer; Performing the first and second annealing processes and cooling the entire structure; And Forming an isolated third metal layer in the second pattern hole Metal wiring forming method of a semiconductor device further comprising. The method of claim 11, And forming the second pattern hole, and then performing the first annealing process at a temperature of 200 to 400 ° C. Providing a substrate having a top metal layer formed thereon through the method of claim 11; Forming a passivation film covering the top metal layer; Etching a portion of the passivation film to form a hole exposing the top metal layer; And Forming a bump to fill the hole Semiconductor device manufacturing method comprising a. The method of claim 13, The bump is formed of a semiconductor device manufacturing method.

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