KR20080011550A - Manufacturing Method of Image Sensor - Google Patents

Abstract

In a method of manufacturing an image sensor on a semiconductor substrate having a first region, a second region, and a third region, a photodiode and a first gate insulating film are formed in the first region and a first gate is formed on the first gate insulating film. A first electrode of the capacitor is formed on the third region while forming an electrode. After forming a dielectric film on side surfaces of the first electrode of the capacitor, a second gate insulating film and a second gate electrode are formed in a second region of the substrate, and at the same time, the dielectric film is electrically connected to the first electrode of the capacitor through the dielectric film. A second electrode of the capacitor coupled to each other is formed on the third region. According to the above process, it is possible to manufacture an image sensor with improved capacitance while improving random noise characteristics.

Description

Method for manufacturing a image sensor

1 is an equivalent circuit diagram schematically illustrating a general image sensor.

2 to 11 are schematic process cross-sectional views and plan views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 104 photodiode

108: first gate insulating film 112: first gate electrode

122: second gate insulating film 126: second gate electrode

116: first electrode 118: dielectric film

128: second electrode

The present invention relates to a method of manufacturing an image sensor, and more particularly, to a method of manufacturing an image sensor including a photodiode and a gate structure.

In general, an image sensor among semiconductor devices is an element that converts an optical image into an electrical signal. Examples of the image sensor include a charge coupled device (CCD), a CMOS image sensor, and the like. In particular, recently, the drawbacks of the CMOS image sensor have been overcome by improvement of a signal processing algorithm, development of the CMOS process technology, and the manufacturing process of the charge coupled device has been replaced by the manufacturing process of the CMOS image sensor. Partial application to improves the quality of CMOS image sensors.

The CMOS image sensor includes a photodiode for detecting light as a unit pixel and a logic circuit for converting the light into an electrical signal. In recent years, the CMOS image sensor includes one photodiode and four transistors as a unit pixel. It is common to include.

1 is an equivalent circuit diagram illustrating a general CMOS image sensor.

Referring to FIG. 1, the CMOS image sensor includes a photodiode P / D, a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. The photodiode P / D is connected in series with the transfer transistor Tx and the reset transistor Rx, and the drain of the reset transistor Rx is connected with an applied voltage V _DD . In addition, the gate of the selection transistor Sx is connected to the floating diffusion region F / D. Here, the floating diffusion region F / D corresponds to the drain of the transfer transistor Tx (the source of the reset transistor Rx). The select transistor Sx is connected in series with the access transistor Ax, and the drain of the select transistor Sx is connected with an applied voltage V _DD .

The operation method of the CMOS image sensor is as follows.

First, when the reset transistor Rx is turned on, the potential of the floating diffusion region F / D becomes an applied voltage. At this time, when light is incident from the outside into the photodiode P / D, an electron-hole pair (EHP) is generated, and signal charges are accumulated in the source of the transfer transistor Tx. When the transfer transistor Tx is turned on, the signal charge accumulated in the source of the transfer transistor Tx is transferred to the floating diffusion region F / D. As a result, the potential of the floating diffusion region F / D changes, and the potential of the gate of the selection transistor Sx also changes. Subsequently, when the access transistor Ax is turned on by the selection signal Row, data is output to the output terminal Out. The optical image is converted into an electrical signal by continuously repeating the above process.

In operation of the CMOS image sensor, signal charge accumulated in the source of the transfer transistor Tx from the photodiode P / D when the transfer transistor Tx is turned on is converted into the floating diffusion region F. / D) must be delivered substantially completely. If the signal charge is not substantially completely transferred and a part of the signal charge remains in the photodiode P / D, the signal charge remaining in the photodiode P / D is the subsequent signal charge. Mixing with causes random noise, such as an image lag.

In the CMOS image sensor, the gate insulating film of the transistors Rx, Tx, Sx, and Ax is mainly formed of silicon oxynitride. In particular, in order to reduce the boron penetration which occurs frequently in the formation of the source / drain of the transistors Rx, Tx, Sx, and Ax, the gate insulating film is in contact with a substrate when the gate insulating film is formed. Concentrate the nitride on the surface. However, it has been confirmed that the random noise occurs more seriously when the nitride is concentrated on the surface of the gate insulating film in contact with the substrate.

It is an object of the present invention to provide a method of manufacturing an image sensor in which generation of random noise is suppressed.

According to an aspect of the present invention, there is provided a method of manufacturing an image sensor, including: providing a semiconductor substrate having a first region, a second region, and a third region; After the diode is formed, a first gate insulating layer is formed on the first region and adjacent to the photodiode. Subsequently, a first gate electrode is formed on the first gate insulating film, a first electrode of a capacitor is formed on the third region, and a dielectric film is formed on side surfaces of the first electrode of the capacitor. Forming a second gate insulating film in a second region of the substrate, forming a second gate electrode on the second gate insulating film, and simultaneously electrically coupling the first electrode of the capacitor through the dielectric film; A second electrode is formed on the third region.

In example embodiments, the first region is an active pixel region, the second region is a logic region, and the third region is a capacitor region.

The first gate insulating layer includes silicon oxide, a metal oxide, or a mixture thereof, and the second gate insulating layer includes silicon oxynitride.

The first gate insulating layer is formed to have a thickness thinner than that of the second gate insulating layer, and spacers are formed on sidewalls of the first gate electrode and the second gate electrode, respectively.

At this time, the side surfaces of the first electrode and the second electrode of the capacitor adjacent to each other have a concave-convex shape.

The image sensor manufactured as described above reduces random noise by forming the gate insulating film of the active region from silicon oxide. At the same time, by forming the gate insulating film of the logic region with the silicon oxynitride film, it is possible to sufficiently reduce the change in the threshold voltage characteristic due to boron penetration phenomenon. In addition, the capacitance of the capacitor can be increased by forming side surfaces of the first electrode and the second electrode of the capacitor in an uneven shape.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, openings, pads, or patterns are shown in greater detail than actual for clarity of the invention. In the present invention, each layer (film), region, pad, opening or pattern is formed on, "on" or "bottom" of the substrate, each layer (film), region, pad, opening or pattern. When referred to, that means that each layer (film), region, pad, opening or pattern is formed directly over or below the substrate, each layer (film), region, pad, opening or pattern, or otherwise Layers (films), other regions, other pads, other patterns or other structures may additionally be formed on the substrate. In addition, when each layer (film), region, pad, opening or pattern is referred to as "first" and / or "second", it is not intended to limit these members but merely each layer (film), region, pad To distinguish between openings or patterns. Thus, "first" and / or "second" may be used selectively or interchangeably for each layer (film), region, pad, opening or pattern, respectively.

2 to 11 are schematic process cross-sectional views and plan views for explaining a method of manufacturing an image sensor according to an embodiment of the present invention.

Referring to FIG. 2, device isolation layers 102a and 102b and a photodiode 104 are formed in the semiconductor substrate 100.

 Specifically, a semiconductor substrate 100 having a first region, a second region, and a third region is provided. In this case, the first region is an active pixel region for forming unit pixels, the second region is a logic region, and the third region is a capacitor region.

Impurities are partially doped in the first region to form a channel region (not shown). In this case, the channel region is a subsequent process and corresponds to a region where a first gate insulating layer (FIG. 3, 108) is to be formed. Here, examples of the impurity for forming the channel region include a p-type impurity as a Group 3 element, an n-type impurity as a Group 5 element, and the like.

Subsequently, the first device isolation layer 102a and the second device isolation layer 102b are formed in the first region of the substrate 100 to define the field region and the active region, respectively.

Hereinafter, a process of forming the first and second device isolation layers 102a and 102b will be described in detail. A buffer oxide film (not shown) is formed on the semiconductor substrate 100. The buffer oxide film is a film for relieving stress when forming a silicon nitride film. Subsequently, a silicon nitride film (not shown) is formed on the buffer oxide film. A portion of the silicon nitride film is removed by a photo process to form a silicon nitride film pattern (not shown). The buffer oxide layer is dry-etched using the silicon nitride layer pattern as an etching mask to form a buffer oxide layer pattern (not shown).

Subsequently, the exposed semiconductor substrate 100 is etched to a predetermined depth using the silicon nitride film pattern as an etching mask to form a trench (not shown). A silicon oxide film (not shown) is embedded in the trench and planarized to expose a silicon nitride film pattern. The silicon nitride layer pattern and the buffer oxide layer pattern are removed by a wet etching process to form first and second device isolation layers 102a and 102b.

Subsequently, a photodiode 104 is formed under the substrate 100 adjacent to the channel region. Specifically, the second photodiode 104b is formed by doping the second impurity under the substrate 120. The first photodiode 104a is formed by doping a first impurity on the second photodiode 104b. In particular, a Group 5 element such as phosphorus (P), Arsenic (As) or the like is selected as the second impurity, and a Group 3 element such as boron (B) or the like is selected as the first impurity.

In the present embodiment, the process is performed in the order of the channel region, the second photodiode 104b and the first photodiode 104a. However, in some cases, the process sequence may be appropriately adjusted. . In another embodiment, the process may be performed in the order of the channel region 23, the first photodiode 104a, and the second photodiode 104b.

The first oxide layer 106 is formed on the substrate 100 on which the device isolation layers 102a and 102b and the photodiode 104 are formed. The first oxide film 106 is formed of a first gate insulating film (Figs. 3 and 108) in the first region in a subsequent process.

 Examples of the oxide forming the first oxide film 106 include silicon oxide, metal oxide, and the like. And examples of the metal oxides include hafnium oxide, zirconium oxide, tantalum oxide, aluminum oxide, titanium oxide and the like.

According to an embodiment of the present invention, when the first oxide film 106 is a silicon oxide film made of silicon oxide, the first oxide film 106 is formed by performing a radical oxidation process, a thermal oxidation process, a chemical vapor deposition process, or the like. can do.

According to another embodiment of the present invention, when the first oxide film 106 is a metal oxide film including a metal, the first oxide film 106 may be formed by performing a chemical vapor deposition process, an atomic layer deposition process, or the like. have.

Referring to FIG. 3, a first gate insulating layer 108 and a first conductive layer 110 are formed in the first region.

Specifically, the first oxide film 106 is patterned to form a first gate insulating film 108. In this case, the patterning is performed after forming a first photoresist pattern (not shown) on the first oxide film 106, the etching process is performed using the first photoresist pattern as a mask. In this step, the first gate insulating film 108 is formed by leaving a part of the first oxide film 106 in the first region.

next. A first conductive layer 110 is formed on the first gate insulating layer 108.

Examples of the first conductive layer 110 may include polysilicon, a metal, a metal nitride, or the like. Examples of the metal include titanium, tantalum, tungsten, aluminum, hafnium, zirconium, copper and the like. It is preferable to use these, and you may use them in mixture of 2 or more. Further, examples of the metal nitrides include titanium nitride, tantalum nitride, tungsten nitride, aluminum nitride, hafnium nitride, zirconium nitride, and copper nitride. According to one embodiment of the present invention, the first conductive film 110 is preferably formed of a polysilicon film.

Referring to FIG. 4, a first gate electrode 112 is formed on the first gate insulating layer 108 of the first region, and a preliminary first electrode 114 of the capacitor is formed on the third region.

First, a second photoresist pattern (not shown) is formed on the first conductive layer 110, and the first conductive layer 110 is patterned using the second photoresist pattern as an etching mask. In this case, the second photoresist pattern is simultaneously formed in the first region and the third region. As described above, the first gate electrode 112 is formed on the first gate insulating layer 108 of the first region. At the same time, the preliminary first electrode 114 of the capacitor is formed on the third region.

5 and 6, the first electrode 116 and the dielectric film 118 are formed in the third region.

The preliminary first electrode 114 formed in the third region is formed as the first electrode 116 by performing a normal photolithography process. At this time, as shown in FIG. The first electrode 116 is patterned so that the side surface has an uneven shape. Due to the concave-convex shape as described above, it is possible to increase the capacitance of the capacitor to be completed in a subsequent process.

Subsequently, a dielectric film 118 is formed on side surfaces of the first electrode 116. The dielectric film 118 may be formed of an ONO film or a metal oxide film having a relatively high dielectric constant.

7 and 8, the second gate insulating layer 122 and the second conductive layer 124 are formed in the second region of the substrate 100.

First, a second oxide film 120 is formed on a substrate on which the first gate electrode 112, the first electrode 116, and the dielectric film 118 are formed. The second oxide film 120 may be formed through substantially the same process as the first oxide film 106.

Accordingly, a detailed description of the process for forming the second oxide film 120 will be omitted.

Next, the second gate insulating film 122 and the second conductive film 124 are formed. The second oxide film 120 may be formed by nitriding the surface of the second oxide film 120 in a nitriding atmosphere. By the nitriding treatment, a part of the surface of the second oxide film 120 is modified to a silicon oxynitride film (not shown).

The nitriding treatment is preferably performed by plasma nitriding treatment. When the plasma nitriding treatment is performed at a temperature exceeding about 200 ° C., the nitriding region may be extended to a region in contact with the substrate. Therefore, the plasma nitridation treatment in this embodiment is preferably carried out at a temperature of about 20 to 200 ℃. Examples of the process gas for the plasma nitridation treatment include N ₂ , N ₂ O, NO, NH ₃ , and the like. These may be used alone or in combination of two or more.

The above nitriding treatment is intended to prepare for boron penetration which occurs frequently in the formation of subsequently formed source / drain.

Subsequently, the second oxide film 120 having a portion of the surface modified with the silicon oxynitride film is subjected to a normal photolithography process, and patterned so that only a predetermined portion of the second region remains. As described above, a second gate insulating layer 122 is formed in the second region. In this case, the second gate insulating layer 122 may be formed to have a higher thickness than the first gate insulating layer 108. This is because borons penetrate the second gate insulating layer 122 and penetrate into the channel region of the semiconductor substrate from the second gate electrode 126 that is subsequently formed to change the flat band voltage (Vfb) and the threshold voltage. It is to prevent it.

Subsequently, a second conductive layer 124 is formed on the substrate 100 on which the second gate insulating layer 122 is formed. In this case, the second conductive layer 124 may have a step due to the first electrode 116 and the dielectric layer 118 formed in the third region. Therefore, a process such as chemical mechanical polishing to planarize the surface of the second conductive layer 124 may be performed.

 The second conductive layer 124 may be formed through the same material and process as the first conductive layer 110. Accordingly, detailed description for forming the second conductive film 124 will be omitted.

9 to 11, a second gate electrode 126 is formed in the second region and a second electrode 128 is formed in the third region.

First, a third photoresist pattern (not shown) is formed on the second conductive film. Subsequently, an etching process using the third photoresist pattern as a mask is performed. In this case, the third photoresist pattern is simultaneously formed in the second region and the third region. By the above process, the second gate electrode 126 is formed in the second region, and the second electrode 128 of the capacitor is formed in the third region. At this time, as shown in FIG. 10, side surfaces of the first electrode 116 and the second electrode 128 adjacent to the first electrode 116 of the capacitor have a concave-convex shape, and thus, the capacitor of the capacitor It can improve the situation.

Subsequently, a nitride film is deposited and anisotropically etched on the first region, the second region, and the third region to form a first spacer on the sidewalls of the first gate electrode 112, the second gate electrode 126, and the capacitor, respectively. 130a), second spacers 130b, and third spacers 130c are formed.

After forming the first spacer 130a, the second spacer 130b, and the third spacer 130c, an ion implantation process is performed to diffuse impurities to function as source / drain regions on the surface portions of the substrate. Form regions (not shown).

By performing the above process, a first gate structure is formed in a form in which a first gate insulating layer 108 and a first gate electrode 112 formed of an oxide film are stacked in the first region. In the second region, a second gate structure including a second gate insulating layer 122 and a second gate electrode 126 including a silicon oxynitride layer having an upper surface modified with an oxynitride layer is formed. In addition, the third region is interposed between a first electrode 116, a second electrode 128 electrically connected to the first electrode 116, and the first electrode 116 and the second electrode 128. A capacitor including the dielectric film 118 is formed.

Thereafter, an interlayer insulating film (not shown), a color filter (not shown), and a micro lens (not shown) are sequentially formed on the substrate 100 on which the impurity diffusion region is formed, thereby completing an image sensor.

In this case, the interlayer insulating film is formed in a multilayer structure and is formed using a material having excellent light transmissivity, such as silicon oxide. In addition, the color filter is formed for realizing a color image, and after the photoresist dyed mainly red (R), green (G), blue (B) is formed on the interlayer insulating film, and selectively patterned Form. The micro lens is formed by applying a photoresist on the color filter and then performing heat treatment.

The image sensor manufactured by the process as described above can also reduce the generation of random noise and boron penetration sufficiently. In addition, the capacitance can be improved by forming the first electrode and the second electrode of the capacitor in an uneven form.

According to the present invention, the gate insulating film formed in the active region is formed of an oxide, so that random noise can be reduced. At the same time, by forming the gate insulating film formed in the logic region with the silicon oxynitride film, it is possible to sufficiently prevent the boron penetration phenomenon without affecting the random noise characteristic. Therefore, it is possible to sufficiently reduce the change in the threshold voltage characteristic due to the boron penetration phenomenon. In addition, according to the present invention, capacitances can be increased by forming side surfaces of the first electrode and the second electrode of the capacitor in an uneven shape, respectively.

Therefore, an image sensor having good electrical characteristics can be manufactured.

As described above, although described with reference to preferred embodiments of the present invention, those skilled in the art will be variously modified and modified without departing from the spirit and scope of the invention described in the claims below. It will be appreciated that it can be changed.

Claims (7)

Providing a semiconductor substrate having a first region, a second region, and a third region; Forming a photodiode on a surface portion of the substrate in the first region; Forming a first gate insulating layer adjacent to the photodiode on the first region; Forming a first gate electrode on the first gate insulating film and simultaneously forming a first electrode of the capacitor on the third region; Forming a dielectric film on sides of the first electrode of the capacitor; Forming a second gate insulating film in a second region of the substrate; And Forming a second gate electrode on the second gate insulating layer, and simultaneously forming a second electrode of the capacitor on the third region electrically coupled with the first electrode of the capacitor through the dielectric layer; The manufacturing method of the image sensor. The method of claim 1, wherein the first region is an active pixel region, the second region is a logic region, and the third region is a capacitor region. The method of claim 1, wherein the first gate insulating layer comprises silicon oxide, metal oxide, or a mixture thereof. The method of claim 1, wherein the second gate insulating layer comprises silicon oxynitride. The method of claim 1, wherein the first gate insulating layer is formed to have a thickness lower than that of the second gate insulating layer. The method of claim 1, wherein the side surfaces of the first electrode and the second electrode of the capacitor adjacent to each other have a concave-convex shape. The method of claim 1, further comprising forming spacers on sidewalls of the first gate electrode and the second gate electrode, respectively.

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