KR20080068411A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device contacts a semiconductor substrate in which active regions are defined by an isolation layer, active regions, and a plurality of contacts having a trapezoidal shape that increases in width downward, and a plurality of conductive lines and contacts arranged on each contact. It includes an interlayer insulating film filling the gap.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for fabricating the same}

1 is a plan view of a semiconductor device according to an embodiment of the present invention.

2A and 2B are cross-sectional views of semiconductor devices according to example embodiments, taken along lines A-A 'and B-B' of FIG. 1.

3A through 11A are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present inventive concept. FIG. 3A through 11A are cross-sectional views taken along the line AA ′ of FIG. 1.

3B through 11B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and are taken along the line BB ′ of FIG. 1.

<Explanation of symbols on main parts of the drawings>

100: semiconductor substrate 102: device isolation film

104: active area 106, 106s, 106d: source / drain area

110: gate insulating film 120: gate line

130: first interlayer insulating film 132: first insulating film

134: second insulating film 142: common source line

144: first trench 146: first line pattern

150: second interlayer insulating film 152: second trench

154: second line pattern 160: line pattern for forming a contact

162: bit line contact 170: bit line

180 mask 190: third interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of increasing a contact area of a bit line contact and preventing misalignment between an active region, a bit line contact, and a bit line, and a manufacturing thereof. It is about a method.

As the degree of integration of a semiconductor device increases, the size of the contact for connecting the device and the device or the layer and the layer decreases while the thickness of the interlayer insulating film increases. In general, such a contact is formed by etching a predetermined region of the insulating layer to form a contact hole, and filling a conductive material in the contact hole.

However, when forming a contact as the degree of integration of a semiconductor device increases, an aspect ratio of the contact hole increases, thereby decreasing an alignment margin of the contact hole. That is, the width of the contact hole may gradually decrease toward the lower portion, or the contact hole may not be completely opened. Therefore, the resistance of the contact can be increased and the characteristics of the semiconductor device can be changed.

Therefore, when the size of the contact hole is increased to secure the lower width of the contact hole, the upper width of the contact hole may also increase to be connected between adjacent contact holes, which causes a bridge phenomenon between the contacts.

In addition, when forming the active region, the bit line contact, and the bit line electrically connected to each other, since they are formed separately, misalignment may occur between the active region, the bit line contact, and the bit line. This phenomenon may generate a leakage current into the active region due to over etch when forming the contact hole, and may increase the resistance of the bit line contact. It is also possible to generate a bridge between the bit line and another bit line contact next to it.

SUMMARY The present invention is directed to a semiconductor device capable of increasing the contact area of a bit line contact and preventing misalignment between an active region, a bit line contact, and a bit line.

In addition, another technical problem to be achieved by the present invention is to provide a method for manufacturing such a semiconductor device.

The technical problem to be achieved by the present invention is not limited to the above-mentioned problem, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above technical problem, a semiconductor device according to an embodiment of the present invention contacts a semiconductor substrate and active regions in which active regions are defined by device isolation layers, and has a plurality of trapezoidal shapes that increase in width downward. A contact, a plurality of conductive lines arranged on each contact, and an interlayer insulating film that fills between the contacts.

In order to achieve the above technical problem, a semiconductor device manufacturing method according to an embodiment of the present invention forms an isolation layer in a semiconductor substrate to define active regions, a first interlayer insulating layer is formed on the semiconductor substrate, and contacts are formed. A trench for exposing the semiconductor substrate in a line form is formed in a first interlayer insulating film of a predetermined region to be formed, and a conductive material is filled in the trench to form a line pattern, and is positioned above the active region, and crosses the line pattern, Forming conductive lines, etching the line pattern until the semiconductor substrate is exposed using the conductive lines as an etch mask to form contacts, and forming a second interlayer insulating layer filling the contacts.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The present invention can be applied to a semiconductor device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a read only memory (ROM), a flash memory device, and the like, and in one embodiment of the present invention, a NAND type A flash memory device will be described as an example.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A to 11A, and 2B to 11B.

First, a structure of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, wherein the cell region of FIG. 2 is taken along the line II-II 'of FIG. 1. It is a cross-sectional view.

As shown in FIGS. 1, 2A, and 2B, the active region 104 is defined in the semiconductor substrate 100 by the device isolation layer 102. The active regions 104 are parallel to each other in a line shape, and a gate insulating layer 110 is formed on the active regions 104.

The gate lines 120 crossing the active regions 104 are parallel to each other on the semiconductor substrate 100, and the gate lines 120 are a string select line SSL and a plurality of word lines WL _0. … … WL _n ) and ground select lines GSL. In more detail, a plurality of word lines WL ₀ between the string select line SSL and the ground select line GSL. … … WL _n are located and form a plurality of memory cell arrays, the plurality of word lines WL _0. … … WL _n and a string select line SSL and a ground select line GSL positioned outside to constitute a string as one memory unit.

The word line WL ₀ ... A source / drain region 106 is formed in the active region 104 between WL _n , and the source region 106s of the string is located in the active region 104 outside the ground select line GSL, and the string selection is performed. The drain region 106d of the string is positioned in the active region outside the line SSL.

The string select line SSL and the plurality of word lines WL ₀ … … WL _n and ground select lines GSL have a stack gate structure. In more detail, the gate line 120 has a structure in which the gate insulating layer 110, the floating gate 122, the dielectric layer 124, the control gates 126a and 126b, and the capping layer 128 are stacked.

The string selection line SSL and the plurality of word lines WL _{0 are} formed on the semiconductor substrate 100. … … A first interlayer insulating layer 130 is disposed to cover WL _n and the ground select lines GSL. The first interlayer insulating layer 130 may include a string select line SSL and a plurality of word lines WL _0. … … The first insulating layer 132 conformally covering the WL _n and the ground selection lines GSL, and the second insulating layer 134 positioned on the first insulating layer 132 and flattened thereon.

The first interlayer insulating layer 130 has a common source line CSL formed in parallel with the ground select line GSL between adjacent ground select lines GSL. The common source line CSL is electrically connected to the source region 106s formed between the ground select lines GSL.

As such, the second interlayer insulating layer 150 is positioned on the first interlayer insulating layer 130 including the common source line CSL, and the lower common source line CSL and the word are disposed on the second interlayer insulating layer 150. Line (WL ₀ … … Bit lines 170 are formed to be perpendicular to the WL _n ). Each of the bit lines 170 is electrically connected to drain regions 106d between adjacent string select lines SSL by a bit line contact 162 disposed below.

The bit line contact DC penetrating the first and second interlayer insulating layers 130 and 150 under the bit line 170 is self-aligned with respect to the bit line 170. The bit line contact 162 is formed to have a trapezoidal shape to have a lower width that is larger than an upper width. Therefore, the contact area between the bit line contact 162 and the active region 104 can be increased, and the occurrence of misalignment between the bit line contact 162 and the active region 104 can be reduced.

Hereinafter, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2A to 11A and 2B to 11B.

3A through 11A are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present inventive concept. FIG. 3A through 11A are cross-sectional views taken along the line AA ′ of FIG. 1. 3B through 11B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and are taken along the line BB ′ of FIG. 1.

First, as shown in FIGS. 3A and 3B, an isolation layer 102 defining an active region 104 by performing a local oxide of silicon (LOCOS) process or a shallow trench isolation (STI) process on a semiconductor substrate 100. ). The device isolation layer 102 defines the active regions 104 in a line shape extending in one direction and parallel to each other.

Then, the gate insulating layer 110 is formed on the upper surface of the active region 104, and then a plurality of gate lines 120 are formed on the semiconductor substrate 100 and extend in one direction across the active region 104. do. The plurality of gate lines 120 may be spaced apart from each other by a plurality of gate lines 120 and may be divided into a string selection line SSL, a plurality of word lines WL _{0 ...} WLn, and a ground selection line GSL.

A method of forming the gate lines 120 will be described in detail. A gate insulating film 110 formed of a silicon oxide film is formed on an upper surface of the active region 104, and a floating gate is formed on the semiconductor substrate 100 on which the gate insulating film 110 is formed. The conductive film 122, the dielectric film 124, the control gate conductive films 126a and 126b, and the capping film 128 are sequentially stacked.

In this case, the floating gate conductive film 122 may be formed by depositing a polysilicon film, and the dielectric film 124 may be formed of an oxide / nitride / oxide (ONO) film. The control gate conductive film may be formed by stacking the polysilicon film 126a and the metal silicide film 126b. In addition, the capping film 128 may be formed by depositing a silicon nitride film.

Then, the capping layer 128 is patterned to form an etch mask, and then the conductive gate conductive layers 126a and 126b and the dielectric layer 124 are sequentially formed until the semiconductor substrate 100 is exposed using the etch mask. And etching the conductive film 122 for the floating gate to form a plurality of gate lines 120. In this case, the gate lines 120 are perpendicular to the active regions 104 of the semiconductor substrate 100.

After the gate lines 120 are formed on the semiconductor substrate 100, the source / drain regions 106 and 106d in the active region 104 of the semiconductor substrate 100 using the gate lines 120 as an ion implantation mask. , 106s).

Then, a first interlayer insulating layer 130 covering the gate lines 120 is formed on the semiconductor substrate 100. The first interlayer insulating layer 130 may be formed of the first insulating layer 132 and the second insulating layer 134. That is, the first insulating layer 132 is first formed conformally on the semiconductor substrate 100 on which the plurality of gate lines 120 are formed. In this case, the first insulating layer 132 may be formed of an insulating material having good embedding characteristics to sufficiently fill the gaps between the gate lines 120. Therefore, the word line WL ₀ positioned between the string select line SSL and the ground select line GSL. … … Since WL _n has a narrow gap, the word line WL ₀ … … The first insulating layer 132 may be buried between WL _n ). The first insulating layer 132 may be formed of, for example, a material such as BoroPhosphoSilicate Glass (BPSG), Plasma Enhanced Tetra Ethyl Ortho Silicate (PE-TEOS), High Density Plasma (HDP), or Undoped Silicate Glass (USG). .

Thereafter, the second insulating film 134 is deposited on the first insulating film 132 to a sufficient thickness, and the top is planarized to complete the first interlayer insulating film 130.

Next, as shown in FIGS. 4A and 4B, trenches are formed in the first interlayer insulating layer 130 to expose the active region 104 between the ground select lines GSL. The trench is formed in parallel with the ground select lines GSL. A metal source such as W, Al, or Cu is then embedded in the trench to form a common source line 142.

Next, as shown in FIGS. 5A and 5B, a first trench 144 is formed in the first interlayer insulating layer 130 to expose a region where bit line contacts are to be formed. That is, the first trench 144 in the form of a line is formed to expose the semiconductor substrate 100 between the string select lines SSL. Then, a polysilicon film is deposited on the first interlayer insulating film 130 so that the first trench 144 is filled, and the entire surface of the polysilicon film is etched until the first interlayer insulating film 130 is exposed. As shown in 6b, the first line pattern 146 is formed.

7A and 7B, a second interlayer insulating layer 150 is formed on the first interlayer insulating layer 130 on which the common source line CSL and the first line pattern 146 are formed.

8A and 8B, a predetermined region of the second interlayer insulating layer 150 is etched to expose the top surface of the first line pattern 146 formed on the first interlayer insulating layer 130 to form a second portion. Trench 152 is formed.

Thereafter, a polysilicon film is deposited on the second interlayer insulating film 150 to fill the second trench 152, and planarized until the second interlayer insulating film 150 is exposed, as shown in FIGS. 9A and 9B. As described above, the second line pattern 154 is formed on the first line pattern 146. As a result, the contact pattern line pattern 160 contacting the semiconductor substrate 100 between the string select lines SSL is completed.

In the exemplary embodiment of the present invention, the line pattern is formed by dividing the first and second interlayer insulating layers 130 and 150, but the second pattern is formed up to the second interlayer insulating layer, and then the line pattern is formed over the first and second interlayer insulating layers. A trench may be formed, and a polysilicon film may be embedded in the trench.

Next, as shown in FIGS. 10A and 10B, the barrier layer 172, the bit line conductive layer 174, and the capping layer may be formed on the second interlayer insulating layer 150 and the contact pattern line pattern 160. 176) are sequentially stacked. In this case, when the barrier layer 172 is formed of a conductive film such as W, Cu, or Al in order to prevent diffusion of a metal material and reduce contact resistance, Ta, TaN, TaSiN, Ti may be used. , TiN, TiSiN, W, WN or a combination thereof. The capping film 176 may be formed of a nitride film for use as a hard mask for forming a bit line.

Afterwards, the capping layer 176 is patterned to etch the conductive layer 174 and the barrier layer 172 for the bit line, so that the bit line 170 is positioned perpendicular to the lower gate lines 120 and extends in one direction. To complete. The bit lines 170 are also perpendicular to the contact forming line pattern 160 formed over the first and second interlayer insulating layers 130 and 150, so that predetermined regions of the bit lines 170 are formed for contact formation. In contact with the line pattern 160.

11A and 11B, a mask 180 is formed on the second interlayer insulating layer 150 on which the bit line 170 is formed to expose the contact pattern line pattern 160. The mask 180 may be formed in a line shape to expose the surface of the contact forming line pattern 160 and the bit lines 170 positioned on the contact forming line pattern 160.

Thereafter, the contact forming line pattern 160 exposed by the mask 180 is etched using the upper bit lines 170 as an etching mask until the lower device isolation layer 102 is exposed. Accordingly, a hole 164 exposing the device isolation layers 102 between adjacent string select lines SSL is formed, and a bit line contact electrically connecting the bit line 170 and the active region 104 to each other. 162 are completed.

When the hole 164 is formed in the contact forming line pattern 160, the hole 164 is formed to have an inclined sidewall due to etching characteristics, thereby completing the hole 164 having a lower width smaller than the upper width. Accordingly, the bit line contact 162 positioned below each bit line 170 may have a lower width than an upper width, and thus may have a trapezoidal shape.

As such, after the bit lines 170 are formed, the line patterns 160 are etched using the bit lines 170 as an etching mask to align each bit line contact 162 with respect to the bit lines 170. Can be formed. In addition, when the holes 164 exposing the device isolation layer 102 are formed in the line pattern 160, holes 164 that become narrower toward the lower portion due to the etching characteristics are formed. The separated bit line contact 162 may increase in width toward the bottom thereof to increase the contact area with the active region 104. In addition, since the hole 164 exposing the device isolation layer 102 is formed when the bit line contact 162 is formed, damage to the active region 104 may be suppressed.

Thereafter, as shown in FIGS. 2A and 2B, a third interlayer insulating layer 190 is formed on the bit line 170 to fill the hole 164 between the bit line contacts 162. Accordingly, the bit line contacts 162 may be insulated. Here, the third interlayer insulating layer 190 may be formed of a material having a good gap-fill property, for example, Tonen SilaZene (TOSZ).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the semiconductor device of the present invention and a method of manufacturing the same, a bit line contact that is self-aligned with the bit line may be formed by forming a bit line on a line pattern and then forming a contact for the bit line. At the same time, the contact for each bit line can be formed in a trapezoidal shape, the width of which gradually increases toward the bottom, so that the contact area of the bit line contact can be increased. In addition, since the lower width of the bit line contact is greater than the upper width, misalignment between the active region and the bit line contact may be prevented.

In addition, since the semiconductor substrate is exposed in the form of a line to form a bit line contact, damage to the active region due to etching can be reduced, and leakage current to the active region can be reduced.

Claims (12)

A semiconductor substrate in which active regions are defined by an isolation layer; A plurality of contacts in contact with the active regions, each of which has a trapezoidal shape that increases in width downward; A plurality of conductive lines arranged on each contact; And And an interlayer insulating layer filling the gaps between the contacts. The method of claim 1, And the active regions are formed in parallel with each other. The method of claim 1, And the plurality of conductive lines are located above the active regions. The method of claim 1, And the contact is self aligned with respect to each conductive line. Forming an isolation layer in the semiconductor substrate to define active regions, Forming a first interlayer insulating film on the semiconductor substrate, Forming a trench in the form of a line in the first interlayer insulating film in a predetermined region where contacts are to be formed; Filling the trench with a conductive material to form a line pattern, Conductive lines disposed on the active region and crossing the line pattern and parallel to each other, Etching the line pattern until the semiconductor substrate is exposed using the conductive lines as an etch mask to form the contacts, And forming a second interlayer insulating film filling the contacts. The method of claim 5, wherein And the device isolation layer defines the active regions in parallel to each other. 7. The method of claim 6, wherein after defining the active region, Forming a plurality of gate lines across the active regions. The method of claim 6, And forming the trench to cross the active regions. The method of claim 6, wherein forming the contact, And forming a lower width of the contact larger than an upper width. The method of claim 6, wherein forming the contact, Forming a line-type mask that exposes the line pattern and some of the conductive lines on the line pattern, By using the conductive line exposed by the mask as an etch mask, the line pattern is etched until the semiconductor substrate is exposed to form holes. A method of manufacturing a semiconductor device comprising removing the mask. The method of claim 10, wherein forming the hole, And etching the line pattern until the device isolation layer is exposed using the conductive lines as an etch mask. The method of claim 11, The hole is a semiconductor device manufacturing method that is gradually reduced in width toward the bottom.

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