KR20090001078A - Method for forming alignment key of semiconductor device - Google Patents

Abstract

A formation method of the alignment key of the semiconductor device is provided to improve the property of device and alignment-accuracy by forming the alignment key using the spacer formed in both sides of the hard mask layer pattern as the etching mask. An etched layer is formed on the top of the semiconductor substrate(200). A hard mask layer pattern(230a) is formed on the top of the etched layer. The etched layer comprises the amorphous carbon layer and SiON. The spacer(255) is formed at both sides of the hard mask layer pattern. The hard mask layer pattern is removed. The etched layer located in the lower part of spacer is etched by using the spacer as a mask. And then, the alignment key is formed by removing the spacer.

Description

Method for forming alignment key of semiconductor device {METHOD FOR FORMING THE ALIGNMENT KEY OF SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views illustrating a method for forming an alignment key of a semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method for forming an alignment key of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

100, 200: semiconductor substrate 110, 210: amorphous carbon layer

120 and 220: silicon oxynitride films 130 and 230: hard mask layer

140, 240: antireflection film 150: photosensitive film pattern

110a, 210a: amorphous carbon layer pattern 120a, 220a: silicon oxynitride film pattern

130a and 230a: Hard Mask Layer Pattern 225: Etched Layer

225a: alignment key 250: first photosensitive film pattern

255: spacer 260: second photosensitive film pattern

The present invention relates to a method of forming an alignment key of a semiconductor device, wherein spacers are formed on both sides of a hard mask layer pattern, the hard mask layer pattern is removed, and an alignment key is formed using the spacer as an etch mask. By doing so, it is possible to form a fine pattern of 40 nm or less while using existing equipment, thereby improving the alignment accuracy (alignment accuracy) to disclose a technique for improving the characteristics of the device.

Pattern size is decreasing with high integration of semiconductor devices. Accordingly, various approaches have been taken in terms of equipment and processes to form fine patterns. For example, a method of reducing the exposure wavelength or increasing the size of a lens has been mainly used for forming a fine pattern.

However, this method requires the development of equipment, which increases the equipment investment cost, and causes difficulties in operating the equipment.

Accordingly, as an alternative method of forming a fine pattern conforming to high integration even using existing equipment, a double exposure technique using two exposure masks and a SPT (Spacer Patterning Technology) method using three exposure masks have been proposed.

1A to 1C are cross-sectional views illustrating a method of forming an alignment key of a semiconductor device according to the prior art.

Referring to FIG. 1A, an amorphous carbon layer (a-Carbon) 110, a silicon oxynitride layer (SiON, 120), a hard mask layer 130, and an antireflection layer 140 are sequentially formed on the semiconductor substrate 100. .

Next, the photosensitive film pattern 150 which defines a pattern is formed.

Referring to FIG. 1B, the anti-reflection film 140 and the hard mask layer 130 are etched using the photoresist pattern 150 as a mask to form an anti-reflection film pattern (not shown) and a hard mask layer pattern 130a.

Next, the anti-reflection film pattern (not shown) and the photosensitive film pattern 150 are removed.

Referring to FIG. 1C, the silicon oxynitride layer 120 and the amorphous carbon layer 110 are sequentially etched using the hard mask layer pattern 130a as a mask to the silicon oxynitride layer pattern 120a and the amorphous carbon layer pattern 110a. An alignment key is formed.

Next, the hard mask layer pattern 130a is removed.

In the above-described method for forming an alignment key of a semiconductor device according to the related art, a photosensitive film pattern is formed using one exposure mask, and an alignment key is formed using the mask. Such direct patterning is 40 nm or less. There is a problem that is difficult to implement a fine pattern.

The present invention forms spacers on both sides of the hard mask layer pattern, removes the hard mask layer pattern, and forms an alignment key using the spacer as an etch mask. It is an object of the present invention to provide a method for forming an alignment key of a semiconductor device in which a pattern can be formed, thereby improving alignment accuracy and improving device characteristics.

Method for forming an alignment key of a semiconductor device according to the present invention

Forming an etched layer on the semiconductor substrate;

Forming a hard mask layer pattern on the etched layer;

Forming spacers on both sides of the hard mask layer pattern;

Removing the hard mask layer pattern;

And etching the lower etched layer under the spacers as a mask to form the alignment key by removing the spacers.

The etching layer is formed of an amorphous carbon layer (a-Cabon) and silicon oxynitride (SiON),

Forming a spacer layer on the entire spacer including the hard mask layer pattern;

Performing an etch back process to form spacers on both sides of the hard mask layer pattern;

The spacer is formed to a thickness of 10 ~ 100nm,

The spacer may be formed of a nitride film.

In addition, in the semiconductor element of the cell region and the peripheral circuit region,

Forming an etched layer and a hard mask layer on the semiconductor substrate;

Etching the hard mask layer to form a hard mask layer pattern;

Forming spacers on both sides of the hard mask layer pattern;

Removing the hard mask layer pattern;

Forming a photoresist pattern for opening the cell region;

Removing the photoresist pattern after performing an etching process in the cell region;

Etching the etched layer below using the spacer as a mask;

And removing the spacers to form an alignment key.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2G are cross-sectional views illustrating a method of forming an alignment key of a semiconductor device according to the present invention, and show only peripheral circuit regions.

Referring to FIG. 2A, an etched layer 225, a hard mask layer 230, and an anti-reflection film 240 are sequentially formed on the semiconductor substrate 200.

Here, the etched layer 225 may be formed in a stacked structure of a silicon oxynitride layer (SiON) 210 and an amorphous carbon layer (a-Carbon) 220.

Next, a first photoresist layer pattern 250 defining the same pattern as the cell region is formed on the anti-reflection layer 240.

In this case, the first photoresist layer pattern 250 is a mask for forming a pattern of the cell region, and the same pattern as that of the cell region pattern may be formed in the peripheral circuit region.

Referring to FIG. 2B, the anti-reflection film 240 and the hard mask layer 230 are etched using the first photoresist pattern 250 as a mask.

Next, the anti-reflection film 240 and the first photosensitive film pattern 250 are removed to form the hard mask layer pattern 230a.

Referring to FIG. 2C, a spacer layer (not shown) having a predetermined thickness is formed on the entire semiconductor substrate including the hard mask layer pattern 230a.

Here, the spacer layer (not shown) is formed of a nitride film, and the spacer layer (not shown) is preferably formed to a thickness of 10 ~ 100nm to secure the line width (Width) of the alignment key in the subsequent process.

Next, an spacer 255 is formed on both sides of the hard mask layer pattern 230a by performing an etch back process.

In this case, the spacer layer (not shown) formed on the hard mask layer pattern 230a and the silicon oxynitride layer 220 is removed to expose the top of the hard mask layer pattern 230a and the silicon oxynitride layer 220. It is desirable to.

Referring to FIG. 2D, the hard mask layer pattern 230a is removed.

At this time, while the hard mask layer pattern 230a is removed, only the spacers 255 formed on both sides of the hard mask layer pattern 230a are left, and the silicon oxynitride film 220 is exposed at the bottom.

Referring to FIG. 2E, the second photoresist layer pattern 260 is formed on the entire top of the spacer 255.

In this case, the second photoresist layer pattern 260 may form a second photoresist layer pattern 260 on the entire peripheral circuit region to prevent etching of the peripheral circuit region during the etching process performed in the cell region. It is desirable not to open this.

The reason why the peripheral circuit region is not opened is to prevent the silicon oxynitride film 220 from being etched twice by three etching processes performed by using three exposure masks.

Next, the second photoresist pattern 260 is removed after the second photo process of the cell region is performed.

Referring to FIG. 2F, the silicon oxynitride layer 220 is etched using the spacer 255 as an etch mask to form the silicon oxynitride layer pattern 220a.

Although not shown, a third photoresist pattern (not shown) for a third photolithography process is formed, and the third photoresist pattern (not shown) is formed of a silicon oxynitride layer (3) during the third photolithography process of the cell region. It is preferable that the peripheral circuit area is formed to be open to etch 220.

Referring to FIG. 2G, the spacer 255 is removed.

Next, the amorphous carbon layer 210 is etched using the silicon oxynitride layer pattern 220a as an etching mask to form the amorphous carbon layer pattern 210a.

Thereafter, the third photoresist layer pattern (not shown) is removed to form an alignment key 225a that is a stacked structure of the amorphous carbon layer pattern 210a and the silicon oxynitride layer pattern 220a.

Here, by forming an alignment key using a spacer patterning technology (SPT) process using the spacer 255 as an etch mask, it is possible to form a fine pattern of 40 nm or less while using existing equipment, and fine spacing. It is possible to improve the alignment accuracy by forming the alignment key in a pattern having a.

In the method of forming an alignment key of a semiconductor device according to the present invention, spacers are formed on both sides of a hard mask layer pattern, the hard mask layer pattern is removed, and an alignment key is formed by using the spacer as an etch mask. It is possible to form a fine pattern of, thereby improving the alignment accuracy has the effect of improving the characteristics of the device.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

Forming an etched layer on the semiconductor substrate; Forming a hard mask layer pattern on the etched layer; Forming spacers on both sides of the hard mask layer pattern; Removing the hard mask layer pattern; And Etching the lower layer to be etched using the spacers as a mask, and then removing the spacers to form an alignment key Alignment key forming method of a semiconductor device comprising a. The method of claim 1, And the etching layer is formed of an amorphous carbon layer (a-Cabon) and a silicon oxynitride layer (SiON). The method of claim 1, Forming a spacer layer on the entire spacer including the hard mask layer pattern; And Forming a spacer on both sides of the hard mask layer pattern by performing an etch back process Alignment key forming method of a semiconductor device comprising a. The method of claim 1, And forming the spacers with a thickness of about 10 nm to about 100 nm. The method of claim 1, And the spacer is formed of a nitride film. In the semiconductor device of the cell region and the peripheral circuit region, Forming an etching target layer and a hard mask layer on the semiconductor substrate; Etching the hard mask layer to form a hard mask layer pattern; Forming spacers on both sides of the hard mask layer pattern; Removing the hard mask layer pattern; Forming a photoresist pattern for opening the cell region; Removing the photoresist pattern after performing an etching process in the cell region; Etching the etched layer below using the spacer as a mask; And Removing the spacers to form an alignment key Alignment key forming method of a semiconductor device comprising a.

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